fbdev/matroxfb: Remove trailing whitespaces

+12 -12

drivers/video/fbdev/matrox/g450_pll.c

··· 258 258 unsigned int found = 0; 259 259 unsigned int idx; 260 260 unsigned int mnpfound = mnparray[0]; 261 - 261 + 262 262 for (idx = 0; idx < mnpcount; idx++) { 263 263 unsigned int sarray[3]; 264 264 unsigned int *sptr; 265 265 { 266 266 unsigned int mnp; 267 - 267 + 268 268 sptr = sarray; 269 269 mnp = mnparray[idx]; 270 270 if (mnp & 0x38) { ··· 277 277 } 278 278 while (sptr >= sarray) { 279 279 unsigned int mnp = *sptr--; 280 - 280 + 281 281 if (g450_testpll(minfo, mnp - 0x0300, pll) && 282 282 g450_testpll(minfo, mnp + 0x0300, pll) && 283 283 g450_testpll(minfo, mnp - 0x0200, pll) && ··· 310 310 struct matrox_pll_cache *ci, unsigned int mnp_key) 311 311 { 312 312 unsigned int i; 313 - 313 + 314 314 mnp_key &= G450_MNP_FREQBITS; 315 315 for (i = 0; i < ci->valid; i++) { 316 316 if (ci->data[i].mnp_key == mnp_key) { 317 317 unsigned int mnp; 318 - 318 + 319 319 mnp = ci->data[i].mnp_value; 320 320 if (i) { 321 321 memmove(ci->data + 1, ci->data, i * sizeof(*ci->data)); ··· 343 343 { 344 344 u_int8_t tmp, xpwrctrl; 345 345 unsigned long flags; 346 - 346 + 347 347 matroxfb_DAC_lock_irqsave(flags); 348 348 349 349 xpwrctrl = matroxfb_DAC_in(minfo, M1064_XPWRCTRL); ··· 375 375 } 376 376 { 377 377 u_int8_t misc; 378 - 378 + 379 379 misc = mga_inb(M_MISC_REG_READ) & ~0x0C; 380 380 switch (pll) { 381 381 case M_PIXEL_PLL_A: ··· 409 409 u_int8_t tmp; 410 410 unsigned int mnp; 411 411 unsigned long flags; 412 - 412 + 413 413 matroxfb_DAC_lock_irqsave(flags); 414 414 tmp = matroxfb_DAC_in(minfo, M1064_XPWRCTRL); 415 415 if (!(tmp & 2)) { 416 416 matroxfb_DAC_out(minfo, M1064_XPWRCTRL, tmp | 2); 417 417 } 418 - 418 + 419 419 mnp = matroxfb_DAC_in(minfo, M1064_XPIXPLLCM) << 16; 420 420 mnp |= matroxfb_DAC_in(minfo, M1064_XPIXPLLCN) << 8; 421 421 matroxfb_DAC_unlock_irqrestore(flags); ··· 441 441 delta = pll_freq_delta(fout, g450_vco2f(mnp, vco)); 442 442 for (idx = mnpcount; idx > 0; idx--) { 443 443 /* == is important; due to nextpll algorithm we get 444 - sorted equally good frequencies from lower VCO 444 + sorted equally good frequencies from lower VCO 445 445 frequency to higher - with <= lowest wins, while 446 446 with < highest one wins */ 447 447 if (delta <= deltaarray[idx-1]) { ··· 472 472 { 473 473 unsigned long flags; 474 474 unsigned int mnp; 475 - 475 + 476 476 matroxfb_DAC_lock_irqsave(flags); 477 477 mnp = g450_checkcache(minfo, ci, mnparray[0]); 478 478 if (mnp != NO_MORE_MNP) { ··· 495 495 unsigned int pll) 496 496 { 497 497 unsigned int* arr; 498 - 498 + 499 499 arr = kmalloc(sizeof(*arr) * MNP_TABLE_SIZE * 2, GFP_KERNEL); 500 500 if (arr) { 501 501 int r;

+23 -23

drivers/video/fbdev/matrox/matroxfb_DAC1064.c

··· 43 43 unsigned int p; 44 44 45 45 DBG(__func__) 46 - 46 + 47 47 /* only for devices older than G450 */ 48 48 49 49 fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p); 50 - 50 + 51 51 p = (1 << p) - 1; 52 52 if (fvco <= 100000) 53 53 ; ··· 169 169 struct matrox_hw_state *hw = &minfo->hw; 170 170 int pixelmnp; 171 171 int videomnp; 172 - 172 + 173 173 c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */ 174 174 c2_ctl |= 0x0001; /* Enable CRTC2 */ 175 175 hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */ ··· 192 192 } 193 193 c2_ctl |= 0x0006; /* Use video PLL */ 194 194 hw->DACreg[POS1064_XPWRCTRL] |= 0x02; 195 - 195 + 196 196 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); 197 197 matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL); 198 198 } ··· 200 200 hw->DACreg[POS1064_XPIXCLKCTRL] &= ~M1064_XPIXCLKCTRL_PLL_UP; 201 201 if (pixelmnp >= 0) { 202 202 hw->DACreg[POS1064_XPIXCLKCTRL] |= M1064_XPIXCLKCTRL_PLL_UP; 203 - 203 + 204 204 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); 205 205 matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C); 206 206 } ··· 303 303 poweroff TMDS. But if we boot with DFP connected, 304 304 TMDS generated clocks are used instead of ALL pixclocks 305 305 available... If someone knows which register 306 - handles it, please reveal this secret to me... */ 306 + handles it, please reveal this secret to me... */ 307 307 hw->DACreg[POS1064_XPWRCTRL] &= ~0x04; /* Poweroff TMDS */ 308 - #endif 308 + #endif 309 309 break; 310 310 } 311 311 /* Now set timming related variables... */ ··· 728 728 } else { 729 729 unsigned long flags; 730 730 unsigned int pwr; 731 - 731 + 732 732 matroxfb_DAC_lock_irqsave(flags); 733 733 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02; 734 734 outDAC1064(minfo, M1064_XPWRCTRL, pwr); 735 735 matroxfb_DAC_unlock_irqrestore(flags); 736 736 } 737 737 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); 738 - 738 + 739 739 /* switch clocks to their real PLL source(s) */ 740 740 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); 741 741 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3); ··· 748 748 /* disable memory refresh */ 749 749 minfo->hw.MXoptionReg &= ~0x001F8000; 750 750 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); 751 - 751 + 752 752 /* set memory interface parameters */ 753 753 minfo->hw.MXoptionReg &= ~0x00207E00; 754 754 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; 755 755 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); 756 756 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); 757 - 757 + 758 758 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); 759 - 759 + 760 760 /* first set up memory interface with disabled memory interface clocks */ 761 761 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U); 762 762 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); ··· 765 765 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U); 766 766 767 767 udelay(200); 768 - 768 + 769 769 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { 770 770 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000); 771 771 } 772 772 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000); 773 - 773 + 774 774 udelay(200); 775 - 775 + 776 776 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; 777 777 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); 778 - 778 + 779 779 /* value is written to memory chips only if old != new */ 780 780 mga_outl(M_PLNWT, 0); 781 781 mga_outl(M_PLNWT, ~0); 782 - 782 + 783 783 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) { 784 784 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core); 785 785 } 786 - 786 + 787 787 } 788 788 789 789 static void g450_preinit(struct matrox_fb_info *minfo) ··· 791 791 u_int32_t c2ctl; 792 792 u_int8_t curctl; 793 793 u_int8_t c1ctl; 794 - 794 + 795 795 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */ 796 796 minfo->hw.MXoptionReg &= 0xC0000100; 797 797 minfo->hw.MXoptionReg |= 0x00000020; ··· 805 805 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); 806 806 807 807 /* Init system clocks */ 808 - 808 + 809 809 /* stop crtc2 */ 810 810 c2ctl = mga_inl(M_C2CTL); 811 811 mga_outl(M_C2CTL, c2ctl & ~1); ··· 818 818 819 819 g450_mclk_init(minfo); 820 820 g450_memory_init(minfo); 821 - 821 + 822 822 /* set legacy VGA clock sources for DOSEmu or VMware... */ 823 823 matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A); 824 824 matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B); 825 825 826 826 /* restore crtc1 */ 827 827 mga_setr(M_SEQ_INDEX, 1, c1ctl); 828 - 828 + 829 829 /* restore cursor */ 830 830 outDAC1064(minfo, M1064_XCURCTRL, curctl); 831 831 832 832 /* restore crtc2 */ 833 833 mga_outl(M_C2CTL, c2ctl); 834 - 834 + 835 835 return; 836 836 } 837 837

+30 -30

drivers/video/fbdev/matrox/matroxfb_g450.c

··· 32 32 #define WLMAX 0x3FF 33 33 34 34 static const struct mctl g450_controls[] = 35 - { { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER, 35 + { { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER, 36 36 "brightness", 37 - 0, WLMAX-BLMIN, 1, 370-BLMIN, 37 + 0, WLMAX-BLMIN, 1, 370-BLMIN, 38 38 0, 39 39 }, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) }, 40 - { { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER, 40 + { { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER, 41 41 "contrast", 42 - 0, 1023, 1, 127, 42 + 0, 1023, 1, 127, 43 43 0, 44 44 }, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) }, 45 45 { { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER, 46 46 "saturation", 47 - 0, 255, 1, 165, 47 + 0, 255, 1, 165, 48 48 0, 49 49 }, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) }, 50 50 { { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER, 51 51 "hue", 52 - 0, 255, 1, 0, 52 + 0, 255, 1, 0, 53 53 0, 54 54 }, offsetof(struct matrox_fb_info, altout.tvo_params.hue) }, 55 55 { { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN, 56 56 "test output", 57 - 0, 1, 1, 0, 57 + 0, 1, 1, 0, 58 58 0, 59 59 }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) }, 60 60 }; ··· 89 89 static void tvo_fill_defaults(struct matrox_fb_info *minfo) 90 90 { 91 91 unsigned int i; 92 - 92 + 93 93 for (i = 0; i < G450CTRLS; i++) { 94 94 *get_ctrl_ptr(minfo, i) = g450_controls[i].desc.default_value; 95 95 } ··· 99 99 { 100 100 unsigned long flags; 101 101 int val; 102 - 102 + 103 103 matroxfb_DAC_lock_irqsave(flags); 104 104 matroxfb_DAC_out(minfo, 0x87, reg); 105 105 val = matroxfb_DAC_in(minfo, 0x88); ··· 141 141 142 142 static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) { 143 143 int i; 144 - 144 + 145 145 i = get_ctrl_id(p->id); 146 146 if (i >= 0) { 147 147 *p = g450_controls[i].desc; 148 148 return 0; 149 149 } 150 150 if (i == -ENOENT) { 151 - static const struct v4l2_queryctrl disctrl = 151 + static const struct v4l2_queryctrl disctrl = 152 152 { .flags = V4L2_CTRL_FLAG_DISABLED }; 153 - 153 + 154 154 i = p->id; 155 155 *p = disctrl; 156 156 p->id = i; ··· 163 163 static int g450_set_ctrl(void* md, struct v4l2_control *p) { 164 164 int i; 165 165 struct matrox_fb_info *minfo = md; 166 - 166 + 167 167 i = get_ctrl_id(p->id); 168 168 if (i < 0) return -EINVAL; 169 169 ··· 209 209 } 210 210 break; 211 211 } 212 - 212 + 213 213 214 214 return 0; 215 215 } ··· 217 217 static int g450_get_ctrl(void* md, struct v4l2_control *p) { 218 218 int i; 219 219 struct matrox_fb_info *minfo = md; 220 - 220 + 221 221 i = get_ctrl_id(p->id); 222 222 if (i < 0) return -EINVAL; 223 223 p->value = *get_ctrl_ptr(minfo, i); ··· 247 247 unsigned long long piic; 248 248 int mnp; 249 249 int over; 250 - 250 + 251 251 r->regs[0x80] = 0x03; /* | 0x40 for SCART */ 252 252 253 253 hvis = ((mt->HDisplay << 1) + 3) & ~3; 254 - 254 + 255 255 if (hvis >= 2048) { 256 256 hvis = 2044; 257 257 } 258 - 258 + 259 259 piic = 1000000000ULL * hvis; 260 260 do_div(piic, outd->h_vis); 261 261 262 262 dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic); 263 - 263 + 264 264 mnp = matroxfb_g450_setclk(minfo, piic, M_VIDEO_PLL); 265 - 265 + 266 266 mt->mnp = mnp; 267 267 mt->pixclock = g450_mnp2f(minfo, mnp); 268 268 ··· 275 275 piic = outd->chromasc; 276 276 do_div(piic, mt->pixclock); 277 277 chromasc = piic; 278 - 278 + 279 279 dprintk(KERN_DEBUG "Chroma is %08X\n", chromasc); 280 280 281 281 r->regs[0] = piic >> 24; ··· 287 287 hsl = (((outd->h_sync + pixclock) / pixclock)) & ~1; 288 288 hlen = hvis + hfp + hsl + hbp; 289 289 over = hlen & 0x0F; 290 - 290 + 291 291 dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen); 292 292 293 293 if (over) { ··· 310 310 r->regs[0x2C] = hfp; 311 311 r->regs[0x31] = hvis / 8; 312 312 r->regs[0x32] = hvis & 7; 313 - 313 + 314 314 dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, hlen); 315 315 316 316 r->regs[0x84] = 1; /* x sync point */ 317 317 r->regs[0x85] = 0; 318 318 hvis = hvis >> 1; 319 319 hlen = hlen >> 1; 320 - 320 + 321 321 dprintk(KERN_DEBUG "hlen=%u hvis=%u\n", hlen, hvis); 322 322 323 323 mt->interlaced = 1; ··· 332 332 unsigned int vtotal; 333 333 unsigned int vsyncend; 334 334 unsigned int vdisplay; 335 - 335 + 336 336 vtotal = mt->VTotal; 337 337 vsyncend = mt->VSyncEnd; 338 338 vdisplay = mt->VDisplay; 339 339 if (vtotal < outd->v_total) { 340 340 unsigned int yovr = outd->v_total - vtotal; 341 - 341 + 342 342 vsyncend += yovr >> 1; 343 343 } else if (vtotal > outd->v_total) { 344 344 vdisplay = outd->v_total - 4; ··· 350 350 r->regs[0x33] = upper - 1; /* upper blanking */ 351 351 r->regs[0x82] = upper; /* y sync point */ 352 352 r->regs[0x83] = upper >> 8; 353 - 353 + 354 354 mt->VDisplay = vdisplay; 355 355 mt->VSyncStart = outd->v_total - 2; 356 356 mt->VSyncEnd = outd->v_total; ··· 509 509 LR(0x80); 510 510 LR(0x82); LR(0x83); 511 511 LR(0x84); LR(0x85); 512 - 512 + 513 513 cve2_set_reg(minfo, 0x3E, 0x01); 514 - 514 + 515 515 for (i = 0; i < 0x3E; i++) { 516 516 LR(i); 517 517 } ··· 558 558 559 559 static int matroxfb_g450_program(void* md) { 560 560 struct matrox_fb_info *minfo = md; 561 - 561 + 562 562 if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) { 563 563 cve2_init_TV(minfo, &minfo->hw.maven); 564 564 }

+10 -10

drivers/video/fbdev/matrox/matroxfb_misc.c

··· 390 390 391 391 static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) { 392 392 unsigned int b0 = readb(pins); 393 - 393 + 394 394 if (b0 == 0x2E && readb(pins+1) == 0x41) { 395 395 unsigned int pins_len = readb(pins+2); 396 396 unsigned int i; ··· 426 426 427 427 static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) { 428 428 unsigned int pcir_offset; 429 - 429 + 430 430 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8); 431 431 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 && 432 432 readb(vbios + pcir_offset ) == 'P' && ··· 451 451 452 452 static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) { 453 453 unsigned char b; 454 - 454 + 455 455 b = readb(vbios + 0x7FF1); 456 456 if (b == 0xFF) { 457 457 b = 0; ··· 461 461 462 462 static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) { 463 463 unsigned int i; 464 - 464 + 465 465 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */ 466 466 bd->output.tvout = 0; 467 467 if (readb(vbios + 0x1D) != 'I' || ··· 472 472 } 473 473 for (i = 0x2D; i < 0x2D + 128; i++) { 474 474 unsigned char b = readb(vbios + i); 475 - 475 + 476 476 if (b == '(' && readb(vbios + i + 1) == 'V') { 477 477 if (readb(vbios + i + 6) == 'T' && 478 478 readb(vbios + i + 7) == 'V' && ··· 488 488 489 489 static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) { 490 490 unsigned int pins_offset; 491 - 491 + 492 492 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) { 493 493 return; 494 494 } ··· 648 648 const struct matrox_bios *bd) 649 649 { 650 650 unsigned int mult; 651 - 651 + 652 652 mult = bd->pins[4]?8000:6000; 653 - 653 + 654 654 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; 655 655 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult; 656 656 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult; ··· 770 770 u32 biosbase; 771 771 u32 fbbase; 772 772 struct pci_dev *pdev = minfo->pcidev; 773 - 773 + 774 774 memset(&minfo->bios, 0, sizeof(minfo->bios)); 775 775 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt); 776 776 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM); ··· 790 790 } else { 791 791 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8); 792 792 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8); 793 - 793 + 794 794 if (ven != pdev->vendor || dev != pdev->device) { 795 795 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n", 796 796 ven, dev, pdev->vendor, pdev->device);

Configure Feed

Configure Feed