tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pci-v4.20-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:

- Fix a link speed checking interface that broke PCIe gen3 cards in
gen1 slots (Mikulas Patocka)

- Fix an imx6 link training error (Trent Piepho)

- Fix a layerscape outbound window accessor calling error (Hou
Zhiqiang)

- Fix a DesignWare endpoint MSI-X address calculation error (Gustavo
Pimentel)

* tag 'pci-v4.20-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: Fix incorrect value returned from pcie_get_speed_cap()
PCI: dwc: Fix MSI-X EP framework address calculation bug
PCI: layerscape: Fix wrong invocation of outbound window disable accessor
PCI: imx6: Fix link training status detection in link up check

Linus Torvalds c734b425 d8f190ee

+13 -24
+1 -9
drivers/pci/controller/dwc/pci-imx6.c
··· 81 81 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) 82 82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) 83 83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) 84 - #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) 85 - #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) 86 84 87 85 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 88 86 #define PCIE_PHY_CTRL_DATA_LOC 0 ··· 709 711 return 0; 710 712 } 711 713 712 - static int imx6_pcie_link_up(struct dw_pcie *pci) 713 - { 714 - return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) & 715 - PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; 716 - } 717 - 718 714 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 719 715 .host_init = imx6_pcie_host_init, 720 716 }; ··· 741 749 } 742 750 743 751 static const struct dw_pcie_ops dw_pcie_ops = { 744 - .link_up = imx6_pcie_link_up, 752 + /* No special ops needed, but pcie-designware still expects this struct */ 745 753 }; 746 754 747 755 #ifdef CONFIG_PM_SLEEP
+1 -1
drivers/pci/controller/dwc/pci-layerscape.c
··· 88 88 int i; 89 89 90 90 for (i = 0; i < PCIE_IATU_NUM; i++) 91 - dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i); 91 + dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); 92 92 } 93 93 94 94 static int ls1021_pcie_link_up(struct dw_pcie *pci)
-1
drivers/pci/controller/dwc/pcie-designware-ep.c
··· 440 440 tbl_offset = dw_pcie_readl_dbi(pci, reg); 441 441 bir = (tbl_offset & PCI_MSIX_TABLE_BIR); 442 442 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 443 - tbl_offset >>= 3; 444 443 445 444 reg = PCI_BASE_ADDRESS_0 + (4 * bir); 446 445 bar_addr_upper = 0;
+11 -13
drivers/pci/pci.c
··· 5556 5556 u32 lnkcap2, lnkcap; 5557 5557 5558 5558 /* 5559 - * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link 5560 - * Speeds Vector in Link Capabilities 2 when supported, falling 5561 - * back to Max Link Speed in Link Capabilities otherwise. 5559 + * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The 5560 + * implementation note there recommends using the Supported Link 5561 + * Speeds Vector in Link Capabilities 2 when supported. 5562 + * 5563 + * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software 5564 + * should use the Supported Link Speeds field in Link Capabilities, 5565 + * where only 2.5 GT/s and 5.0 GT/s speeds were defined. 5562 5566 */ 5563 5567 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); 5564 5568 if (lnkcap2) { /* PCIe r3.0-compliant */ ··· 5578 5574 } 5579 5575 5580 5576 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 5581 - if (lnkcap) { 5582 - if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 5583 - return PCIE_SPEED_16_0GT; 5584 - else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 5585 - return PCIE_SPEED_8_0GT; 5586 - else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 5587 - return PCIE_SPEED_5_0GT; 5588 - else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 5589 - return PCIE_SPEED_2_5GT; 5590 - } 5577 + if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) 5578 + return PCIE_SPEED_5_0GT; 5579 + else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) 5580 + return PCIE_SPEED_2_5GT; 5591 5581 5592 5582 return PCI_SPEED_UNKNOWN; 5593 5583 }