Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Remove state verification for LT PHY fields
Currently we do state verification for all VDR Registers.
Remove LT PHY State verification for all VDR register fields other
than VDR0_CONFIG and VDR2_CONFIG. The reason being that VDR0_CONFIG
and VDR2_CONFIG are the only reliable shadow register which hold onto
their values over the course of power gatings which happen internally
due to features like PSR/PR.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260105055937.136522-1-suraj.kandpal@intel.com
+7
-23
+7
-23
drivers/gpu/drm/i915/display/intel_lt_phy.c
+7
-23
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
2259
2259
struct intel_encoder *encoder;
2260
2260
struct intel_lt_phy_pll_state pll_hw_state = {};
2261
2261
const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
2262
-
int clock;
2263
-
int i, j;
2264
2262
2265
2263
if (DISPLAY_VER(display) < 35)
2266
2264
return;
···
2273
2275
2274
2276
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
2275
2277
intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
2276
-
clock = intel_lt_phy_calc_port_clock(encoder, new_crtc_state);
2277
2278
2278
2279
dig_port = enc_to_dig_port(encoder);
2279
2280
if (intel_tc_port_in_tbt_alt_mode(dig_port))
2280
2281
return;
2281
2282
2282
-
INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock,
2283
-
"[CRTC:%d:%s] mismatch in LT PHY: Register CLOCK (expected %d, found %d)",
2283
+
INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],
2284
+
"[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)",
2284
2285
crtc->base.base.id, crtc->base.name,
2285
-
pll_sw_state->clock, pll_hw_state.clock);
2286
-
2287
-
for (i = 0; i < 3; i++) {
2288
-
INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i] != pll_sw_state->config[i],
2289
-
"[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG%d: (expected 0x%04x, found 0x%04x)",
2290
-
crtc->base.base.id, crtc->base.name, i,
2291
-
pll_sw_state->config[i], pll_hw_state.config[i]);
2292
-
}
2293
-
2294
-
for (i = 0; i <= 12; i++) {
2295
-
for (j = 3; j >= 0; j--)
2296
-
INTEL_DISPLAY_STATE_WARN(display,
2297
-
pll_hw_state.data[i][j] !=
2298
-
pll_sw_state->data[i][j],
2299
-
"[CRTC:%d:%s] mismatch in LT PHY PLL DATA[%d][%d]: (expected 0x%04x, found 0x%04x)",
2300
-
crtc->base.base.id, crtc->base.name, i, j,
2301
-
pll_sw_state->data[i][j], pll_hw_state.data[i][j]);
2302
-
}
2286
+
pll_sw_state->config[0], pll_hw_state.config[0]);
2287
+
INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],
2288
+
"[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)",
2289
+
crtc->base.base.id, crtc->base.name,
2290
+
pll_sw_state->config[2], pll_hw_state.config[2]);
2303
2291
}
2304
2292
2305
2293
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,