Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'samsung-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.13
1. Add new SoC Samsung Exynos8895 and new board using it: Samsung
Galaxy S8 (SM-G950F) mobile phone. Only small support so far:
CPUs (Samsung Mongoose M2), main clock controllers (FSYS, PERIC,
TOP), pin controllers, SPI for cameras, timers.
2. Add new SoC Samsung Exynos990 and new board using it: Samsung
Galaxy Note20 5G (c1s/SM-N981B) mobile phone. Only minimal support
so far: CPUs (Samsung Mongoose M5), pin controllers, timers.
3. Prepare for adding new SoC Samsung Exynos9810 - add bindings. The
SoC DTSI was not yet ready, but it is posted on the mailing lists so
should come soon.
4. ExynosAutov920: Add several clock controllers.
* tag 'samsung-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
dt-bindings: arm: samsung: Document Exynos9810 and starlte board binding
dt-bindings: soc: samsung: exynos-pmu: Add exynos9810 compatible
dt-bindings: arm: cpus: Add Samsung Mongoose M3
arm64: dts: exynos8895: Add spi_0/1 nodes
arm64: dts: exynos8895: Add Multi Core Timer (MCT) node
arm64: dts: exynos8895: Add clock management unit nodes
dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible
dt-bindings: clock: samsung: Add Exynos8895 SoC
arm64: dts: exynos: Add initial support for Samsung Galaxy Note20 5G (c1s)
arm64: dts: exynos: Add initial support for the Exynos 990 SoC
dt-bindings: arm: samsung: samsung-boards: Add bindings for Exynos 990 boards
dt-bindings: arm: cpus: Add Samsung Mongoose M5
arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes
dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
arm64: dts: exynos: Add initial support for Samsung Galaxy S8
arm64: dts: exynos: Add initial support for exynos8895 SoC
dt-bindings: soc: samsung: exynos-pmu: Add exynos8895 compatible
dt-bindings: arm: samsung: Document dreamlte board binding
dt-bindings: arm: cpus: Add Samsung Mongoose M2
Link: https://lore.kernel.org/r/20241029081002.21106-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+4983
+3
Documentation/devicetree/bindings/arm/cpus.yaml
+3
Documentation/devicetree/bindings/arm/cpus.yaml
+18
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+18
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
···
224
224
- winlink,e850-96 # WinLink E850-96
225
225
- const: samsung,exynos850
226
226
227
+
- description: Exynos8895 based boards
228
+
items:
229
+
- enum:
230
+
- samsung,dreamlte # Samsung Galaxy S8 (SM-G950F)
231
+
- const: samsung,exynos8895
232
+
233
+
- description: Exynos9810 based boards
234
+
items:
235
+
- enum:
236
+
- samsung,starlte # Samsung Galaxy S9 (SM-G960F)
237
+
- const: samsung,exynos9810
238
+
239
+
- description: Exynos990 based boards
240
+
items:
241
+
- enum:
242
+
- samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
243
+
- const: samsung,exynos990
244
+
227
245
- description: Exynos Auto v9 based boards
228
246
items:
229
247
- enum:
+239
Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml
+239
Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung Exynos8895 SoC clock controller
8
+
9
+
maintainers:
10
+
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
11
+
- Chanwoo Choi <cw00.choi@samsung.com>
12
+
- Krzysztof Kozlowski <krzk@kernel.org>
13
+
14
+
description: |
15
+
Exynos8895 clock controller is comprised of several CMU units, generating
16
+
clocks for different domains. Those CMU units are modeled as separate device
17
+
tree nodes, and might depend on each other. The root clock in that root tree
18
+
is an external clock: OSCCLK (26 MHz). This external clock must be defined
19
+
as a fixed-rate clock in dts.
20
+
21
+
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
22
+
dividers; all other clocks of function blocks (other CMUs) are usually
23
+
derived from CMU_TOP.
24
+
25
+
Each clock is assigned an identifier and client nodes can use this identifier
26
+
to specify the clock which they consume. All clocks available for usage
27
+
in clock consumer nodes are defined as preprocessor macros in
28
+
'include/dt-bindings/clock/samsung,exynos8895.h' header.
29
+
30
+
properties:
31
+
compatible:
32
+
enum:
33
+
- samsung,exynos8895-cmu-fsys0
34
+
- samsung,exynos8895-cmu-fsys1
35
+
- samsung,exynos8895-cmu-peric0
36
+
- samsung,exynos8895-cmu-peric1
37
+
- samsung,exynos8895-cmu-peris
38
+
- samsung,exynos8895-cmu-top
39
+
40
+
clocks:
41
+
minItems: 1
42
+
maxItems: 16
43
+
44
+
clock-names:
45
+
minItems: 1
46
+
maxItems: 16
47
+
48
+
"#clock-cells":
49
+
const: 1
50
+
51
+
reg:
52
+
maxItems: 1
53
+
54
+
required:
55
+
- compatible
56
+
- clocks
57
+
- clock-names
58
+
- reg
59
+
- "#clock-cells"
60
+
61
+
allOf:
62
+
- if:
63
+
properties:
64
+
compatible:
65
+
contains:
66
+
const: samsung,exynos8895-cmu-fsys0
67
+
68
+
then:
69
+
properties:
70
+
clocks:
71
+
items:
72
+
- description: External reference clock (26 MHz)
73
+
- description: CMU_FSYS0 BUS clock (from CMU_TOP)
74
+
- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
75
+
- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
76
+
- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
77
+
- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
78
+
79
+
clock-names:
80
+
items:
81
+
- const: oscclk
82
+
- const: bus
83
+
- const: dpgtc
84
+
- const: mmc
85
+
- const: ufs
86
+
- const: usbdrd30
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
const: samsung,exynos8895-cmu-fsys1
93
+
94
+
then:
95
+
properties:
96
+
clocks:
97
+
items:
98
+
- description: External reference clock (26 MHz)
99
+
- description: CMU_FSYS1 BUS clock (from CMU_TOP)
100
+
- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
101
+
- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
102
+
- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
103
+
104
+
clock-names:
105
+
items:
106
+
- const: oscclk
107
+
- const: bus
108
+
- const: pcie
109
+
- const: ufs
110
+
- const: mmc
111
+
112
+
- if:
113
+
properties:
114
+
compatible:
115
+
contains:
116
+
const: samsung,exynos8895-cmu-peric0
117
+
118
+
then:
119
+
properties:
120
+
clocks:
121
+
items:
122
+
- description: External reference clock (26 MHz)
123
+
- description: CMU_PERIC0 BUS clock (from CMU_TOP)
124
+
- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
125
+
- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
126
+
- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
127
+
- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
128
+
- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
129
+
130
+
clock-names:
131
+
items:
132
+
- const: oscclk
133
+
- const: bus
134
+
- const: uart
135
+
- const: usi0
136
+
- const: usi1
137
+
- const: usi2
138
+
- const: usi3
139
+
140
+
- if:
141
+
properties:
142
+
compatible:
143
+
contains:
144
+
const: samsung,exynos8895-cmu-peric1
145
+
146
+
then:
147
+
properties:
148
+
clocks:
149
+
items:
150
+
- description: External reference clock (26 MHz)
151
+
- description: CMU_PERIC1 BUS clock (from CMU_TOP)
152
+
- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
153
+
- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
154
+
- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
155
+
- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
156
+
- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
157
+
- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
158
+
- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
159
+
- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
160
+
- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
161
+
- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
162
+
- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
163
+
- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
164
+
- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
165
+
- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
166
+
167
+
clock-names:
168
+
items:
169
+
- const: oscclk
170
+
- const: bus
171
+
- const: speedy
172
+
- const: cam0
173
+
- const: cam1
174
+
- const: uart
175
+
- const: usi4
176
+
- const: usi5
177
+
- const: usi6
178
+
- const: usi7
179
+
- const: usi8
180
+
- const: usi9
181
+
- const: usi10
182
+
- const: usi11
183
+
- const: usi12
184
+
- const: usi13
185
+
186
+
- if:
187
+
properties:
188
+
compatible:
189
+
contains:
190
+
const: samsung,exynos8895-cmu-peris
191
+
192
+
then:
193
+
properties:
194
+
clocks:
195
+
items:
196
+
- description: External reference clock (26 MHz)
197
+
- description: CMU_PERIS BUS clock (from CMU_TOP)
198
+
199
+
clock-names:
200
+
items:
201
+
- const: oscclk
202
+
- const: bus
203
+
204
+
- if:
205
+
properties:
206
+
compatible:
207
+
contains:
208
+
const: samsung,exynos8895-cmu-top
209
+
210
+
then:
211
+
properties:
212
+
clocks:
213
+
items:
214
+
- description: External reference clock (26 MHz)
215
+
216
+
clock-names:
217
+
items:
218
+
- const: oscclk
219
+
220
+
additionalProperties: false
221
+
222
+
examples:
223
+
- |
224
+
#include <dt-bindings/clock/samsung,exynos8895.h>
225
+
226
+
cmu_fsys1: clock-controller@11400000 {
227
+
compatible = "samsung,exynos8895-cmu-fsys1";
228
+
reg = <0x11400000 0x8000>;
229
+
#clock-cells = <1>;
230
+
231
+
clocks = <&oscclk>,
232
+
<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
233
+
<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
234
+
<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
235
+
<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
236
+
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
237
+
};
238
+
239
+
...
+2
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+2
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+2
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+2
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
···
33
33
- samsung,exynos5420-mct
34
34
- samsung,exynos5433-mct
35
35
- samsung,exynos850-mct
36
+
- samsung,exynos8895-mct
36
37
- tesla,fsd-mct
37
38
- const: samsung,exynos4210-mct
38
39
···
134
133
- samsung,exynos5420-mct
135
134
- samsung,exynos5433-mct
136
135
- samsung,exynos850-mct
136
+
- samsung,exynos8895-mct
137
137
then:
138
138
properties:
139
139
interrupts:
+2
arch/arm64/boot/dts/exynos/Makefile
+2
arch/arm64/boot/dts/exynos/Makefile
+126
arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts
+126
arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung Galaxy S8 (dreamlte/SM-G950F) device tree source
4
+
*
5
+
* Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6
+
*/
7
+
8
+
/dts-v1/;
9
+
#include "exynos8895.dtsi"
10
+
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/input/input.h>
12
+
#include <dt-bindings/interrupt-controller/irq.h>
13
+
14
+
/ {
15
+
model = "Samsung Galaxy S8 (SM-G950F)";
16
+
compatible = "samsung,dreamlte", "samsung,exynos8895";
17
+
chassis-type = "handset";
18
+
19
+
chosen {
20
+
#address-cells = <2>;
21
+
#size-cells = <1>;
22
+
ranges;
23
+
24
+
framebuffer: framebuffer@cc000000 {
25
+
compatible = "simple-framebuffer";
26
+
reg = <0 0xcc000000 (1440 * 2960 * 4)>;
27
+
width = <1440>;
28
+
height = <2960>;
29
+
stride = <(1440 * 4)>;
30
+
format = "a8r8g8b8";
31
+
};
32
+
};
33
+
34
+
memory@80000000 {
35
+
device_type = "memory";
36
+
reg = <0x0 0x80000000 0x3c800000>,
37
+
<0x0 0xc0000000 0x40000000>,
38
+
<0x8 0x80000000 0x80000000>;
39
+
};
40
+
41
+
reserved-memory {
42
+
#address-cells = <2>;
43
+
#size-cells = <1>;
44
+
ranges;
45
+
46
+
ramoops@92000000 {
47
+
compatible = "ramoops";
48
+
reg = <0 0x92000000 0x8000>;
49
+
record-size = <0x4000>;
50
+
console-size = <0x4000>;
51
+
};
52
+
53
+
cont_splash_mem: framebuffer@cc000000 {
54
+
reg = <0 0xcc000000 (1440 * 2960 * 4)>;
55
+
no-map;
56
+
};
57
+
};
58
+
59
+
gpio-keys {
60
+
compatible = "gpio-keys";
61
+
62
+
pinctrl-0 = <&key_power &key_voldown &key_volup &key_wink>;
63
+
pinctrl-names = "default";
64
+
65
+
power-key {
66
+
label = "Power";
67
+
linux,code = <KEY_POWER>;
68
+
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
69
+
wakeup-source;
70
+
};
71
+
72
+
voldown-key {
73
+
label = "Volume Down";
74
+
linux,code = <KEY_VOLUMEDOWN>;
75
+
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
76
+
};
77
+
78
+
volup-key {
79
+
label = "Volume Up";
80
+
linux,code = <KEY_VOLUMEUP>;
81
+
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82
+
};
83
+
84
+
/* Typically used for Bixby. Map it as a camera button for now */
85
+
wink-key {
86
+
label = "Camera";
87
+
linux,code = <KEY_CAMERA>;
88
+
gpios = <&gpa0 6 GPIO_ACTIVE_LOW>;
89
+
wakeup-source;
90
+
};
91
+
};
92
+
};
93
+
94
+
&oscclk {
95
+
clock-frequency = <26000000>;
96
+
};
97
+
98
+
&pinctrl_alive {
99
+
key_power: key-power-pins {
100
+
samsung,pins = "gpa2-4";
101
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
102
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
103
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
104
+
};
105
+
106
+
key_voldown: key-voldown-pins {
107
+
samsung,pins = "gpa0-4";
108
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
109
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
110
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
111
+
};
112
+
113
+
key_volup: key-volup-pins {
114
+
samsung,pins = "gpa0-3";
115
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
116
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
117
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
118
+
};
119
+
120
+
key_wink: key-wink-pins {
121
+
samsung,pins = "gpa0-6";
122
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
123
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
124
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
125
+
};
126
+
};
+1094
arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi
+1094
arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source
4
+
*
5
+
* Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
#include "exynos-pinctrl.h"
10
+
11
+
&pinctrl_abox {
12
+
gph0: gph0-gpio-bank {
13
+
gpio-controller;
14
+
#gpio-cells = <2>;
15
+
16
+
interrupt-controller;
17
+
#interrupt-cells = <2>;
18
+
};
19
+
20
+
gph1: gph1-gpio-bank {
21
+
gpio-controller;
22
+
#gpio-cells = <2>;
23
+
24
+
interrupt-controller;
25
+
#interrupt-cells = <2>;
26
+
};
27
+
28
+
gph3: gph3-gpio-bank {
29
+
gpio-controller;
30
+
#gpio-cells = <2>;
31
+
32
+
interrupt-controller;
33
+
#interrupt-cells = <2>;
34
+
};
35
+
};
36
+
37
+
&pinctrl_alive {
38
+
gpa0: gpa0-gpio-bank {
39
+
gpio-controller;
40
+
#gpio-cells = <2>;
41
+
42
+
interrupt-controller;
43
+
#interrupt-cells = <2>;
44
+
interrupt-parent = <&gic>;
45
+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
46
+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
47
+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
48
+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
49
+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
50
+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
51
+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
52
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
53
+
};
54
+
55
+
gpa1: gpa1-gpio-bank {
56
+
gpio-controller;
57
+
#gpio-cells = <2>;
58
+
59
+
interrupt-controller;
60
+
#interrupt-cells = <2>;
61
+
interrupt-parent = <&gic>;
62
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
63
+
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
64
+
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
65
+
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
66
+
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
67
+
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
68
+
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
69
+
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
70
+
};
71
+
72
+
gpa2: gpa2-gpio-bank {
73
+
gpio-controller;
74
+
#gpio-cells = <2>;
75
+
76
+
interrupt-controller;
77
+
#interrupt-cells = <2>;
78
+
};
79
+
80
+
gpa3: gpa3-gpio-bank {
81
+
gpio-controller;
82
+
#gpio-cells = <2>;
83
+
84
+
interrupt-controller;
85
+
#interrupt-cells = <2>;
86
+
};
87
+
88
+
gpa4: gpa4-gpio-bank {
89
+
gpio-controller;
90
+
#gpio-cells = <2>;
91
+
};
92
+
93
+
bt_hostwake: bt-hostwake-pins {
94
+
samsung,pins = "gpa2-3";
95
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
96
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
97
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
98
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
99
+
};
100
+
101
+
pcie_wake: pcie-wake-pins {
102
+
samsung,pins = "gpa3-3";
103
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
104
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
105
+
};
106
+
107
+
uart1_bus: uart1-bus-pins {
108
+
samsung,pins = "gpa4-4", "gpa4-3", "gpa4-2", "gpa4-1";
109
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
110
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
111
+
};
112
+
113
+
wlan_host_wake: wlan-host-wake-pins {
114
+
samsung,pins = "gpa0-7";
115
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
116
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
117
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
118
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>;
119
+
};
120
+
};
121
+
122
+
&pinctrl_busc {
123
+
gpb2: gpb2-gpio-bank {
124
+
gpio-controller;
125
+
#gpio-cells = <2>;
126
+
127
+
interrupt-controller;
128
+
#interrupt-cells = <2>;
129
+
};
130
+
131
+
hsi2c0_bus: hsi2c0-bus-pins {
132
+
samsung,pins = "gpb2-1", "gpb2-0";
133
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
134
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
135
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
136
+
};
137
+
138
+
speedy_bus: speedy-bus-pins {
139
+
samsung,pins = "gpb2-0";
140
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
141
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
142
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
143
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
144
+
};
145
+
};
146
+
147
+
&pinctrl_fsys0 {
148
+
gpi0: gpi0-gpio-bank {
149
+
gpio-controller;
150
+
#gpio-cells = <2>;
151
+
152
+
interrupt-controller;
153
+
#interrupt-cells = <2>;
154
+
};
155
+
156
+
gpi1: gpi1-gpio-bank {
157
+
gpio-controller;
158
+
#gpio-cells = <2>;
159
+
160
+
interrupt-controller;
161
+
#interrupt-cells = <2>;
162
+
};
163
+
164
+
ufs_rst_n: ufs-rst-n-pins {
165
+
samsung,pins = "gpi0-1";
166
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
167
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
168
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
169
+
};
170
+
171
+
ufs_refclk_out: ufs-refclk-out-pins {
172
+
samsung,pins = "gpi0-0";
173
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
174
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
175
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
176
+
};
177
+
};
178
+
179
+
&pinctrl_fsys1 {
180
+
gpj0: gpj0-gpio-bank {
181
+
gpio-controller;
182
+
#gpio-cells = <2>;
183
+
184
+
interrupt-controller;
185
+
#interrupt-cells = <2>;
186
+
};
187
+
188
+
gpj1: gpj1-gpio-bank {
189
+
gpio-controller;
190
+
#gpio-cells = <2>;
191
+
192
+
interrupt-controller;
193
+
#interrupt-cells = <2>;
194
+
};
195
+
196
+
bt_btwake: bt-btwake-pins {
197
+
samsung,pins = "gpj1-4";
198
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
199
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
200
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
201
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
202
+
};
203
+
204
+
bt_en: bt-en-pins {
205
+
samsung,pins ="gpj1-7";
206
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
207
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
208
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
209
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
210
+
};
211
+
212
+
cfg_wlanen: cfg-wlanen-pins {
213
+
samsung,pins = "gpj1-3";
214
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
215
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
216
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
217
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
218
+
};
219
+
220
+
sd2_clk: sd2-clk-pins {
221
+
samsung,pins = "gpj0-0";
222
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
223
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
224
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
225
+
};
226
+
227
+
sd2_cmd: sd2-cmd-pins {
228
+
samsung,pins = "gpj0-1";
229
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
230
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
231
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV3>;
232
+
};
233
+
234
+
sd2_bus1: sd2-bus-width1-pins {
235
+
samsung,pins = "gpj0-2";
236
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
237
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
238
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV3>;
239
+
};
240
+
241
+
sd2_bus4: sd2-bus-width4-pins {
242
+
samsung,pins = "gpj0-3", "gpj0-4", "gpj0-5";
243
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
244
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
245
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV3>;
246
+
};
247
+
248
+
/* For Drive strength swapping */
249
+
sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
250
+
samsung,pins = "gpj0-0";
251
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
252
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
253
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
254
+
};
255
+
256
+
sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
257
+
samsung,pins = "gpj0-0";
258
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
259
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
260
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV3>;
261
+
};
262
+
263
+
sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
264
+
samsung,pins = "gpj0-0";
265
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
266
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
267
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
268
+
};
269
+
270
+
sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
271
+
samsung,pins = "gpj0-0";
272
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
273
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
274
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
275
+
};
276
+
};
277
+
278
+
&pinctrl_peric0 {
279
+
gpb1: gpb1-gpio-bank {
280
+
gpio-controller;
281
+
#gpio-cells = <2>;
282
+
283
+
interrupt-controller;
284
+
#interrupt-cells = <2>;
285
+
};
286
+
287
+
gpd0: gpd0-gpio-bank {
288
+
gpio-controller;
289
+
#gpio-cells = <2>;
290
+
291
+
interrupt-controller;
292
+
#interrupt-cells = <2>;
293
+
};
294
+
295
+
gpd1: gpd1-gpio-bank {
296
+
gpio-controller;
297
+
#gpio-cells = <2>;
298
+
299
+
interrupt-controller;
300
+
#interrupt-cells = <2>;
301
+
};
302
+
303
+
gpd2: gpd2-gpio-bank {
304
+
gpio-controller;
305
+
#gpio-cells = <2>;
306
+
307
+
interrupt-controller;
308
+
#interrupt-cells = <2>;
309
+
};
310
+
311
+
gpd3: gpd3-gpio-bank {
312
+
gpio-controller;
313
+
#gpio-cells = <2>;
314
+
315
+
interrupt-controller;
316
+
#interrupt-cells = <2>;
317
+
};
318
+
319
+
gpe7: gpe7-gpio-bank {
320
+
gpio-controller;
321
+
#gpio-cells = <2>;
322
+
323
+
interrupt-controller;
324
+
#interrupt-cells = <2>;
325
+
};
326
+
327
+
gpf1: gpf1-gpio-bank {
328
+
gpio-controller;
329
+
#gpio-cells = <2>;
330
+
331
+
interrupt-controller;
332
+
#interrupt-cells = <2>;
333
+
};
334
+
335
+
hsi2c5_bus: hsi2c5-bus-pins {
336
+
samsung,pins = "gpd1-1", "gpd1-0";
337
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
338
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
339
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
340
+
};
341
+
342
+
hsi2c6_bus: hsi2c6-bus-pins {
343
+
samsung,pins = "gpd1-3", "gpd1-2";
344
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
345
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
346
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
347
+
};
348
+
349
+
hsi2c7_bus: hsi2c7-bus-pins {
350
+
samsung,pins = "gpd1-5", "gpd1-4";
351
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
352
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
353
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
354
+
};
355
+
356
+
hsi2c8_bus: hsi2c8-bus-pins {
357
+
samsung,pins = "gpd1-7", "gpd1-6";
358
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
359
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
360
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
361
+
};
362
+
363
+
hsi2c9_bus: hsi2c9-bus-pins {
364
+
samsung,pins = "gpd2-1", "gpd2-0";
365
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
366
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
367
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
368
+
};
369
+
370
+
hsi2c10_bus: hsi2c10-bus-pins {
371
+
samsung,pins = "gpd2-3", "gpd2-2";
372
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
373
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
374
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
375
+
};
376
+
377
+
hsi2c11_bus: hsi2c11-bus-pins {
378
+
samsung,pins = "gpd3-1", "gpd3-0";
379
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
380
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
381
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
382
+
};
383
+
384
+
hsi2c12_bus: hsi2c12-bus-pins {
385
+
samsung,pins = "gpd3-3", "gpd3-2";
386
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
387
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
388
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
389
+
};
390
+
391
+
hs_i2c14_bus: hs-i2c14-bus-pins {
392
+
samsung,pins = "gpe6-3", "gpe6-2";
393
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
394
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
395
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
396
+
};
397
+
398
+
spi2_bus: spi2-bus-pins {
399
+
samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
400
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
401
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
402
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
403
+
};
404
+
405
+
spi2_cs: spi2-cs-pins {
406
+
samsung,pins = "gpd1-2";
407
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
408
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
409
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
410
+
};
411
+
412
+
spi3_bus: spi3-bus-pins {
413
+
samsung,pins = "gpd1-7", "gpd1-5", "gpd1-4";
414
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
415
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
416
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
417
+
};
418
+
419
+
spi3_cs: spi3-cs-pins {
420
+
samsung,pins = "gpd1-6";
421
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
422
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
423
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
424
+
};
425
+
426
+
spi4_bus: spi4-bus-pins {
427
+
samsung,pins = "gpd2-3", "gpd2-1", "gpd2-0";
428
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
429
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
430
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
431
+
};
432
+
433
+
spi4_cs: spi4-cs-pins {
434
+
samsung,pins = "gpd2-2";
435
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
436
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
437
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
438
+
};
439
+
440
+
spi5_bus: spi5-bus-pins {
441
+
samsung,pins = "gpd3-3", "gpd3-1", "gpd3-0";
442
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
443
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
444
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
445
+
};
446
+
447
+
spi5_cs: spi5-cs-pins {
448
+
samsung,pins = "gpd3-2";
449
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
450
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
451
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
452
+
};
453
+
454
+
uart0_bus: uart0-bus-pins {
455
+
samsung,pins = "gpd0-7", "gpd0-6";
456
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
457
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
458
+
};
459
+
460
+
uart2_bus: uart2-bus-pins {
461
+
samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
462
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
463
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
464
+
};
465
+
466
+
uart2_bus_dual: uart2-bus-dual-pins {
467
+
samsung,pins = "gpd1-1", "gpd1-0";
468
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
469
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
470
+
};
471
+
472
+
uart3_bus: uart3-bus-pins {
473
+
samsung,pins = "gpd1-7", "gpd1-6", "gpd1-5", "gpd1-4";
474
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
475
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
476
+
};
477
+
478
+
uart3_bus_dual: uart3-bus-dual-pins {
479
+
samsung,pins = "gpd1-5", "gpd1-4";
480
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
481
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
482
+
};
483
+
484
+
uart4_bus: uart4-bus-pins {
485
+
samsung,pins = "gpd2-3", "gpd2-2", "gpd2-1", "gpd2-0";
486
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
487
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
488
+
};
489
+
490
+
uart4_bus_dual: uart4-bus-dual-pins {
491
+
samsung,pins = "gpd2-1", "gpd2-0";
492
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
493
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
494
+
};
495
+
496
+
uart5_bus: uart5-bus-pins {
497
+
samsung,pins = "gpd3-3", "gpd3-2", "gpd3-1", "gpd3-0";
498
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
499
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
500
+
};
501
+
502
+
uart5_bus_dual: uart5-bus-dual-pins {
503
+
samsung,pins = "gpd3-1", "gpd3-0";
504
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
505
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
506
+
};
507
+
};
508
+
509
+
&pinctrl_peric1 {
510
+
gpb0: gpb0-gpio-bank {
511
+
gpio-controller;
512
+
#gpio-cells = <2>;
513
+
514
+
interrupt-controller;
515
+
#interrupt-cells = <2>;
516
+
};
517
+
518
+
gpc0: gpc0-gpio-bank {
519
+
gpio-controller;
520
+
#gpio-cells = <2>;
521
+
522
+
interrupt-controller;
523
+
#interrupt-cells = <2>;
524
+
};
525
+
526
+
gpc1: gpc1-gpio-bank {
527
+
gpio-controller;
528
+
#gpio-cells = <2>;
529
+
530
+
interrupt-controller;
531
+
#interrupt-cells = <2>;
532
+
};
533
+
534
+
gpc2: gpc2-gpio-bank {
535
+
gpio-controller;
536
+
#gpio-cells = <2>;
537
+
538
+
interrupt-controller;
539
+
#interrupt-cells = <2>;
540
+
};
541
+
542
+
gpc3: gpc3-gpio-bank {
543
+
gpio-controller;
544
+
#gpio-cells = <2>;
545
+
546
+
interrupt-controller;
547
+
#interrupt-cells = <2>;
548
+
};
549
+
550
+
gpe1: gpe1-gpio-bank {
551
+
gpio-controller;
552
+
#gpio-cells = <2>;
553
+
554
+
interrupt-controller;
555
+
#interrupt-cells = <2>;
556
+
};
557
+
558
+
gpe2: gpe2-gpio-bank {
559
+
gpio-controller;
560
+
#gpio-cells = <2>;
561
+
562
+
interrupt-controller;
563
+
#interrupt-cells = <2>;
564
+
};
565
+
566
+
gpe3: gpe3-gpio-bank {
567
+
gpio-controller;
568
+
#gpio-cells = <2>;
569
+
570
+
interrupt-controller;
571
+
#interrupt-cells = <2>;
572
+
};
573
+
574
+
gpe4: gpe4-gpio-bank {
575
+
gpio-controller;
576
+
#gpio-cells = <2>;
577
+
578
+
interrupt-controller;
579
+
#interrupt-cells = <2>;
580
+
};
581
+
582
+
gpe5: gpe5-gpio-bank {
583
+
gpio-controller;
584
+
#gpio-cells = <2>;
585
+
586
+
interrupt-controller;
587
+
#interrupt-cells = <2>;
588
+
};
589
+
590
+
gpe6: gpe6-gpio-bank {
591
+
gpio-controller;
592
+
#gpio-cells = <2>;
593
+
594
+
interrupt-controller;
595
+
#interrupt-cells = <2>;
596
+
};
597
+
598
+
gpf0: gpf0-gpio-bank {
599
+
gpio-controller;
600
+
#gpio-cells = <2>;
601
+
602
+
interrupt-controller;
603
+
#interrupt-cells = <2>;
604
+
};
605
+
606
+
gpg0: gpg0-gpio-bank {
607
+
gpio-controller;
608
+
#gpio-cells = <2>;
609
+
610
+
interrupt-controller;
611
+
#interrupt-cells = <2>;
612
+
};
613
+
614
+
gpk0: gpk0-gpio-bank {
615
+
gpio-controller;
616
+
#gpio-cells = <2>;
617
+
618
+
interrupt-controller;
619
+
#interrupt-cells = <2>;
620
+
};
621
+
622
+
hrm_irq: hrm-irq-pins {
623
+
samsung,pins = "gpe6-6";
624
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
625
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
626
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
627
+
};
628
+
629
+
hsi2c1_bus: hsi2c1-bus-pins {
630
+
samsung,pins = "gpc2-1", "gpc2-0";
631
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
632
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
633
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
634
+
};
635
+
636
+
hsi2c2_bus: hsi2c2-bus-pins {
637
+
samsung,pins = "gpc2-3", "gpc2-2";
638
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
639
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
640
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
641
+
};
642
+
643
+
hsi2c3_bus: hsi2c3-bus-pins {
644
+
samsung,pins = "gpc2-5", "gpc2-4";
645
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
646
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
647
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
648
+
};
649
+
650
+
hsi2c4_bus: hsi2c4-bus-pins {
651
+
samsung,pins = "gpc2-7", "gpc2-6";
652
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
653
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
654
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
655
+
};
656
+
657
+
hsi2c13_bus: hsi2c13-bus-pins {
658
+
samsung,pins = "gpe5-1", "gpe5-0";
659
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
660
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
661
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
662
+
};
663
+
664
+
hsi2c14_bus: hsi2c14-bus-pins {
665
+
samsung,pins = "gpe5-3", "gpe5-2";
666
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
667
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
668
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
669
+
};
670
+
671
+
hsi2c15_bus: hsi2c15-bus-pins {
672
+
samsung,pins = "gpe1-1", "gpe1-0";
673
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
674
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
675
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
676
+
};
677
+
678
+
hsi2c16_bus: hsi2c16-bus-pins {
679
+
samsung,pins = "gpe1-3", "gpe1-2";
680
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
681
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
682
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
683
+
};
684
+
685
+
hsi2c17_bus: hsi2c17-bus-pins {
686
+
samsung,pins = "gpe1-5", "gpe1-4";
687
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
688
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
689
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
690
+
};
691
+
692
+
hsi2c18_bus: hsi2c18-bus-pins {
693
+
samsung,pins = "gpe1-7", "gpe1-6";
694
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
695
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
696
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
697
+
};
698
+
699
+
hsi2c19_bus: hsi2c19-bus-pins {
700
+
samsung,pins = "gpe2-1", "gpe2-0";
701
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
702
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
703
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
704
+
};
705
+
706
+
hsi2c20_bus: hsi2c20-bus-pins {
707
+
samsung,pins = "gpe2-3", "gpe2-2";
708
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
709
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
710
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
711
+
};
712
+
713
+
hsi2c21_bus: hsi2c21-bus-pins {
714
+
samsung,pins = "gpe2-5", "gpe2-4";
715
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
716
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
717
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
718
+
};
719
+
720
+
hsi2c22_bus: hsi2c22-bus-pins {
721
+
samsung,pins = "gpe2-7", "gpe2-6";
722
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
723
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
724
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
725
+
};
726
+
727
+
hsi2c23_bus: hsi2c23-bus-pins {
728
+
samsung,pins = "gpe3-1", "gpe3-0";
729
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
730
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
731
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
732
+
};
733
+
734
+
hsi2c24_bus: hsi2c24-bus-pins {
735
+
samsung,pins = "gpe3-3", "gpe3-2";
736
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
737
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
738
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
739
+
};
740
+
741
+
hsi2c25_bus: hsi2c25-bus-pins {
742
+
samsung,pins = "gpe3-5", "gpe3-4";
743
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
744
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
745
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
746
+
};
747
+
748
+
hsi2c26_bus: hsi2c26-bus-pins {
749
+
samsung,pins = "gpe3-7", "gpe3-6";
750
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
751
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
752
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
753
+
};
754
+
755
+
hsi2c27_bus: hsi2c27-bus-pins {
756
+
samsung,pins = "gpe4-1", "gpe4-0";
757
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
758
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
759
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
760
+
};
761
+
762
+
hsi2c28_bus: hsi2c28-bus-pins {
763
+
samsung,pins = "gpe4-3", "gpe4-2";
764
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
765
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
766
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
767
+
};
768
+
769
+
hsi2c29_bus: hsi2c29-bus-pins {
770
+
samsung,pins = "gpe4-5", "gpe4-4";
771
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
772
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
773
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
774
+
};
775
+
776
+
hsi2c30_bus: hsi2c30-bus-pins {
777
+
samsung,pins = "gpe4-7", "gpe4-6";
778
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
779
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
780
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
781
+
};
782
+
783
+
hsi2c31_bus: hsi2c31-bus-pins {
784
+
samsung,pins = "gpe5-5", "gpe5-4";
785
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
786
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
787
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
788
+
};
789
+
790
+
hsi2c32_bus: hsi2c32-bus-pins {
791
+
samsung,pins = "gpe5-7", "gpe5-6";
792
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
793
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
794
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
795
+
};
796
+
797
+
spi0_bus: spi0-bus-pins {
798
+
samsung,pins = "gpc3-3", "gpc3-2", "gpc3-0";
799
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
800
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
801
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
802
+
};
803
+
804
+
spi0_cs: spi0-cs-pins {
805
+
samsung,pins = "gpc3-1";
806
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
807
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
808
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
809
+
};
810
+
811
+
spi1_bus: spi1-bus-pins {
812
+
samsung,pins = "gpc3-7", "gpc3-6", "gpc3-4";
813
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
814
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
815
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
816
+
};
817
+
818
+
spi1_cs: spi1-cs-pins {
819
+
samsung,pins = "gpc3-5";
820
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
821
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
822
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
823
+
};
824
+
825
+
spi6_bus: spi6-bus-pins {
826
+
samsung,pins = "gpe5-3", "gpe5-1", "gpe5-0";
827
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
828
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
829
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
830
+
};
831
+
832
+
spi6_cs: spi6-cs-pins {
833
+
samsung,pins = "gpe5-2";
834
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
835
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
836
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
837
+
};
838
+
839
+
spi7_bus: spi7-bus-pins {
840
+
samsung,pins = "gpe1-3", "gpe1-1", "gpe1-0";
841
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
842
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
843
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
844
+
};
845
+
846
+
spi7_cs: spi7-cs-pins {
847
+
samsung,pins = "gpe1-2";
848
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
849
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
850
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
851
+
};
852
+
853
+
spi8_bus: spi8-bus-pins {
854
+
samsung,pins = "gpe1-7", "gpe1-5", "gpe1-4";
855
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
856
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
857
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
858
+
};
859
+
860
+
spi8_cs: spi8-cs-pins {
861
+
samsung,pins = "gpe1-6";
862
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
863
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
864
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
865
+
};
866
+
867
+
spi9_bus: spi9-bus-pins {
868
+
samsung,pins = "gpe2-3", "gpe2-1", "gpe2-0";
869
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
870
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
871
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
872
+
};
873
+
874
+
spi9_cs: spi9-cs-pins {
875
+
samsung,pins = "gpe2-2";
876
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
877
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
878
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
879
+
};
880
+
881
+
spi10_bus: spi10-bus-pins {
882
+
samsung,pins = "gpe2-7", "gpe2-5", "gpe2-4";
883
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
884
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
885
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
886
+
};
887
+
888
+
spi10_cs: spi10-cs-pins {
889
+
samsung,pins = "gpe2-6";
890
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
891
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
892
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
893
+
};
894
+
895
+
spi11_bus: spi11-bus-pins {
896
+
samsung,pins = "gpe3-3", "gpe3-1", "gpe3-0";
897
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
898
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
899
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
900
+
};
901
+
902
+
spi11_cs: spi11-cs-pins {
903
+
samsung,pins = "gpe3-2";
904
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
905
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
906
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
907
+
};
908
+
909
+
spi12_bus: spi12-bus-pins {
910
+
samsung,pins = "gpe3-7", "gpe3-5", "gpe3-4";
911
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
912
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
913
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
914
+
};
915
+
916
+
spi12_cs: spi12-cs-pins {
917
+
samsung,pins = "gpe3-6";
918
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
919
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
920
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
921
+
};
922
+
923
+
spi13_bus: spi13-bus-pins {
924
+
samsung,pins = "gpe4-3", "gpe4-1", "gpe4-0";
925
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
926
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
927
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
928
+
};
929
+
930
+
spi13_cs: spi13-cs-pins {
931
+
samsung,pins = "gpe4-2";
932
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
933
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
934
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
935
+
};
936
+
937
+
spi14_bus: spi14-bus-pins {
938
+
samsung,pins = "gpe4-7", "gpe4-5", "gpe4-4";
939
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
940
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
941
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
942
+
};
943
+
944
+
spi14_cs: spi14-cs-pins {
945
+
samsung,pins = "gpe4-6";
946
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
947
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
948
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
949
+
};
950
+
951
+
spi15_bus: spi15-bus-pins {
952
+
samsung,pins = "gpe5-7", "gpe5-5", "gpe5-4";
953
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
954
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
955
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
956
+
};
957
+
958
+
spi15_cs: spi15-cs-pins {
959
+
samsung,pins = "gpe5-6";
960
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
961
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
962
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
963
+
};
964
+
965
+
uart6_bus: uart6-bus-pins {
966
+
samsung,pins = "gpe5-3", "gpe5-2", "gpe5-1", "gpe5-0";
967
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
968
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
969
+
};
970
+
971
+
uart6_bus_dual: uart6-bus-dual-pins {
972
+
samsung,pins = "gpe5-1", "gpe5-0";
973
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
974
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
975
+
};
976
+
977
+
uart7_bus: uart7-bus-pins {
978
+
samsung,pins = "gpe1-3", "gpe1-2", "gpe1-1", "gpe1-0";
979
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
980
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
981
+
};
982
+
983
+
uart7_bus_dual: uart7-bus-dual-pins {
984
+
samsung,pins = "gpe1-1", "gpe1-0";
985
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
986
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
987
+
};
988
+
989
+
uart8_bus: uart8-bus-pins {
990
+
samsung,pins = "gpe1-7", "gpe1-6", "gpe1-5", "gpe1-4";
991
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
992
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
993
+
};
994
+
995
+
uart8_bus_dual: uart8-bus-dual-pins {
996
+
samsung,pins = "gpe1-5", "gpe1-4";
997
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
998
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
999
+
};
1000
+
1001
+
uart9_bus: uart9-bus-pins {
1002
+
samsung,pins = "gpe2-3", "gpe2-2", "gpe2-1", "gpe2-0";
1003
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1004
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1005
+
};
1006
+
1007
+
uart9_bus_dual: uart9-bus-dual-pins {
1008
+
samsung,pins = "gpe2-1", "gpe2-0";
1009
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1010
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1011
+
};
1012
+
1013
+
uart10_bus: uart10-bus-pins {
1014
+
samsung,pins = "gpe2-7", "gpe2-6", "gpe2-5", "gpe2-4";
1015
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1016
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1017
+
};
1018
+
1019
+
uart10_bus_dual: uart10-bus-dual-pins {
1020
+
samsung,pins = "gpe2-5", "gpe2-4";
1021
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1022
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1023
+
};
1024
+
1025
+
uart11_bus: uart11-bus-pins {
1026
+
samsung,pins = "gpe3-3", "gpe3-2", "gpe3-1", "gpe3-0";
1027
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1028
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1029
+
};
1030
+
1031
+
uart11_bus_dual: uart11-bus-dual-pins {
1032
+
samsung,pins = "gpe3-1", "gpe3-0";
1033
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1034
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1035
+
};
1036
+
1037
+
uart12_bus: uart12-bus-pins {
1038
+
samsung,pins = "gpe3-7", "gpe3-6", "gpe3-5", "gpe3-4";
1039
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1040
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1041
+
};
1042
+
1043
+
uart12_bus_dual: uart12-bus-dual-pins {
1044
+
samsung,pins = "gpe3-5", "gpe3-4";
1045
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1046
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1047
+
};
1048
+
1049
+
uart13_bus: uart13-bus-pins {
1050
+
samsung,pins = "gpe4-3", "gpe4-2", "gpe4-1", "gpe4-0";
1051
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1052
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1053
+
};
1054
+
1055
+
uart13_bus_dual: uart13-bus-dual-pins {
1056
+
samsung,pins = "gpe4-1", "gpe4-0";
1057
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1058
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1059
+
};
1060
+
1061
+
uart14_bus: uart14-bus-pins {
1062
+
samsung,pins = "gpe4-7", "gpe4-6", "gpe4-5", "gpe4-4";
1063
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1064
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1065
+
};
1066
+
1067
+
uart14_bus_dual: uart14-bus-dual-pins {
1068
+
samsung,pins = "gpe4-5", "gpe4-4";
1069
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1070
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1071
+
};
1072
+
1073
+
uart15_bus: uart15-bus-pins {
1074
+
samsung,pins = "gpe5-7", "gpe5-6", "gpe5-5", "gpe5-4";
1075
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1076
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1077
+
};
1078
+
1079
+
uart15_bus_dual: uart15-bus-dual-pins {
1080
+
samsung,pins = "gpe5-5", "gpe5-4";
1081
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1082
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1083
+
};
1084
+
};
1085
+
1086
+
&pinctrl_vts {
1087
+
gph2: gph2-gpio-bank {
1088
+
gpio-controller;
1089
+
#gpio-cells = <2>;
1090
+
1091
+
interrupt-controller;
1092
+
#interrupt-cells = <2>;
1093
+
};
1094
+
};
+386
arch/arm64/boot/dts/exynos/exynos8895.dtsi
+386
arch/arm64/boot/dts/exynos/exynos8895.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung's Exynos 8895 SoC device tree source
4
+
*
5
+
* Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6
+
*/
7
+
8
+
#include <dt-bindings/clock/samsung,exynos8895.h>
9
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
+
11
+
/ {
12
+
compatible = "samsung,exynos8895";
13
+
#address-cells = <2>;
14
+
#size-cells = <1>;
15
+
16
+
interrupt-parent = <&gic>;
17
+
18
+
aliases {
19
+
pinctrl0 = &pinctrl_alive;
20
+
pinctrl1 = &pinctrl_abox;
21
+
pinctrl2 = &pinctrl_vts;
22
+
pinctrl3 = &pinctrl_fsys0;
23
+
pinctrl4 = &pinctrl_fsys1;
24
+
pinctrl5 = &pinctrl_busc;
25
+
pinctrl6 = &pinctrl_peric0;
26
+
pinctrl7 = &pinctrl_peric1;
27
+
};
28
+
29
+
arm-a53-pmu {
30
+
compatible = "arm,cortex-a53-pmu";
31
+
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
32
+
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
33
+
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
34
+
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
35
+
interrupt-affinity = <&cpu0>,
36
+
<&cpu1>,
37
+
<&cpu2>,
38
+
<&cpu3>;
39
+
};
40
+
41
+
/* There's no PMU model for the Mongoose cores */
42
+
43
+
cpus {
44
+
#address-cells = <1>;
45
+
#size-cells = <0>;
46
+
47
+
cpu-map {
48
+
cluster0 {
49
+
core0 {
50
+
cpu = <&cpu0>;
51
+
};
52
+
core1 {
53
+
cpu = <&cpu1>;
54
+
};
55
+
core2 {
56
+
cpu = <&cpu2>;
57
+
};
58
+
core3 {
59
+
cpu = <&cpu3>;
60
+
};
61
+
};
62
+
63
+
cluster1 {
64
+
core0 {
65
+
cpu = <&cpu4>;
66
+
};
67
+
core1 {
68
+
cpu = <&cpu5>;
69
+
};
70
+
core2 {
71
+
cpu = <&cpu6>;
72
+
};
73
+
core3 {
74
+
cpu = <&cpu7>;
75
+
};
76
+
};
77
+
};
78
+
79
+
cpu4: cpu@0 {
80
+
device_type = "cpu";
81
+
compatible = "samsung,mongoose-m2";
82
+
reg = <0x0>;
83
+
enable-method = "psci";
84
+
};
85
+
86
+
cpu5: cpu@1 {
87
+
device_type = "cpu";
88
+
compatible = "samsung,mongoose-m2";
89
+
reg = <0x1>;
90
+
enable-method = "psci";
91
+
};
92
+
93
+
cpu6: cpu@2 {
94
+
device_type = "cpu";
95
+
compatible = "samsung,mongoose-m2";
96
+
reg = <0x2>;
97
+
enable-method = "psci";
98
+
};
99
+
100
+
cpu7: cpu@3 {
101
+
device_type = "cpu";
102
+
compatible = "samsung,mongoose-m2";
103
+
reg = <0x3>;
104
+
enable-method = "psci";
105
+
};
106
+
107
+
cpu0: cpu@100 {
108
+
device_type = "cpu";
109
+
compatible = "arm,cortex-a53";
110
+
reg = <0x100>;
111
+
enable-method = "psci";
112
+
};
113
+
114
+
cpu1: cpu@101 {
115
+
device_type = "cpu";
116
+
compatible = "arm,cortex-a53";
117
+
reg = <0x101>;
118
+
enable-method = "psci";
119
+
};
120
+
121
+
cpu2: cpu@102 {
122
+
device_type = "cpu";
123
+
compatible = "arm,cortex-a53";
124
+
reg = <0x102>;
125
+
enable-method = "psci";
126
+
};
127
+
128
+
cpu3: cpu@103 {
129
+
device_type = "cpu";
130
+
compatible = "arm,cortex-a53";
131
+
reg = <0x103>;
132
+
enable-method = "psci";
133
+
};
134
+
};
135
+
136
+
oscclk: osc-clock {
137
+
compatible = "fixed-clock";
138
+
#clock-cells = <0>;
139
+
clock-output-names = "oscclk";
140
+
};
141
+
142
+
psci {
143
+
compatible = "arm,psci";
144
+
method = "smc";
145
+
cpu_off = <0x84000002>;
146
+
cpu_on = <0xc4000003>;
147
+
cpu_suspend = <0xc4000001>;
148
+
};
149
+
150
+
soc: soc@0 {
151
+
compatible = "simple-bus";
152
+
ranges = <0x0 0x0 0x0 0x20000000>;
153
+
154
+
#address-cells = <1>;
155
+
#size-cells = <1>;
156
+
157
+
chipid@10000000 {
158
+
compatible = "samsung,exynos8895-chipid",
159
+
"samsung,exynos850-chipid";
160
+
reg = <0x10000000 0x24>;
161
+
};
162
+
163
+
cmu_peris: clock-controller@10010000 {
164
+
compatible = "samsung,exynos8895-cmu-peris";
165
+
reg = <0x10010000 0x8000>;
166
+
#clock-cells = <1>;
167
+
clocks = <&oscclk>,
168
+
<&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
169
+
clock-names = "oscclk", "bus";
170
+
};
171
+
172
+
timer@10040000 {
173
+
compatible = "samsung,exynos8895-mct",
174
+
"samsung,exynos4210-mct";
175
+
reg = <0x10040000 0x800>;
176
+
clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
177
+
clock-names = "fin_pll", "mct";
178
+
interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
179
+
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
180
+
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
181
+
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
182
+
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
183
+
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
184
+
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
185
+
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
186
+
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
187
+
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
188
+
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
189
+
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
190
+
};
191
+
192
+
gic: interrupt-controller@10201000 {
193
+
compatible = "arm,gic-400";
194
+
reg = <0x10201000 0x1000>,
195
+
<0x10202000 0x1000>,
196
+
<0x10204000 0x2000>,
197
+
<0x10206000 0x2000>;
198
+
#interrupt-cells = <3>;
199
+
interrupt-controller;
200
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
201
+
IRQ_TYPE_LEVEL_HIGH)>;
202
+
#address-cells = <0>;
203
+
#size-cells = <1>;
204
+
};
205
+
206
+
cmu_peric0: clock-controller@10400000 {
207
+
compatible = "samsung,exynos8895-cmu-peric0";
208
+
reg = <0x10400000 0x8000>;
209
+
#clock-cells = <1>;
210
+
clocks = <&oscclk>,
211
+
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
212
+
<&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
213
+
<&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
214
+
<&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
215
+
<&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
216
+
<&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
217
+
clock-names = "oscclk", "bus", "uart", "usi0",
218
+
"usi1", "usi2", "usi3";
219
+
};
220
+
221
+
pinctrl_peric0: pinctrl@104d0000 {
222
+
compatible = "samsung,exynos8895-pinctrl";
223
+
reg = <0x104d0000 0x1000>;
224
+
interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
225
+
};
226
+
227
+
cmu_peric1: clock-controller@10800000 {
228
+
compatible = "samsung,exynos8895-cmu-peric1";
229
+
reg = <0x10800000 0x8000>;
230
+
#clock-cells = <1>;
231
+
clocks = <&oscclk>,
232
+
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
233
+
<&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
234
+
<&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
235
+
<&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>,
236
+
<&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>,
237
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI04>,
238
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI05>,
239
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI06>,
240
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI07>,
241
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI08>,
242
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI09>,
243
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI10>,
244
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI11>,
245
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI12>,
246
+
<&cmu_top CLK_DOUT_CMU_PERIC1_USI13>;
247
+
clock-names = "oscclk", "bus", "speedy", "cam0",
248
+
"cam1", "uart", "usi4", "usi5",
249
+
"usi6", "usi7", "usi8", "usi9",
250
+
"usi10", "usi11", "usi12", "usi13";
251
+
};
252
+
253
+
pinctrl_peric1: pinctrl@10980000 {
254
+
compatible = "samsung,exynos8895-pinctrl";
255
+
reg = <0x10980000 0x1000>;
256
+
interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
257
+
};
258
+
259
+
spi_0: spi@109d0000 {
260
+
compatible = "samsung,exynos8895-spi",
261
+
"samsung,exynos850-spi";
262
+
reg = <0x109d0000 0x100>;
263
+
#address-cells = <1>;
264
+
#size-cells = <0>;
265
+
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_PCLK>,
266
+
<&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK>;
267
+
clock-names = "spi", "spi_busclk0";
268
+
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
269
+
pinctrl-0 = <&spi0_bus>;
270
+
pinctrl-names = "default";
271
+
status = "disabled";
272
+
};
273
+
274
+
spi_1: spi@109e0000 {
275
+
compatible = "samsung,exynos8895-spi",
276
+
"samsung,exynos850-spi";
277
+
reg = <0x109e0000 0x100>;
278
+
#address-cells = <1>;
279
+
#size-cells = <0>;
280
+
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_PCLK>,
281
+
<&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK>;
282
+
clock-names = "spi", "spi_busclk0";
283
+
interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
284
+
pinctrl-0 = <&spi1_bus>;
285
+
pinctrl-names = "default";
286
+
status = "disabled";
287
+
};
288
+
289
+
cmu_fsys0: clock-controller@11000000 {
290
+
compatible = "samsung,exynos8895-cmu-fsys0";
291
+
reg = <0x11000000 0x8000>;
292
+
#clock-cells = <1>;
293
+
clocks = <&oscclk>,
294
+
<&cmu_top CLK_DOUT_CMU_FSYS0_BUS>,
295
+
<&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>,
296
+
<&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>,
297
+
<&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>,
298
+
<&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>;
299
+
clock-names = "oscclk", "bus", "dpgtc", "mmc",
300
+
"ufs", "usbdrd30";
301
+
};
302
+
303
+
pinctrl_fsys0: pinctrl@11050000 {
304
+
compatible = "samsung,exynos8895-pinctrl";
305
+
reg = <0x11050000 0x1000>;
306
+
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
307
+
};
308
+
309
+
cmu_fsys1: clock-controller@11400000 {
310
+
compatible = "samsung,exynos8895-cmu-fsys1";
311
+
reg = <0x11400000 0x8000>;
312
+
#clock-cells = <1>;
313
+
clocks = <&oscclk>,
314
+
<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
315
+
<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
316
+
<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
317
+
<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
318
+
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
319
+
};
320
+
321
+
pinctrl_fsys1: pinctrl@11430000 {
322
+
compatible = "samsung,exynos8895-pinctrl";
323
+
reg = <0x11430000 0x1000>;
324
+
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
325
+
};
326
+
327
+
pinctrl_abox: pinctrl@13e60000 {
328
+
compatible = "samsung,exynos8895-pinctrl";
329
+
reg = <0x13e60000 0x1000>;
330
+
};
331
+
332
+
pinctrl_vts: pinctrl@14080000 {
333
+
compatible = "samsung,exynos8895-pinctrl";
334
+
reg = <0x14080000 0x1000>;
335
+
};
336
+
337
+
pinctrl_busc: pinctrl@15a30000 {
338
+
compatible = "samsung,exynos8895-pinctrl";
339
+
reg = <0x15a30000 0x1000>;
340
+
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
341
+
};
342
+
343
+
cmu_top: clock-controller@15a80000 {
344
+
compatible = "samsung,exynos8895-cmu-top";
345
+
reg = <0x15a80000 0x8000>;
346
+
#clock-cells = <1>;
347
+
clocks = <&oscclk>;
348
+
clock-names = "oscclk";
349
+
};
350
+
351
+
pmu_system_controller: system-controller@16480000 {
352
+
compatible = "samsung,exynos8895-pmu",
353
+
"samsung,exynos7-pmu", "syscon";
354
+
reg = <0x16480000 0x10000>;
355
+
};
356
+
357
+
pinctrl_alive: pinctrl@164b0000 {
358
+
compatible = "samsung,exynos8895-pinctrl";
359
+
reg = <0x164b0000 0x1000>;
360
+
361
+
wakeup-interrupt-controller {
362
+
compatible = "samsung,exynos8895-wakeup-eint",
363
+
"samsung,exynos7-wakeup-eint";
364
+
interrupt-parent = <&gic>;
365
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
366
+
};
367
+
};
368
+
};
369
+
370
+
timer {
371
+
compatible = "arm,armv8-timer";
372
+
/* Hypervisor Virtual Timer interrupt is not wired to GIC */
373
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
374
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
375
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
376
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
377
+
/*
378
+
* Non-updatable, broken stock Samsung bootloader does not
379
+
* configure CNTFRQ_EL0
380
+
*/
381
+
clock-frequency = <26000000>;
382
+
};
383
+
};
384
+
385
+
#include "exynos8895-pinctrl.dtsi"
386
+
#include "arm/samsung/exynos-syscon-restart.dtsi"
+115
arch/arm64/boot/dts/exynos/exynos990-c1s.dts
+115
arch/arm64/boot/dts/exynos/exynos990-c1s.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung Galaxy Note20 5G (c1s/SM-N981B) device tree source
4
+
*
5
+
* Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
6
+
*/
7
+
8
+
/dts-v1/;
9
+
#include "exynos990.dtsi"
10
+
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/input/input.h>
12
+
#include <dt-bindings/interrupt-controller/irq.h>
13
+
14
+
/ {
15
+
model = "Samsung Galaxy Note20";
16
+
compatible = "samsung,c1s", "samsung,exynos990";
17
+
18
+
#address-cells = <2>;
19
+
#size-cells = <2>;
20
+
21
+
chosen {
22
+
#address-cells = <2>;
23
+
#size-cells = <2>;
24
+
ranges;
25
+
26
+
framebuffer0: framebuffer@f1000000 {
27
+
compatible = "simple-framebuffer";
28
+
reg = <0 0xf1000000 0 (1080 * 2400 * 4)>;
29
+
width = <1080>;
30
+
height = <2400>;
31
+
stride = <(1080 * 4)>;
32
+
format = "a8r8g8b8";
33
+
};
34
+
};
35
+
36
+
memory@80000000 {
37
+
device_type = "memory";
38
+
reg = <0x0 0x80000000 0x0 0x3ab00000>,
39
+
/* Memory hole */
40
+
<0x0 0xc1200000 0x0 0x1ee00000>,
41
+
/* Memory hole */
42
+
<0x0 0xe1900000 0x0 0x1e700000>,
43
+
/* Memory hole - last block */
44
+
<0x8 0x80000000 0x1 0x7ec00000>;
45
+
};
46
+
47
+
reserved-memory {
48
+
#address-cells = <2>;
49
+
#size-cells = <2>;
50
+
ranges;
51
+
52
+
cont_splash_mem: framebuffer@f1000000 {
53
+
reg = <0 0xf1000000 0 0x13c6800>;
54
+
no-map;
55
+
};
56
+
57
+
abox_reserved: audio@f7fb0000 {
58
+
reg = <0 0xf7fb0000 0 0x2a50000>;
59
+
no-map;
60
+
};
61
+
};
62
+
63
+
gpio-keys {
64
+
compatible = "gpio-keys";
65
+
66
+
pinctrl-0 = <&key_power &key_voldown &key_volup>;
67
+
pinctrl-names = "default";
68
+
69
+
power-key {
70
+
label = "Power";
71
+
linux,code = <KEY_POWER>;
72
+
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
73
+
wakeup-source;
74
+
};
75
+
76
+
voldown-key {
77
+
label = "Volume Down";
78
+
linux,code = <KEY_VOLUMEDOWN>;
79
+
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
80
+
};
81
+
82
+
volup-key {
83
+
label = "Volume Up";
84
+
linux,code = <KEY_VOLUMEUP>;
85
+
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
86
+
};
87
+
};
88
+
};
89
+
90
+
&oscclk {
91
+
clock-frequency = <26000000>;
92
+
};
93
+
94
+
&pinctrl_alive {
95
+
key_power: key-power-pins {
96
+
samsung,pins = "gpa2-4";
97
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
98
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
99
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
100
+
};
101
+
102
+
key_voldown: key-voldown-pins {
103
+
samsung,pins = "gpa0-4";
104
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
105
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
106
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
107
+
};
108
+
109
+
key_volup: key-volup-pins {
110
+
samsung,pins = "gpa0-3";
111
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
112
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
113
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
114
+
};
115
+
};
+2195
arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi
+2195
arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung Exynos 990 pin-mux and pin-config device tree source
4
+
*
5
+
* Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
#include "exynos-pinctrl.h"
10
+
11
+
&pinctrl_alive {
12
+
gpa0: gpa0-gpio-bank {
13
+
gpio-controller;
14
+
#gpio-cells = <2>;
15
+
16
+
interrupt-controller;
17
+
#interrupt-cells = <2>;
18
+
interrupt-parent = <&gic>;
19
+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
20
+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
21
+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
22
+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
23
+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
24
+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
25
+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
26
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
27
+
};
28
+
29
+
gpa1: gpa1-gpio-bank {
30
+
gpio-controller;
31
+
#gpio-cells = <2>;
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <2>;
35
+
interrupt-parent = <&gic>;
36
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
37
+
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
38
+
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
39
+
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
40
+
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
41
+
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
42
+
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
43
+
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
44
+
};
45
+
46
+
gpa2: gpa2-gpio-bank {
47
+
gpio-controller;
48
+
#gpio-cells = <2>;
49
+
50
+
interrupt-controller;
51
+
#interrupt-cells = <2>;
52
+
interrupt-parent = <&gic>;
53
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
54
+
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
55
+
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
56
+
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
57
+
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
58
+
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
59
+
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
60
+
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
61
+
};
62
+
63
+
gpa3: gpa3-gpio-bank {
64
+
gpio-controller;
65
+
#gpio-cells = <2>;
66
+
67
+
interrupt-controller;
68
+
#interrupt-cells = <2>;
69
+
interrupt-parent = <&gic>;
70
+
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
71
+
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
72
+
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
73
+
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
74
+
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
75
+
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
76
+
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
77
+
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
78
+
};
79
+
80
+
gpa4: gpa4-gpio-bank {
81
+
gpio-controller;
82
+
#gpio-cells = <2>;
83
+
84
+
interrupt-controller;
85
+
#interrupt-cells = <2>;
86
+
interrupt-parent = <&gic>;
87
+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
88
+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
89
+
};
90
+
91
+
gpq0: gpq0-gpio-bank {
92
+
gpio-controller;
93
+
#gpio-cells = <2>;
94
+
95
+
interrupt-controller;
96
+
#interrupt-cells = <2>;
97
+
};
98
+
99
+
speedy_bus: speedy-bus-pins {
100
+
samsung,pins = "gpq0-4";
101
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
102
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
103
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
104
+
};
105
+
106
+
speedy1_bus: speedy1-bus-pins {
107
+
samsung,pins = "gpq0-5";
108
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
109
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
110
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
111
+
};
112
+
113
+
/* UART1 is also referred to as UART_BT in downstream. */
114
+
uart1_bus_single: uart1-bus-pins {
115
+
samsung,pins = "gpq0-3", "gpq0-2", "gpq0-1", "gpq0-0";
116
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
117
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
118
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
119
+
};
120
+
121
+
uart1_rxd_pull: uart1-bus-rxd-pins {
122
+
samsung,pins = "gpq0-0";
123
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
124
+
};
125
+
126
+
uart1_bus_rts: uart1-bus-rts-pins {
127
+
samsung,pins = "gpq0-2";
128
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
129
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130
+
};
131
+
132
+
uart1_bus_tx_input: uart1-bus-tx-input-pins {
133
+
samsung,pins = "gpq0-1";
134
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
135
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
136
+
};
137
+
138
+
uart1_bus_tx_dat: uart1-bus-tx-dat-pins {
139
+
samsung,pins = "gpq0-1";
140
+
};
141
+
142
+
uart1_bus_tx_con: uart1-bus-tx-con-pins {
143
+
samsung,pins = "gpq0-1";
144
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
145
+
};
146
+
147
+
wlan_host_wake: wlan-host-wake-pins {
148
+
samsung,pins = "gpa0-7";
149
+
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
150
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
151
+
};
152
+
};
153
+
154
+
&pinctrl_cmgp {
155
+
gpm0: gpm0-gpio-bank {
156
+
gpio-controller;
157
+
#gpio-cells = <2>;
158
+
159
+
interrupt-controller;
160
+
#interrupt-cells = <2>;
161
+
};
162
+
163
+
gpm1: gpm1-gpio-bank {
164
+
gpio-controller;
165
+
#gpio-cells = <2>;
166
+
167
+
interrupt-controller;
168
+
#interrupt-cells = <2>;
169
+
};
170
+
171
+
gpm2: gpm2-gpio-bank {
172
+
gpio-controller;
173
+
#gpio-cells = <2>;
174
+
175
+
interrupt-controller;
176
+
#interrupt-cells = <2>;
177
+
};
178
+
179
+
gpm3: gpm3-gpio-bank {
180
+
gpio-controller;
181
+
#gpio-cells = <2>;
182
+
183
+
interrupt-controller;
184
+
#interrupt-cells = <2>;
185
+
};
186
+
187
+
gpm4: gpm4-gpio-bank {
188
+
gpio-controller;
189
+
#gpio-cells = <2>;
190
+
191
+
interrupt-controller;
192
+
#interrupt-cells = <2>;
193
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
194
+
};
195
+
196
+
gpm5: gpm5-gpio-bank {
197
+
gpio-controller;
198
+
#gpio-cells = <2>;
199
+
200
+
interrupt-controller;
201
+
#interrupt-cells = <2>;
202
+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
203
+
};
204
+
205
+
gpm6: gpm6-gpio-bank {
206
+
gpio-controller;
207
+
#gpio-cells = <2>;
208
+
209
+
interrupt-controller;
210
+
#interrupt-cells = <2>;
211
+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
212
+
};
213
+
214
+
gpm7: gpm7-gpio-bank {
215
+
gpio-controller;
216
+
#gpio-cells = <2>;
217
+
218
+
interrupt-controller;
219
+
#interrupt-cells = <2>;
220
+
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
221
+
};
222
+
223
+
gpm8: gpm8-gpio-bank {
224
+
gpio-controller;
225
+
#gpio-cells = <2>;
226
+
227
+
interrupt-controller;
228
+
#interrupt-cells = <2>;
229
+
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
230
+
};
231
+
232
+
gpm9: gpm9-gpio-bank {
233
+
gpio-controller;
234
+
#gpio-cells = <2>;
235
+
236
+
interrupt-controller;
237
+
#interrupt-cells = <2>;
238
+
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
239
+
};
240
+
241
+
gpm10: gpm10-gpio-bank {
242
+
gpio-controller;
243
+
#gpio-cells = <2>;
244
+
245
+
interrupt-controller;
246
+
#interrupt-cells = <2>;
247
+
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
248
+
};
249
+
250
+
gpm11: gpm11-gpio-bank {
251
+
gpio-controller;
252
+
#gpio-cells = <2>;
253
+
254
+
interrupt-controller;
255
+
#interrupt-cells = <2>;
256
+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
257
+
};
258
+
259
+
gpm12: gpm12-gpio-bank {
260
+
gpio-controller;
261
+
#gpio-cells = <2>;
262
+
263
+
interrupt-controller;
264
+
#interrupt-cells = <2>;
265
+
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
266
+
};
267
+
268
+
gpm13: gpm13-gpio-bank {
269
+
gpio-controller;
270
+
#gpio-cells = <2>;
271
+
272
+
interrupt-controller;
273
+
#interrupt-cells = <2>;
274
+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
275
+
};
276
+
277
+
gpm14: gpm14-gpio-bank {
278
+
gpio-controller;
279
+
#gpio-cells = <2>;
280
+
281
+
interrupt-controller;
282
+
#interrupt-cells = <2>;
283
+
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
284
+
};
285
+
286
+
gpm15: gpm15-gpio-bank {
287
+
gpio-controller;
288
+
#gpio-cells = <2>;
289
+
290
+
interrupt-controller;
291
+
#interrupt-cells = <2>;
292
+
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
293
+
};
294
+
295
+
gpm16: gpm16-gpio-bank {
296
+
gpio-controller;
297
+
#gpio-cells = <2>;
298
+
299
+
interrupt-controller;
300
+
#interrupt-cells = <2>;
301
+
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
302
+
};
303
+
304
+
gpm17: gpm17-gpio-bank {
305
+
gpio-controller;
306
+
#gpio-cells = <2>;
307
+
308
+
interrupt-controller;
309
+
#interrupt-cells = <2>;
310
+
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
311
+
};
312
+
313
+
gpm18: gpm18-gpio-bank {
314
+
gpio-controller;
315
+
#gpio-cells = <2>;
316
+
317
+
interrupt-controller;
318
+
#interrupt-cells = <2>;
319
+
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
320
+
};
321
+
322
+
gpm19: gpm19-gpio-bank {
323
+
gpio-controller;
324
+
#gpio-cells = <2>;
325
+
326
+
interrupt-controller;
327
+
#interrupt-cells = <2>;
328
+
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
329
+
};
330
+
331
+
gpm20: gpm20-gpio-bank {
332
+
gpio-controller;
333
+
#gpio-cells = <2>;
334
+
335
+
interrupt-controller;
336
+
#interrupt-cells = <2>;
337
+
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
338
+
};
339
+
340
+
gpm21: gpm21-gpio-bank {
341
+
gpio-controller;
342
+
#gpio-cells = <2>;
343
+
344
+
interrupt-controller;
345
+
#interrupt-cells = <2>;
346
+
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
347
+
};
348
+
349
+
gpm22: gpm22-gpio-bank {
350
+
gpio-controller;
351
+
#gpio-cells = <2>;
352
+
353
+
interrupt-controller;
354
+
#interrupt-cells = <2>;
355
+
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
356
+
};
357
+
358
+
gpm23: gpm23-gpio-bank {
359
+
gpio-controller;
360
+
#gpio-cells = <2>;
361
+
362
+
interrupt-controller;
363
+
#interrupt-cells = <2>;
364
+
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
365
+
};
366
+
367
+
gpm24: gpm24-gpio-bank {
368
+
gpio-controller;
369
+
#gpio-cells = <2>;
370
+
371
+
interrupt-controller;
372
+
#interrupt-cells = <2>;
373
+
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
374
+
};
375
+
376
+
gpm25: gpm25-gpio-bank {
377
+
gpio-controller;
378
+
#gpio-cells = <2>;
379
+
380
+
interrupt-controller;
381
+
#interrupt-cells = <2>;
382
+
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
383
+
};
384
+
385
+
gpm26: gpm26-gpio-bank {
386
+
gpio-controller;
387
+
#gpio-cells = <2>;
388
+
389
+
interrupt-controller;
390
+
#interrupt-cells = <2>;
391
+
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
392
+
};
393
+
394
+
gpm27: gpm27-gpio-bank {
395
+
gpio-controller;
396
+
#gpio-cells = <2>;
397
+
398
+
interrupt-controller;
399
+
#interrupt-cells = <2>;
400
+
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
401
+
};
402
+
403
+
gpm28: gpm28-gpio-bank {
404
+
gpio-controller;
405
+
#gpio-cells = <2>;
406
+
407
+
interrupt-controller;
408
+
#interrupt-cells = <2>;
409
+
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
410
+
};
411
+
412
+
gpm29: gpm29-gpio-bank {
413
+
gpio-controller;
414
+
#gpio-cells = <2>;
415
+
416
+
interrupt-controller;
417
+
#interrupt-cells = <2>;
418
+
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
419
+
};
420
+
421
+
gpm30: gpm30-gpio-bank {
422
+
gpio-controller;
423
+
#gpio-cells = <2>;
424
+
425
+
interrupt-controller;
426
+
#interrupt-cells = <2>;
427
+
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
428
+
};
429
+
430
+
gpm31: gpm31-gpio-bank {
431
+
gpio-controller;
432
+
#gpio-cells = <2>;
433
+
434
+
interrupt-controller;
435
+
#interrupt-cells = <2>;
436
+
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
437
+
};
438
+
439
+
gpm32: gpm32-gpio-bank {
440
+
gpio-controller;
441
+
#gpio-cells = <2>;
442
+
443
+
interrupt-controller;
444
+
#interrupt-cells = <2>;
445
+
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
446
+
};
447
+
448
+
gpm33: gpm33-gpio-bank {
449
+
gpio-controller;
450
+
#gpio-cells = <2>;
451
+
452
+
interrupt-controller;
453
+
#interrupt-cells = <2>;
454
+
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
455
+
};
456
+
457
+
hsi2c38_bus: hsi2c38-bus-pins {
458
+
samsung,pins = "gpm0-0", "gpm1-0";
459
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
460
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
461
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
462
+
};
463
+
464
+
hsi2c39_bus: hsi2c39-bus-pins {
465
+
samsung,pins = "gpm2-0", "gpm3-0";
466
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
467
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
468
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
469
+
};
470
+
471
+
hsi2c40_bus: hsi2c40-bus-pins {
472
+
samsung,pins = "gpm4-0", "gpm5-0";
473
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
474
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
475
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
476
+
};
477
+
478
+
hsi2c41_bus: hsi2c41-bus-pins {
479
+
samsung,pins = "gpm6-0", "gpm7-0";
480
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
481
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
482
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
483
+
};
484
+
485
+
hsi2c42_bus: hsi2c42-bus-pins {
486
+
samsung,pins = "gpm8-0", "gpm9-0";
487
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
488
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
489
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
490
+
};
491
+
492
+
hsi2c43_bus: hsi2c43-bus-pins {
493
+
samsung,pins = "gpm10-0", "gpm11-0";
494
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
495
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
496
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
497
+
};
498
+
499
+
hsi2c44_bus: hsi2c44-bus-pins {
500
+
samsung,pins = "gpm12-0", "gpm13-0";
501
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
502
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
503
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
504
+
};
505
+
506
+
hsi2c45_bus: hsi2c45-bus-pins {
507
+
samsung,pins = "gpm14-0", "gpm15-0";
508
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
509
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
510
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
511
+
};
512
+
513
+
spi19_bus: spi19-bus-pins {
514
+
samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0";
515
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
516
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
517
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
518
+
};
519
+
520
+
spi19_cs: spi19-cs-pins {
521
+
samsung,pins = "gpm3-0";
522
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
523
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
524
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
525
+
};
526
+
527
+
spi19_cs_func: spi19-cs-func-pins {
528
+
samsung,pins = "gpm3-0";
529
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
530
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
531
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
532
+
};
533
+
534
+
spi20_bus: spi20-bus-pins {
535
+
samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0";
536
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
537
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
538
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
539
+
};
540
+
541
+
spi20_cs: spi20-cs-pins {
542
+
samsung,pins = "gpm7-0";
543
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
544
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
545
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
546
+
};
547
+
548
+
spi20_cs_func: spi20-cs-func-pins {
549
+
samsung,pins = "gpm7-0";
550
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
551
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
552
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
553
+
};
554
+
555
+
spi21_bus: spi21-bus-pins {
556
+
samsung,pins = "gpm8-0", "gpm9-0", "gpm10-0";
557
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
558
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
559
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
560
+
};
561
+
562
+
spi21_cs: spi21-cs-pins {
563
+
samsung,pins = "gpm11-0";
564
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
565
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
566
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
567
+
};
568
+
569
+
spi21_cs_func: spi21-cs-func-pins {
570
+
samsung,pins = "gpm11-0";
571
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
572
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
573
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
574
+
};
575
+
576
+
spi22_bus: spi22-bus-pins {
577
+
samsung,pins = "gpm12-0", "gpm13-0", "gpm14-0";
578
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
579
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
580
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
581
+
};
582
+
583
+
spi22_cs: spi22-cs-pins {
584
+
samsung,pins = "gpm15-0";
585
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
586
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
587
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
588
+
};
589
+
590
+
spi22_cs_func: spi22-cs-func-pins {
591
+
samsung,pins = "gpm15-0";
592
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
593
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
594
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
595
+
};
596
+
597
+
uart21_bus_single: uart21-bus-pins {
598
+
samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
599
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
600
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
601
+
};
602
+
603
+
uart21_bus_dual: uart21-bus-dual-pins {
604
+
samsung,pins = "gpm0-0", "gpm1-0";
605
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
606
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
607
+
};
608
+
609
+
uart22_bus_single: uart22-bus-pins {
610
+
samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
611
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
612
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
613
+
};
614
+
615
+
uart22_bus_dual: uart22-bus-dual-pins {
616
+
samsung,pins = "gpm4-0", "gpm5-0";
617
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
618
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
619
+
};
620
+
621
+
uart23_bus_single: uart23-bus-pins {
622
+
samsung,pins = "gpm8-0", "gpm9-0", "gpm10-0", "gpm11-0";
623
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
624
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
625
+
};
626
+
627
+
uart23_bus_dual: uart23-bus-dual-pins {
628
+
samsung,pins = "gpm8-0", "gpm9-0";
629
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
630
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
631
+
};
632
+
633
+
uart24_bus_single: uart24-bus-pins {
634
+
samsung,pins = "gpm12-0", "gpm13-0", "gpm14-0", "gpm15-0";
635
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
636
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
637
+
};
638
+
639
+
uart24_bus_dual: uart24-bus-dual-pins {
640
+
samsung,pins = "gpm12-0", "gpm13-0";
641
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
642
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
643
+
};
644
+
};
645
+
646
+
&pinctrl_hsi1 {
647
+
gpf0: gpf0-gpio-bank {
648
+
gpio-controller;
649
+
#gpio-cells = <2>;
650
+
651
+
interrupt-controller;
652
+
#interrupt-cells = <2>;
653
+
};
654
+
655
+
gpf1: gpf1-gpio-bank {
656
+
gpio-controller;
657
+
#gpio-cells = <2>;
658
+
659
+
interrupt-controller;
660
+
#interrupt-cells = <2>;
661
+
};
662
+
663
+
gpf2: gpf2-gpio-bank {
664
+
gpio-controller;
665
+
#gpio-cells = <2>;
666
+
667
+
interrupt-controller;
668
+
#interrupt-cells = <2>;
669
+
};
670
+
671
+
pcie0_clkreq: pcie0-clkreq-pins {
672
+
samsung,pins = "gpf0-0";
673
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
674
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
675
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
676
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
677
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
678
+
};
679
+
680
+
pcie0_perst: pcie0-perst-pins {
681
+
samsung,pins = "gpf0-1";
682
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
683
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
684
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
685
+
};
686
+
687
+
pcie1_clkreq: pcie1-clkreq-pins {
688
+
samsung,pins = "gpf0-2";
689
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
690
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
691
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
692
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
693
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
694
+
};
695
+
696
+
pcie1_perst: pcie1-perst-pins {
697
+
samsung,pins = "gpf0-3";
698
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
699
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
700
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
701
+
};
702
+
703
+
ufs_rst_n: ufs-rst-n-pins {
704
+
samsung,pins = "gpf2-1";
705
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
706
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
707
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
708
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
709
+
};
710
+
711
+
ufs_refclk_out: ufs-refclk-out-pins {
712
+
samsung,pins = "gpf2-0";
713
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
714
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
715
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
716
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
717
+
};
718
+
719
+
sd2_clk: sd2-clk-pins {
720
+
samsung,pins = "gpf1-0";
721
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
722
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
723
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV3>;
724
+
};
725
+
726
+
sd2_cmd: sd2-cmd-pins {
727
+
samsung,pins = "gpf1-1";
728
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
729
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
730
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
731
+
};
732
+
733
+
sd2_bus1: sd2-bus-width1-pins {
734
+
samsung,pins = "gpf1-2";
735
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
736
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
737
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
738
+
};
739
+
740
+
sd2_bus4: sd2-bus-width4-pins {
741
+
samsung,pins = "gpf1-3", "gpf1-4", "gpf1-5";
742
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
743
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
744
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
745
+
};
746
+
747
+
sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
748
+
samsung,pins = "gpf1-0";
749
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
750
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
751
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV1>;
752
+
};
753
+
754
+
sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x-pins {
755
+
samsung,pins = "gpf1-0";
756
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
757
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
758
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV1_5>;
759
+
};
760
+
761
+
sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
762
+
samsung,pins = "gpf1-0";
763
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
764
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
765
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
766
+
};
767
+
768
+
sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x-pins {
769
+
samsung,pins = "gpf1-0";
770
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
771
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
772
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2_5>;
773
+
};
774
+
775
+
sd2_clk_fast_slew_rate_3x: sd2-clk-fas-slew-rate-3x-pins {
776
+
samsung,pins = "gpf1-0";
777
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
778
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
779
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV3>;
780
+
};
781
+
782
+
sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
783
+
samsung,pins = "gpf1-0";
784
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
785
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
786
+
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV4>;
787
+
};
788
+
789
+
sd2_pins_as_pdn: sd2-pins-as-pdn-pins {
790
+
samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5";
791
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
792
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
793
+
};
794
+
};
795
+
796
+
&pinctrl_hsi2 {
797
+
gpf3: gpf3-gpio-bank {
798
+
gpio-controller;
799
+
#gpio-cells = <2>;
800
+
801
+
interrupt-controller;
802
+
#interrupt-cells = <2>;
803
+
};
804
+
805
+
pcie2_clkreq: pcie2-clkreq-pins {
806
+
samsung,pins = "gpf3-0";
807
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
808
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
809
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
810
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
811
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
812
+
};
813
+
814
+
pcie2_perst: pcie2-perst-pins {
815
+
samsung,pins = "gpf3-1";
816
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
817
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
818
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
819
+
};
820
+
};
821
+
822
+
&pinctrl_peric0 {
823
+
gpg0: gpg0-gpio-bank {
824
+
gpio-controller;
825
+
#gpio-cells = <2>;
826
+
827
+
interrupt-controller;
828
+
#interrupt-cells = <2>;
829
+
};
830
+
831
+
gpp0: gpp0-gpio-bank {
832
+
gpio-controller;
833
+
#gpio-cells = <2>;
834
+
835
+
interrupt-controller;
836
+
#interrupt-cells = <2>;
837
+
};
838
+
839
+
gpp1: gpp1-gpio-bank {
840
+
gpio-controller;
841
+
#gpio-cells = <2>;
842
+
843
+
interrupt-controller;
844
+
#interrupt-cells = <2>;
845
+
};
846
+
847
+
gpp2: gpp2-gpio-bank {
848
+
gpio-controller;
849
+
#gpio-cells = <2>;
850
+
851
+
interrupt-controller;
852
+
#interrupt-cells = <2>;
853
+
};
854
+
855
+
gpp3: gpp3-gpio-bank {
856
+
gpio-controller;
857
+
#gpio-cells = <2>;
858
+
859
+
interrupt-controller;
860
+
#interrupt-cells = <2>;
861
+
};
862
+
863
+
gpp4: gpp4-gpio-bank {
864
+
gpio-controller;
865
+
#gpio-cells = <2>;
866
+
867
+
interrupt-controller;
868
+
#interrupt-cells = <2>;
869
+
};
870
+
871
+
hsi2c0_bus: hsi2c0-bus-pins {
872
+
samsung,pins = "gpp0-0", "gpp0-1";
873
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
874
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
875
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
876
+
};
877
+
878
+
hsi2c1_bus: hsi2c1-bus-pins {
879
+
samsung,pins = "gpp0-2", "gpp0-3";
880
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
881
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
882
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
883
+
};
884
+
885
+
hsi2c2_bus: hsi2c2-bus-pins {
886
+
samsung,pins = "gpp0-4", "gpp0-5";
887
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
888
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
889
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
890
+
};
891
+
892
+
hsi2c3_bus: hsi2c3-bus-pins {
893
+
samsung,pins = "gpp0-6", "gpp0-7";
894
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
895
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
896
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
897
+
};
898
+
899
+
hsi2c4_bus: hsi2c4-bus-pins {
900
+
samsung,pins = "gpp1-0", "gpp1-1";
901
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
902
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
903
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
904
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
905
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
906
+
};
907
+
908
+
hsi2c5_bus: hsi2c5-bus-pins {
909
+
samsung,pins = "gpp1-2", "gpp1-3";
910
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
911
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
912
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
913
+
};
914
+
915
+
hsi2c6_bus: hsi2c6-bus-pins {
916
+
samsung,pins = "gpp1-4", "gpp1-5";
917
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
918
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
919
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
920
+
};
921
+
922
+
hsi2c7_bus: hsi2c7-bus-pins {
923
+
samsung,pins = "gpp1-6", "gpp1-7";
924
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
925
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
926
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
927
+
};
928
+
929
+
hsi2c8_bus: hsi2c8-bus-pins {
930
+
samsung,pins = "gpp2-0", "gpp2-1";
931
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
932
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
933
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
934
+
};
935
+
936
+
hsi2c9_bus: hsi2c9-bus-pins {
937
+
samsung,pins = "gpp2-2", "gpp2-3";
938
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
939
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
940
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
941
+
};
942
+
943
+
hsi2c10_bus: hsi2c10-bus-pins {
944
+
samsung,pins = "gpp2-4", "gpp2-5";
945
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
946
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
947
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
948
+
};
949
+
950
+
hsi2c11_bus: hsi2c11-bus-pins {
951
+
samsung,pins = "gpp2-6", "gpp2-7";
952
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
953
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
954
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
955
+
};
956
+
957
+
hsi2c26_bus: hsi2c26-bus-pins {
958
+
samsung,pins = "gpp3-0", "gpp3-1";
959
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
960
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
961
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
962
+
};
963
+
964
+
hsi2c27_bus: hsi2c27-bus-pins {
965
+
samsung,pins = "gpp3-2", "gpp3-3";
966
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
967
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
968
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
969
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
970
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
971
+
};
972
+
973
+
hsi2c28_bus: hsi2c28-bus-pins {
974
+
samsung,pins = "gpp3-4", "gpp3-5";
975
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
976
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
977
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
978
+
};
979
+
980
+
hsi2c29_bus: hsi2c29-bus-pins {
981
+
samsung,pins = "gpp3-6", "gpp3-7";
982
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
983
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
984
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
985
+
};
986
+
987
+
hsi2c30_bus: hsi2c30-bus-pins {
988
+
samsung,pins = "gpp4-0", "gpp4-1";
989
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
990
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
991
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
992
+
};
993
+
994
+
hsi2c31_bus: hsi2c31-bus-pins {
995
+
samsung,pins = "gpp4-2", "gpp4-3";
996
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
997
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
998
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
999
+
};
1000
+
1001
+
spi0_bus: spi0-bus-pins {
1002
+
samsung,pins = "gpp0-2", "gpp0-1", "gpp0-0";
1003
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1004
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1005
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1006
+
};
1007
+
1008
+
spi0_cs: spi0-cs-pins {
1009
+
samsung,pins = "gpp0-3";
1010
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1011
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1012
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1013
+
};
1014
+
1015
+
spi0_cs_func: spi0-cs-func-pins {
1016
+
samsung,pins = "gpp0-3";
1017
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1018
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1019
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1020
+
};
1021
+
1022
+
spi1_bus: spi1-bus-pins {
1023
+
samsung,pins = "gpp0-6", "gpp0-5", "gpp0-4";
1024
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1025
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1026
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1027
+
};
1028
+
1029
+
spi1_cs: spi1-cs-pins {
1030
+
samsung,pins = "gpp0-7";
1031
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1032
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1033
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1034
+
};
1035
+
1036
+
spi1_cs_func: spi1-cs-func-pins {
1037
+
samsung,pins = "gpp0-7";
1038
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1039
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1040
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1041
+
};
1042
+
1043
+
spi2_bus: spi2-bus-pins {
1044
+
samsung,pins = "gpp1-2", "gpp1-1", "gpp1-0";
1045
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1046
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1047
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1048
+
};
1049
+
1050
+
spi2_cs: spi2-cs-pins {
1051
+
samsung,pins = "gpp1-3";
1052
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1053
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1054
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1055
+
};
1056
+
1057
+
spi2_cs_func: spi2-cs-func-pins {
1058
+
samsung,pins = "gpp1-3";
1059
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1060
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1061
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1062
+
};
1063
+
1064
+
spi3_bus: spi3-bus-pins {
1065
+
samsung,pins = "gpp1-6", "gpp1-5", "gpp1-4";
1066
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1067
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1068
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1069
+
};
1070
+
1071
+
spi3_cs: spi3-cs-pins {
1072
+
samsung,pins = "gpp1-7";
1073
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1074
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1075
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1076
+
};
1077
+
1078
+
spi3_cs_func: spi3-cs-func-pins {
1079
+
samsung,pins = "gpp1-7";
1080
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1081
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1082
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1083
+
};
1084
+
1085
+
spi4_bus: spi4-bus-pins {
1086
+
samsung,pins = "gpp2-2", "gpp2-1", "gpp2-0";
1087
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1088
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1089
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1090
+
};
1091
+
1092
+
spi4_cs: spi4-cs-pins {
1093
+
samsung,pins = "gpp2-3";
1094
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1095
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1096
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1097
+
};
1098
+
1099
+
spi4_cs_func: spi4-cs-func-pins {
1100
+
samsung,pins = "gpp2-3";
1101
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1102
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1103
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1104
+
};
1105
+
1106
+
spi4_fp_inactive: spi4-fp-inactive-pins {
1107
+
samsung,pins = "gpp2-3", "gpp2-2", "gpp2-1", "gpp2-0";
1108
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1109
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1110
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1111
+
};
1112
+
1113
+
spi4_fp_cs_func_high: spi4-fp-cs-func-high-pins {
1114
+
samsung,pins = "gpp2-3";
1115
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1116
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1117
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1118
+
};
1119
+
1120
+
spi5_bus: spi5-bus-pins {
1121
+
samsung,pins = "gpp2-6", "gpp2-5", "gpp2-4";
1122
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1123
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1124
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1125
+
};
1126
+
1127
+
spi5_cs: spi5-cs-pins {
1128
+
samsung,pins = "gpp2-7";
1129
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1130
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1131
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1132
+
};
1133
+
1134
+
spi5_cs_func: spi5-cs-func-pins {
1135
+
samsung,pins = "gpp2-7";
1136
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1137
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1138
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1139
+
};
1140
+
1141
+
spi13_bus: spi13-bus-pins {
1142
+
samsung,pins = "gpp3-2", "gpp3-1", "gpp3-0";
1143
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1144
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1145
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1146
+
};
1147
+
1148
+
spi13_cs: spi13-cs-pins {
1149
+
samsung,pins = "gpp3-3";
1150
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1151
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1152
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1153
+
};
1154
+
1155
+
spi13_cs_func: spi13-cs-func-pins {
1156
+
samsung,pins = "gpp3-3";
1157
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1158
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1159
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1160
+
};
1161
+
1162
+
spi14_bus: spi14-bus-pins {
1163
+
samsung,pins = "gpp3-6", "gpp3-5", "gpp3-4";
1164
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1165
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1166
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1167
+
};
1168
+
1169
+
spi14_cs: spi14-cs-pins {
1170
+
samsung,pins = "gpp3-7";
1171
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1172
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1173
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1174
+
};
1175
+
1176
+
spi14_cs_func: spi14-cs-func-pins {
1177
+
samsung,pins = "gpp3-7";
1178
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1179
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1180
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1181
+
};
1182
+
1183
+
spi15_bus: spi15-bus-pins {
1184
+
samsung,pins = "gpp4-2", "gpp4-1", "gpp4-0";
1185
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1186
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1187
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1188
+
};
1189
+
1190
+
spi15_cs: spi15-cs-pins {
1191
+
samsung,pins = "gpp4-3";
1192
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1193
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1194
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1195
+
};
1196
+
1197
+
spi15_cs_func: spi15-cs-func-pins {
1198
+
samsung,pins = "gpp4-3";
1199
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1200
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1201
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1202
+
};
1203
+
1204
+
uart0_bus: uart0-bus-pins {
1205
+
samsung,pins = "gpp4-6", "gpp4-7";
1206
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1207
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1208
+
};
1209
+
1210
+
uart2_bus_single: uart2-bus-pins {
1211
+
samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";
1212
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1213
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1214
+
};
1215
+
1216
+
uart2_bus_dual: uart2-bus-dual-pins {
1217
+
samsung,pins = "gpp0-0", "gpp0-1";
1218
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1219
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1220
+
};
1221
+
1222
+
uart3_bus_single: uart3-bus-pins {
1223
+
samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7";
1224
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1225
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1226
+
};
1227
+
1228
+
uart3_bus_dual: uart3-bus-dual-pins {
1229
+
samsung,pins = "gpp0-4", "gpp0-5";
1230
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1231
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1232
+
};
1233
+
1234
+
uart4_bus_single: uart4-bus-pins {
1235
+
samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";
1236
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1237
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1238
+
};
1239
+
1240
+
uart4_bus_dual: uart4-bus-dual-pins {
1241
+
samsung,pins = "gpp1-0", "gpp1-1";
1242
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1243
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1244
+
};
1245
+
1246
+
uart5_bus_single: uart5-bus-pins {
1247
+
samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7";
1248
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1249
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1250
+
};
1251
+
1252
+
uart5_bus_dual: uart5-bus-dual-pins {
1253
+
samsung,pins = "gpp1-4", "gpp1-5";
1254
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1255
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1256
+
};
1257
+
1258
+
uart6_bus_single: uart6-bus-pins {
1259
+
samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
1260
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1261
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1262
+
};
1263
+
1264
+
uart6_bus_dual: uart6-bus-dual-pins {
1265
+
samsung,pins = "gpp2-0", "gpp2-1";
1266
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1267
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1268
+
};
1269
+
1270
+
uart7_bus_single: uart7-bus-pins {
1271
+
samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7";
1272
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1273
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1274
+
};
1275
+
1276
+
uart7_bus_dual: uart7-bus-dual-pins {
1277
+
samsung,pins = "gpp2-4", "gpp2-5";
1278
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1279
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1280
+
};
1281
+
1282
+
uart15_bus_single: uart15-bus-pins {
1283
+
samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3";
1284
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1285
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1286
+
};
1287
+
1288
+
uart15_bus_dual: uart15-bus-dual-pins {
1289
+
samsung,pins = "gpp3-0", "gpp3-1";
1290
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1291
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1292
+
};
1293
+
1294
+
uart16_bus_single: uart16-bus-pins {
1295
+
samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6", "gpp3-7";
1296
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1297
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1298
+
};
1299
+
1300
+
uart16_bus_dual: uart16-bus-dual-pins {
1301
+
samsung,pins = "gpp3-4", "gpp3-5";
1302
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1303
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1304
+
};
1305
+
1306
+
uart17_bus_single: uart17-bus-pins {
1307
+
samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3";
1308
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1309
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1310
+
};
1311
+
1312
+
uart17_bus_dual: uart17-bus-dual-pins {
1313
+
samsung,pins = "gpp4-0", "gpp4-1";
1314
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1315
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1316
+
};
1317
+
};
1318
+
1319
+
&pinctrl_peric1 {
1320
+
gpb0: gpb0-gpio-bank {
1321
+
gpio-controller;
1322
+
#gpio-cells = <2>;
1323
+
1324
+
interrupt-controller;
1325
+
#interrupt-cells = <2>;
1326
+
};
1327
+
1328
+
gpb1: gpb1-gpio-bank {
1329
+
gpio-controller;
1330
+
#gpio-cells = <2>;
1331
+
1332
+
interrupt-controller;
1333
+
#interrupt-cells = <2>;
1334
+
};
1335
+
1336
+
gpb2: gpb2-gpio-bank {
1337
+
gpio-controller;
1338
+
#gpio-cells = <2>;
1339
+
1340
+
interrupt-controller;
1341
+
#interrupt-cells = <2>;
1342
+
};
1343
+
1344
+
gpc0: gpc0-gpio-bank {
1345
+
gpio-controller;
1346
+
#gpio-cells = <2>;
1347
+
1348
+
interrupt-controller;
1349
+
#interrupt-cells = <2>;
1350
+
};
1351
+
1352
+
gpg1: gpg1-gpio-bank {
1353
+
gpio-controller;
1354
+
#gpio-cells = <2>;
1355
+
1356
+
interrupt-controller;
1357
+
#interrupt-cells = <2>;
1358
+
};
1359
+
1360
+
gpp5: gpp5-gpio-bank {
1361
+
gpio-controller;
1362
+
#gpio-cells = <2>;
1363
+
1364
+
interrupt-controller;
1365
+
#interrupt-cells = <2>;
1366
+
};
1367
+
1368
+
gpp6: gpp6-gpio-bank {
1369
+
gpio-controller;
1370
+
#gpio-cells = <2>;
1371
+
1372
+
interrupt-controller;
1373
+
#interrupt-cells = <2>;
1374
+
};
1375
+
1376
+
gpp7: gpp7-gpio-bank {
1377
+
gpio-controller;
1378
+
#gpio-cells = <2>;
1379
+
1380
+
interrupt-controller;
1381
+
#interrupt-cells = <2>;
1382
+
};
1383
+
1384
+
gpp8: gpp8-gpio-bank {
1385
+
gpio-controller;
1386
+
#gpio-cells = <2>;
1387
+
1388
+
interrupt-controller;
1389
+
#interrupt-cells = <2>;
1390
+
};
1391
+
1392
+
gpp9: gpp9-gpio-bank {
1393
+
gpio-controller;
1394
+
#gpio-cells = <2>;
1395
+
1396
+
interrupt-controller;
1397
+
#interrupt-cells = <2>;
1398
+
};
1399
+
1400
+
aud_i2s0_bus: aud-i2s0-bus-pins {
1401
+
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";
1402
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1403
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1404
+
};
1405
+
1406
+
aud_i2s0_idle: aud-i2s0-idle-pins {
1407
+
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";
1408
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1409
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1410
+
};
1411
+
1412
+
aud_i2s1_bus: aud-i2s1-bus-pins {
1413
+
samsung,pins = "gpb0-4", "gpb0-5", "gpb0-6", "gpb0-7";
1414
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1415
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1416
+
};
1417
+
1418
+
aud_i2s1_idle: aud-i2s1-idle-pins {
1419
+
samsung,pins = "gpb0-4", "gpb0-5", "gpb0-6", "gpb0-7";
1420
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1421
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1422
+
};
1423
+
1424
+
aud_i2s2_bus: aud-i2s2-bus-pins {
1425
+
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
1426
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1427
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1428
+
};
1429
+
1430
+
aud_i2s2_idle: aud-i2s2-idle-pins {
1431
+
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
1432
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1433
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1434
+
};
1435
+
1436
+
aud_i2s3_bus: aud-i2s3-bus-pins {
1437
+
samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";
1438
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1439
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1440
+
};
1441
+
1442
+
aud_i2s3_idle: aud-i2s3-idle-pins {
1443
+
samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";
1444
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1445
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1446
+
};
1447
+
1448
+
aud_i2s4_bus: aud-i2s4-bus-pins {
1449
+
samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
1450
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1451
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1452
+
};
1453
+
1454
+
aud_i2s4_pci: aud-i2s4-pci-pins {
1455
+
samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
1456
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1457
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1458
+
};
1459
+
1460
+
aud_i2s4_idle: aud-i2s4-idle-pins {
1461
+
samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
1462
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1463
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1464
+
};
1465
+
1466
+
aud_i2s5_bus: aud-i2s5-bus-pins {
1467
+
samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";
1468
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1469
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1470
+
};
1471
+
1472
+
aud_i2s5_idle: aud-i2s5-idle-pins {
1473
+
samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";
1474
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1475
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1476
+
};
1477
+
1478
+
aud_dsd_bus: aud-dsd-bus-pins {
1479
+
samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6";
1480
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1481
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1482
+
};
1483
+
1484
+
aud_dsd_idle: aud-dsd-idle-pins {
1485
+
samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6";
1486
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1487
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1488
+
};
1489
+
1490
+
cfg_wlanen: cfg-wlanen-pins {
1491
+
samsung,pins = "gpb0-4";
1492
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1493
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1494
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
1495
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1496
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1497
+
};
1498
+
1499
+
cnss_wlan_en_active: cnss-wlan-en-active-pins {
1500
+
samsung,pins = "gpb0-4";
1501
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1502
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1503
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
1504
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1505
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1506
+
};
1507
+
1508
+
cnss_wlan_en_sleep: cnss-wlan-en-sleep-pins {
1509
+
samsung,pins = "gpb0-4";
1510
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1511
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1512
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV2>;
1513
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1514
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1515
+
};
1516
+
1517
+
decon_f_te_on: decon-f-te-on-pins {
1518
+
samsung,pins = "gpc0-4";
1519
+
samsung,pin-function = <0xf>;
1520
+
};
1521
+
1522
+
decon_f_te_off: decon-f-te-off-pins {
1523
+
samsung,pins = "gpc0-4";
1524
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1525
+
};
1526
+
1527
+
decon_s_te_on: decon-s-te-on-pins {
1528
+
samsung,pins = "gpc0-5";
1529
+
samsung,pin-function = <0xf>;
1530
+
};
1531
+
1532
+
decon_s_te_off: decon-s-te-off-pins {
1533
+
samsung,pins = "gpc0-5";
1534
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1535
+
};
1536
+
1537
+
hsi2c12_bus: hsi2c12-bus-pins {
1538
+
samsung,pins = "gpp5-0", "gpp5-1";
1539
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1540
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1541
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1542
+
};
1543
+
1544
+
hsi2c13_bus: hsi2c13-bus-pins {
1545
+
samsung,pins = "gpp5-2", "gpp5-3";
1546
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1547
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1548
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1549
+
};
1550
+
1551
+
hsi2c14_bus: hsi2c14-bus-pins {
1552
+
samsung,pins = "gpp5-4", "gpp5-5";
1553
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1554
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1555
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1556
+
};
1557
+
1558
+
hsi2c15_bus: hsi2c15-bus-pins {
1559
+
samsung,pins = "gpp5-6", "gpp5-7";
1560
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1561
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1562
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1563
+
};
1564
+
1565
+
hsi2c16_bus: hsi2c16-bus-pins {
1566
+
samsung,pins = "gpp6-0", "gpp6-1";
1567
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1568
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1569
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1570
+
};
1571
+
1572
+
hsi2c17_bus: hsi2c17-bus-pins {
1573
+
samsung,pins = "gpp6-2", "gpp6-3";
1574
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1575
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1576
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1577
+
};
1578
+
1579
+
hsi2c18_bus: hsi2c18-bus-pins {
1580
+
samsung,pins = "gpp6-4", "gpp6-5";
1581
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1582
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1583
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1584
+
};
1585
+
1586
+
hsi2c19_bus: hsi2c19-bus-pins {
1587
+
samsung,pins = "gpp6-6", "gpp6-7";
1588
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1589
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1590
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1591
+
};
1592
+
1593
+
hsi2c20_bus: hsi2c20-bus-pins {
1594
+
samsung,pins = "gpp7-0", "gpp7-1";
1595
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1596
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1597
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1598
+
};
1599
+
1600
+
hsi2c21_bus: hsi2c21-bus-pins {
1601
+
samsung,pins = "gpp7-2", "gpp7-3";
1602
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1603
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1604
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1605
+
};
1606
+
1607
+
hsi2c22_bus: hsi2c22-bus-pins {
1608
+
samsung,pins = "gpp7-4", "gpp7-5";
1609
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1610
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1611
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1612
+
};
1613
+
1614
+
hsi2c23_bus: hsi2c23-bus-pins {
1615
+
samsung,pins = "gpp7-6", "gpp7-7";
1616
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1617
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1618
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1619
+
};
1620
+
1621
+
hsi2c24_bus: hsi2c24-bus-pins {
1622
+
samsung,pins = "gpp8-0", "gpp8-1";
1623
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1624
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1625
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1626
+
};
1627
+
1628
+
hsi2c25_bus: hsi2c25-bus-pins {
1629
+
samsung,pins = "gpp8-2", "gpp8-3";
1630
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1631
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1632
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1633
+
};
1634
+
1635
+
hsi2c32_bus: hsi2c32-bus-pins {
1636
+
samsung,pins = "gpp8-4", "gpp8-5";
1637
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1638
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1639
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1640
+
};
1641
+
1642
+
hsi2c33_bus: hsi2c33-bus-pins {
1643
+
samsung,pins = "gpp8-6", "gpp8-7";
1644
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1645
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1646
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1647
+
};
1648
+
1649
+
hsi2c34_bus: hsi2c34-bus-pins {
1650
+
samsung,pins = "gpp9-0", "gpp9-1";
1651
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1652
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1653
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1654
+
};
1655
+
1656
+
hsi2c35_bus: hsi2c35-bus-pins {
1657
+
samsung,pins = "gpp9-2", "gpp9-3";
1658
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1659
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1660
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1661
+
};
1662
+
1663
+
hsi2c36_bus: hsi2c36-bus-pins {
1664
+
samsung,pins = "gpp9-4", "gpp9-5";
1665
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1666
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1667
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1668
+
};
1669
+
1670
+
hsi2c37_bus: hsi2c37-bus-pins {
1671
+
samsung,pins = "gpp9-6", "gpp9-7";
1672
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1673
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1674
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1675
+
};
1676
+
1677
+
sensor_mclk0_out: sensor-mclk0-out-pins {
1678
+
samsung,pins = "gpc0-0";
1679
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1680
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1681
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1682
+
};
1683
+
1684
+
sensor_mclk1_out: sensor-mclk1-out-pins {
1685
+
samsung,pins = "gpg1-1";
1686
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1687
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1688
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1689
+
};
1690
+
1691
+
sensor_mclk2_out: sensor-mclk2-out-pins {
1692
+
samsung,pins = "gpc0-1";
1693
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1694
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1695
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1696
+
};
1697
+
1698
+
sensor_mclk3_out: sensor-mclk3-out-pins {
1699
+
samsung,pins = "gpc0-2";
1700
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1701
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1702
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1703
+
};
1704
+
1705
+
sensor_mclk4_out: sensor-mclk4-out-pins {
1706
+
samsung,pins = "gpc0-3";
1707
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1708
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1709
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1710
+
};
1711
+
1712
+
sensor_mclk5_out: sensor-mclk5-out-pins {
1713
+
samsung,pins = "gpg1-2";
1714
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1715
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1716
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1717
+
};
1718
+
1719
+
sensor_mclk0_fn: sensor-mclk0-fn-pins {
1720
+
samsung,pins = "gpc0-0";
1721
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1722
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1723
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1724
+
};
1725
+
1726
+
sensor_mclk1_fn: sensor-mclk1-fn-pins {
1727
+
samsung,pins = "gpg1-1";
1728
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1729
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1730
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1731
+
};
1732
+
1733
+
sensor_mclk2_fn: sensor-mclk2-fn-pins {
1734
+
samsung,pins = "gpc0-1";
1735
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1736
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1737
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1738
+
};
1739
+
1740
+
sensor_mclk3_fn: sensor-mclk3-fn-pins {
1741
+
samsung,pins = "gpc0-2";
1742
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1743
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1744
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1745
+
};
1746
+
1747
+
sensor_mclk4_fn: sensor-mclk4-fn-pins {
1748
+
samsung,pins = "gpc0-3";
1749
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1750
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1751
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1752
+
};
1753
+
1754
+
sensor_mclk5_fn: sensor-mclk5-fn-pins {
1755
+
samsung,pins = "gpg1-2";
1756
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1757
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1758
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1759
+
};
1760
+
1761
+
spi6_bus: spi6-bus-pins {
1762
+
samsung,pins = "gpp5-2", "gpp5-1", "gpp5-0";
1763
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1764
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1765
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1766
+
};
1767
+
1768
+
spi6_cs: spi6-cs-pins {
1769
+
samsung,pins = "gpp5-3";
1770
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1771
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1772
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1773
+
};
1774
+
1775
+
spi6_cs_func: spi6-cs-func-pins {
1776
+
samsung,pins = "gpp5-3";
1777
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1778
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1779
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1780
+
};
1781
+
1782
+
spi7_bus: spi7-bus-pins {
1783
+
samsung,pins = "gpp5-6", "gpp5-5", "gpp5-4";
1784
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1785
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1786
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1787
+
};
1788
+
1789
+
spi7_cs: spi7-cs-pins {
1790
+
samsung,pins = "gpp5-7";
1791
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1792
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1793
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1794
+
};
1795
+
1796
+
spi7_cs_func: spi7-cs-func-pins {
1797
+
samsung,pins = "gpp5-7";
1798
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1799
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1800
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1801
+
};
1802
+
1803
+
spi8_bus: spi8-bus-pins {
1804
+
samsung,pins = "gpp6-2", "gpp6-1", "gpp6-0";
1805
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1806
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1807
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1808
+
};
1809
+
1810
+
spi8_cs: spi8-cs-pins {
1811
+
samsung,pins = "gpp6-3";
1812
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1813
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1814
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1815
+
};
1816
+
1817
+
spi8_cs_func: spi8-cs-func-pins {
1818
+
samsung,pins = "gpp6-3";
1819
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1820
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1821
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1822
+
};
1823
+
1824
+
spi9_bus: spi9-bus-pins {
1825
+
samsung,pins = "gpp6-6", "gpp6-5", "gpp6-4";
1826
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1827
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1828
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1829
+
};
1830
+
1831
+
spi9_cs: spi9-cs-pins {
1832
+
samsung,pins = "gpp6-7";
1833
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1834
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1835
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1836
+
};
1837
+
1838
+
spi9_cs_func: spi9-cs-func-pins {
1839
+
samsung,pins = "gpp6-7";
1840
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1841
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1842
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1843
+
};
1844
+
1845
+
spi10_bus: spi10-bus-pins {
1846
+
samsung,pins = "gpp7-2", "gpp7-1", "gpp7-0";
1847
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1848
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1849
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1850
+
};
1851
+
1852
+
spi10_cs: spi10-cs-pins {
1853
+
samsung,pins = "gpp7-3";
1854
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1855
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1856
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1857
+
};
1858
+
1859
+
spi10_cs_func: spi10-cs-func-pins {
1860
+
samsung,pins = "gpp7-3";
1861
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1862
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1863
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1864
+
};
1865
+
1866
+
spi11_bus: spi11-bus-pins {
1867
+
samsung,pins = "gpp7-6", "gpp7-5", "gpp7-4";
1868
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1869
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1870
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1871
+
};
1872
+
1873
+
spi11_cs: spi11-cs-pins {
1874
+
samsung,pins = "gpp7-7";
1875
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1876
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1877
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1878
+
};
1879
+
1880
+
spi11_cs_func: spi11-cs-func-pins {
1881
+
samsung,pins = "gpp7-7";
1882
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1883
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1884
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1885
+
};
1886
+
1887
+
spi12_bus: spi12-bus-pins {
1888
+
samsung,pins = "gpp8-2", "gpp8-1", "gpp8-0";
1889
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1890
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1891
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1892
+
};
1893
+
1894
+
spi12_cs: spi12-cs-pins {
1895
+
samsung,pins = "gpp8-3";
1896
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1897
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1898
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1899
+
};
1900
+
1901
+
spi12_cs_func: spi12-cs-func-pins {
1902
+
samsung,pins = "gpp8-3";
1903
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1904
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1905
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1906
+
};
1907
+
1908
+
spi16_bus: spi16-bus-pins {
1909
+
samsung,pins = "gpp8-6", "gpp8-5", "gpp8-4";
1910
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1911
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1912
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1913
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1914
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1915
+
};
1916
+
1917
+
spi16_cs: spi16-cs-pins {
1918
+
samsung,pins = "gpp8-7";
1919
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1920
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1921
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1922
+
};
1923
+
1924
+
spi16_cs_func: spi16-cs-func-pins {
1925
+
samsung,pins = "gpp8-7";
1926
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1927
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1928
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1929
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1930
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1931
+
};
1932
+
1933
+
spi17_bus: spi17-bus-pins {
1934
+
samsung,pins = "gpp9-2", "gpp9-1", "gpp9-0";
1935
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1936
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1937
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1938
+
};
1939
+
1940
+
spi17_cs: spi17-cs-pins {
1941
+
samsung,pins = "gpp9-3";
1942
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1943
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1944
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1945
+
};
1946
+
1947
+
spi17_cs_func: spi17-cs-func-pins {
1948
+
samsung,pins = "gpp9-3";
1949
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1950
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1951
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1952
+
};
1953
+
1954
+
spi18_bus: spi18-bus-pins {
1955
+
samsung,pins = "gpp9-6", "gpp9-5", "gpp9-4";
1956
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1957
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1958
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1959
+
};
1960
+
1961
+
spi18_cs: spi18-cs-pins {
1962
+
samsung,pins = "gpp9-7";
1963
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1964
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1965
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1966
+
};
1967
+
1968
+
spi18_cs_func: spi18-cs-func-pins {
1969
+
samsung,pins = "gpp9-7";
1970
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1971
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1972
+
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1973
+
};
1974
+
1975
+
uart8_bus_single: uart8-bus-pins {
1976
+
samsung,pins = "gpp5-3", "gpp5-2", "gpp5-1", "gpp5-0";
1977
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1978
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1979
+
};
1980
+
1981
+
uart8_bus_dual: uart8-bus-dual-pins {
1982
+
samsung,pins = "gpp5-0", "gpp5-1";
1983
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1984
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1985
+
};
1986
+
1987
+
uart9_bus_single: uart9-bus-pins {
1988
+
samsung,pins = "gpp5-7", "gpp5-6", "gpp5-5", "gpp5-4";
1989
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1990
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1991
+
};
1992
+
1993
+
uart9_bus_dual: uart9-bus-dual-pins {
1994
+
samsung,pins = "gpp5-4", "gpp5-5";
1995
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1996
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1997
+
};
1998
+
1999
+
uart10_bus_single: uart10-bus-pins {
2000
+
samsung,pins = "gpp6-3", "gpp6-2", "gpp6-1", "gpp6-0";
2001
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2002
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2003
+
};
2004
+
2005
+
uart10_bus_dual: uart10-bus-dual-pins {
2006
+
samsung,pins = "gpp6-0", "gpp6-1";
2007
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2008
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2009
+
};
2010
+
2011
+
uart11_bus_single: uart11-bus-pins {
2012
+
samsung,pins = "gpp6-7", "gpp6-6", "gpp6-5", "gpp6-4";
2013
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2014
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2015
+
};
2016
+
2017
+
uart11_bus_dual: uart11-bus-dual-pins {
2018
+
samsung,pins = "gpp6-4", "gpp6-5";
2019
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2020
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2021
+
};
2022
+
2023
+
uart12_bus_single: uart12-bus-pins {
2024
+
samsung,pins = "gpp7-3", "gpp7-2", "gpp7-1", "gpp7-0";
2025
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2026
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2027
+
};
2028
+
2029
+
uart12_bus_dual: uart12-bus-dual-pins {
2030
+
samsung,pins = "gpp7-0", "gpp7-1";
2031
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2032
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2033
+
};
2034
+
2035
+
uart13_bus_single: uart13-bus-pins {
2036
+
samsung,pins = "gpp7-7", "gpp7-6", "gpp7-5", "gpp7-4";
2037
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2038
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2039
+
};
2040
+
2041
+
uart13_bus_dual: uart13-bus-dual-pins {
2042
+
samsung,pins = "gpp7-4", "gpp7-5";
2043
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2044
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2045
+
};
2046
+
2047
+
uart14_bus_single: uart14-bus-pins {
2048
+
samsung,pins = "gpp8-3", "gpp8-2", "gpp8-1", "gpp8-0";
2049
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2050
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2051
+
};
2052
+
2053
+
uart14_bus_dual: uart14-bus-dual-pins {
2054
+
samsung,pins = "gpp8-0", "gpp8-1";
2055
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2056
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2057
+
};
2058
+
2059
+
uart18_bus_single: uart18-bus-pins {
2060
+
samsung,pins = "gpp8-7", "gpp8-6", "gpp8-5", "gpp8-4";
2061
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2062
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2063
+
};
2064
+
2065
+
uart18_bus_dual: uart18-bus-dual-pins {
2066
+
samsung,pins = "gpp8-4", "gpp8-5";
2067
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2068
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2069
+
};
2070
+
2071
+
uart19_bus_single: uart19-bus-pins {
2072
+
samsung,pins = "gpp9-3", "gpp9-2", "gpp9-1", "gpp9-0";
2073
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2074
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2075
+
};
2076
+
2077
+
uart19_bus_dual: uart19-bus-dual-pins {
2078
+
samsung,pins = "gpp9-0", "gpp9-1";
2079
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2080
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2081
+
};
2082
+
2083
+
uart20_bus_single: uart20-bus-pins {
2084
+
samsung,pins = "gpp9-7", "gpp9-6", "gpp9-5", "gpp9-4";
2085
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2086
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2087
+
};
2088
+
2089
+
uart20_bus_dual: uart20-bus-dual-pins {
2090
+
samsung,pins = "gpp9-4", "gpp9-5";
2091
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2092
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2093
+
};
2094
+
};
2095
+
2096
+
&pinctrl_vts {
2097
+
gpv0: gpv0-gpio-bank {
2098
+
gpio-controller;
2099
+
#gpio-cells = <2>;
2100
+
2101
+
interrupt-controller;
2102
+
#interrupt-cells = <2>;
2103
+
};
2104
+
2105
+
amic_pdm: amic-pdm-pins {
2106
+
samsung,pins = "gpv0-3";
2107
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
2108
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2109
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2110
+
};
2111
+
2112
+
dmic_bus_clk: dmic-bus-clk-pins {
2113
+
samsung,pins = "gpv0-0";
2114
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2115
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
2116
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2117
+
};
2118
+
2119
+
dmic_bus_clk_idle: dmic-bus-clk-idle-pins {
2120
+
samsung,pins = "gpv0-0";
2121
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
2122
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2123
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2124
+
};
2125
+
2126
+
dmic_bus_clk1: dmic-bus-clk1-pins {
2127
+
samsung,pins = "gpv0-1";
2128
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2129
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
2130
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2131
+
};
2132
+
2133
+
dmic_bus_clk1_idle: dmic-bus-clk1-idle-pins {
2134
+
samsung,pins = "gpv0-1";
2135
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
2136
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2137
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2138
+
};
2139
+
2140
+
dmic_bus_clk2: dmic-bus-clk2-pins {
2141
+
samsung,pins = "gpv0-2";
2142
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2143
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
2144
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2145
+
};
2146
+
2147
+
dmic_bus_clk2_idle: dmic-bus-clk2-idle-pins {
2148
+
samsung,pins = "gpv0-2";
2149
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
2150
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2151
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2152
+
};
2153
+
2154
+
dmic_pdm: dmic-pdm-pins {
2155
+
samsung,pins = "gpv0-3";
2156
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2157
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
2158
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2159
+
};
2160
+
2161
+
dmic_pdm_idle: dmic-pdm-idle-pins {
2162
+
samsung,pins = "gpv0-3";
2163
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
2164
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2165
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2166
+
};
2167
+
2168
+
dmic_pdm1_bus: dmic-pdm1-bus-pins {
2169
+
samsung,pins = "gpv0-4";
2170
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2171
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
2172
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2173
+
};
2174
+
2175
+
dmic_pdm1_idle: dmic-pdm1-idle-pins {
2176
+
samsung,pins = "gpv0-4";
2177
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
2178
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2179
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2180
+
};
2181
+
2182
+
dmic_pdm2_bus: dmic-pdm2-bus-pins {
2183
+
samsung,pins = "gpv0-5";
2184
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
2185
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
2186
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2187
+
};
2188
+
2189
+
dmic_pdm2_idle: dmic-pdm2-idle-pins {
2190
+
samsung,pins = "gpv0-5";
2191
+
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
2192
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
2193
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
2194
+
};
2195
+
};
+251
arch/arm64/boot/dts/exynos/exynos990.dtsi
+251
arch/arm64/boot/dts/exynos/exynos990.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung Exynos 990 SoC device tree source
4
+
*
5
+
* Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
10
+
/ {
11
+
compatible = "samsung,exynos990";
12
+
#address-cells = <2>;
13
+
#size-cells = <1>;
14
+
15
+
interrupt-parent = <&gic>;
16
+
17
+
aliases {
18
+
pinctrl0 = &pinctrl_alive;
19
+
pinctrl1 = &pinctrl_cmgp;
20
+
pinctrl2 = &pinctrl_hsi1;
21
+
pinctrl3 = &pinctrl_hsi2;
22
+
pinctrl4 = &pinctrl_peric0;
23
+
pinctrl5 = &pinctrl_peric1;
24
+
pinctrl6 = &pinctrl_vts;
25
+
};
26
+
27
+
arm-a55-pmu {
28
+
compatible = "arm,cortex-a55-pmu";
29
+
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
30
+
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
31
+
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
32
+
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
33
+
34
+
interrupt-affinity = <&cpu0>,
35
+
<&cpu1>,
36
+
<&cpu2>,
37
+
<&cpu3>;
38
+
};
39
+
40
+
arm-a76-pmu {
41
+
compatible = "arm,cortex-a76-pmu";
42
+
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
43
+
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
44
+
45
+
interrupt-affinity = <&cpu4>,
46
+
<&cpu5>;
47
+
};
48
+
49
+
/* There's no PMU model for cluster2, which are the Mongoose cores. */
50
+
51
+
cpus {
52
+
#address-cells = <1>;
53
+
#size-cells = <0>;
54
+
55
+
cpu-map {
56
+
cluster0 {
57
+
core0 {
58
+
cpu = <&cpu0>;
59
+
};
60
+
61
+
core1 {
62
+
cpu = <&cpu1>;
63
+
};
64
+
65
+
core2 {
66
+
cpu = <&cpu2>;
67
+
};
68
+
69
+
core3 {
70
+
cpu = <&cpu3>;
71
+
};
72
+
};
73
+
74
+
cluster1 {
75
+
core0 {
76
+
cpu = <&cpu4>;
77
+
};
78
+
79
+
core1 {
80
+
cpu = <&cpu5>;
81
+
};
82
+
};
83
+
84
+
cluster2 {
85
+
core0 {
86
+
cpu = <&cpu6>;
87
+
};
88
+
89
+
core1 {
90
+
cpu = <&cpu7>;
91
+
};
92
+
};
93
+
};
94
+
95
+
cpu0: cpu@0 {
96
+
device_type = "cpu";
97
+
compatible = "arm,cortex-a55";
98
+
reg = <0x0>;
99
+
enable-method = "psci";
100
+
};
101
+
102
+
cpu1: cpu@1 {
103
+
device_type = "cpu";
104
+
compatible = "arm,cortex-a55";
105
+
reg = <0x1>;
106
+
enable-method = "psci";
107
+
};
108
+
109
+
cpu2: cpu@2 {
110
+
device_type = "cpu";
111
+
compatible = "arm,cortex-a55";
112
+
reg = <0x2>;
113
+
enable-method = "psci";
114
+
};
115
+
116
+
cpu3: cpu@3 {
117
+
device_type = "cpu";
118
+
compatible = "arm,cortex-a55";
119
+
reg = <0x3>;
120
+
enable-method = "psci";
121
+
};
122
+
123
+
cpu4: cpu@100 {
124
+
device_type = "cpu";
125
+
compatible = "arm,cortex-a76";
126
+
reg = <0x4>;
127
+
enable-method = "psci";
128
+
};
129
+
130
+
cpu5: cpu@101 {
131
+
device_type = "cpu";
132
+
compatible = "arm,cortex-a76";
133
+
reg = <0x5>;
134
+
enable-method = "psci";
135
+
};
136
+
137
+
cpu6: cpu@200 {
138
+
device_type = "cpu";
139
+
compatible = "samsung,mongoose-m5";
140
+
reg = <0x6>;
141
+
enable-method = "psci";
142
+
};
143
+
144
+
cpu7: cpu@201 {
145
+
device_type = "cpu";
146
+
compatible = "samsung,mongoose-m5";
147
+
reg = <0x7>;
148
+
enable-method = "psci";
149
+
};
150
+
};
151
+
152
+
oscclk: clock-osc {
153
+
compatible = "fixed-clock";
154
+
#clock-cells = <0>;
155
+
clock-output-names = "oscclk";
156
+
};
157
+
158
+
psci {
159
+
compatible = "arm,psci-0.2";
160
+
method = "hvc";
161
+
};
162
+
163
+
soc: soc@0 {
164
+
compatible = "simple-bus";
165
+
ranges = <0x0 0x0 0x0 0x20000000>;
166
+
167
+
#address-cells = <1>;
168
+
#size-cells = <1>;
169
+
170
+
chipid@10000000 {
171
+
compatible = "samsung,exynos990-chipid",
172
+
"samsung,exynos850-chipid";
173
+
reg = <0x10000000 0x100>;
174
+
};
175
+
176
+
gic: interrupt-controller@10101000 {
177
+
compatible = "arm,gic-400";
178
+
reg = <0x10101000 0x1000>,
179
+
<0x10102000 0x1000>,
180
+
<0x10104000 0x2000>,
181
+
<0x10106000 0x2000>;
182
+
#interrupt-cells = <3>;
183
+
interrupt-controller;
184
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
185
+
IRQ_TYPE_LEVEL_HIGH)>;
186
+
#address-cells = <0>;
187
+
#size-cells = <1>;
188
+
};
189
+
190
+
pinctrl_peric0: pinctrl@10430000 {
191
+
compatible = "samsung,exynos990-pinctrl";
192
+
reg = <0x10430000 0x1000>;
193
+
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
194
+
};
195
+
196
+
pinctrl_peric1: pinctrl@10730000 {
197
+
compatible = "samsung,exynos990-pinctrl";
198
+
reg = <0x10730000 0x1000>;
199
+
interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
200
+
};
201
+
202
+
pinctrl_hsi1: pinctrl@13040000 {
203
+
compatible = "samsung,exynos990-pinctrl";
204
+
reg = <0x13040000 0x1000>;
205
+
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
206
+
};
207
+
208
+
pinctrl_hsi2: pinctrl@13c30000 {
209
+
compatible = "samsung,exynos990-pinctrl";
210
+
reg = <0x13c30000 0x1000>;
211
+
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
212
+
};
213
+
214
+
pinctrl_vts: pinctrl@15580000 {
215
+
compatible = "samsung,exynos990-pinctrl";
216
+
reg = <0x15580000 0x1000>;
217
+
};
218
+
219
+
pinctrl_alive: pinctrl@15850000 {
220
+
compatible = "samsung,exynos990-pinctrl";
221
+
reg = <0x15850000 0x1000>;
222
+
223
+
wakeup-interrupt-controller {
224
+
compatible = "samsung,exynos990-wakeup-eint",
225
+
"samsung,exynos850-wakeup-eint",
226
+
"samsung,exynos7-wakeup-eint";
227
+
};
228
+
};
229
+
230
+
pinctrl_cmgp: pinctrl@15c30000 {
231
+
compatible = "samsung,exynos990-pinctrl";
232
+
reg = <0x15c30000 0x1000>;
233
+
};
234
+
};
235
+
236
+
timer {
237
+
compatible = "arm,armv8-timer";
238
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
239
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
240
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
241
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
242
+
243
+
/*
244
+
* Non-updatable, broken stock Samsung bootloader does not
245
+
* configure CNTFRQ_EL0
246
+
*/
247
+
clock-frequency = <26000000>;
248
+
};
249
+
};
250
+
251
+
#include "exynos990-pinctrl.dtsi"
+50
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+50
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
···
172
172
reg = <0x10000000 0x24>;
173
173
};
174
174
175
+
cmu_misc: clock-controller@10020000 {
176
+
compatible = "samsung,exynosautov920-cmu-misc";
177
+
reg = <0x10020000 0x8000>;
178
+
#clock-cells = <1>;
179
+
180
+
clocks = <&xtcxo>,
181
+
<&cmu_top DOUT_CLKCMU_MISC_NOC>;
182
+
clock-names = "oscclk",
183
+
"noc";
184
+
};
185
+
175
186
gic: interrupt-controller@10400000 {
176
187
compatible = "arm,gic-v3";
177
188
#interrupt-cells = <3>;
···
258
247
status = "disabled";
259
248
};
260
249
250
+
cmu_peric1: clock-controller@10c00000 {
251
+
compatible = "samsung,exynosautov920-cmu-peric1";
252
+
reg = <0x10c00000 0x8000>;
253
+
#clock-cells = <1>;
254
+
255
+
clocks = <&xtcxo>,
256
+
<&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
257
+
<&cmu_top DOUT_CLKCMU_PERIC1_IP>;
258
+
clock-names = "oscclk",
259
+
"noc",
260
+
"ip";
261
+
};
262
+
261
263
syscon_peric1: syscon@10c20000 {
262
264
compatible = "samsung,exynosautov920-peric1-sysreg",
263
265
"syscon";
···
307
283
reg = <0x11860000 0x10000>;
308
284
};
309
285
286
+
cmu_hsi0: clock-controller@16000000 {
287
+
compatible = "samsung,exynosautov920-cmu-hsi0";
288
+
reg = <0x16000000 0x8000>;
289
+
#clock-cells = <1>;
290
+
291
+
clocks = <&xtcxo>,
292
+
<&cmu_top DOUT_CLKCMU_HSI0_NOC>;
293
+
clock-names = "oscclk",
294
+
"noc";
295
+
};
296
+
310
297
pinctrl_hsi0: pinctrl@16040000 {
311
298
compatible = "samsung,exynosautov920-pinctrl";
312
299
reg = <0x16040000 0x10000>;
313
300
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
301
+
};
302
+
303
+
cmu_hsi1: clock-controller@16400000 {
304
+
compatible = "samsung,exynosautov920-cmu-hsi1";
305
+
reg = <0x16400000 0x8000>;
306
+
#clock-cells = <1>;
307
+
308
+
clocks = <&xtcxo>,
309
+
<&cmu_top DOUT_CLKCMU_HSI1_NOC>,
310
+
<&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
311
+
<&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
312
+
clock-names = "oscclk",
313
+
"noc",
314
+
"usbdrd",
315
+
"mmc_card";
314
316
};
315
317
316
318
pinctrl_hsi1: pinctrl@16450000 {
+453
include/dt-bindings/clock/samsung,exynos8895.h
+453
include/dt-bindings/clock/samsung,exynos8895.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
4
+
* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
5
+
*
6
+
* Device Tree binding constants for Exynos8895 clock controller.
7
+
*/
8
+
9
+
#ifndef _DT_BINDINGS_CLOCK_EXYNOS8895_H
10
+
#define _DT_BINDINGS_CLOCK_EXYNOS8895_H
11
+
12
+
/* CMU_TOP */
13
+
#define CLK_FOUT_SHARED0_PLL 1
14
+
#define CLK_FOUT_SHARED1_PLL 2
15
+
#define CLK_FOUT_SHARED2_PLL 3
16
+
#define CLK_FOUT_SHARED3_PLL 4
17
+
#define CLK_FOUT_SHARED4_PLL 5
18
+
#define CLK_MOUT_PLL_SHARED0 6
19
+
#define CLK_MOUT_PLL_SHARED1 7
20
+
#define CLK_MOUT_PLL_SHARED2 8
21
+
#define CLK_MOUT_PLL_SHARED3 9
22
+
#define CLK_MOUT_PLL_SHARED4 10
23
+
#define CLK_MOUT_CP2AP_MIF_CLK_USER 11
24
+
#define CLK_MOUT_CMU_ABOX_CPUABOX 12
25
+
#define CLK_MOUT_CMU_APM_BUS 13
26
+
#define CLK_MOUT_CMU_BUS1_BUS 14
27
+
#define CLK_MOUT_CMU_BUSC_BUS 15
28
+
#define CLK_MOUT_CMU_BUSC_BUSPHSI2C 16
29
+
#define CLK_MOUT_CMU_CAM_BUS 17
30
+
#define CLK_MOUT_CMU_CAM_TPU0 18
31
+
#define CLK_MOUT_CMU_CAM_TPU1 19
32
+
#define CLK_MOUT_CMU_CAM_VRA 20
33
+
#define CLK_MOUT_CMU_CIS_CLK0 21
34
+
#define CLK_MOUT_CMU_CIS_CLK1 22
35
+
#define CLK_MOUT_CMU_CIS_CLK2 23
36
+
#define CLK_MOUT_CMU_CIS_CLK3 24
37
+
#define CLK_MOUT_CMU_CORE_BUS 25
38
+
#define CLK_MOUT_CMU_CPUCL0_SWITCH 26
39
+
#define CLK_MOUT_CMU_CPUCL1_SWITCH 27
40
+
#define CLK_MOUT_CMU_DBG_BUS 28
41
+
#define CLK_MOUT_CMU_DCAM_BUS 29
42
+
#define CLK_MOUT_CMU_DCAM_IMGD 30
43
+
#define CLK_MOUT_CMU_DPU_BUS 31
44
+
#define CLK_MOUT_CMU_DROOPDETECTOR 32
45
+
#define CLK_MOUT_CMU_DSP_BUS 33
46
+
#define CLK_MOUT_CMU_FSYS0_BUS 34
47
+
#define CLK_MOUT_CMU_FSYS0_DPGTC 35
48
+
#define CLK_MOUT_CMU_FSYS0_MMC_EMBD 36
49
+
#define CLK_MOUT_CMU_FSYS0_UFS_EMBD 37
50
+
#define CLK_MOUT_CMU_FSYS0_USBDRD30 38
51
+
#define CLK_MOUT_CMU_FSYS1_BUS 39
52
+
#define CLK_MOUT_CMU_FSYS1_MMC_CARD 40
53
+
#define CLK_MOUT_CMU_FSYS1_PCIE 41
54
+
#define CLK_MOUT_CMU_FSYS1_UFS_CARD 42
55
+
#define CLK_MOUT_CMU_G2D_G2D 43
56
+
#define CLK_MOUT_CMU_G2D_JPEG 44
57
+
#define CLK_MOUT_CMU_HPM 45
58
+
#define CLK_MOUT_CMU_IMEM_BUS 46
59
+
#define CLK_MOUT_CMU_ISPHQ_BUS 47
60
+
#define CLK_MOUT_CMU_ISPLP_BUS 48
61
+
#define CLK_MOUT_CMU_IVA_BUS 49
62
+
#define CLK_MOUT_CMU_MFC_BUS 50
63
+
#define CLK_MOUT_CMU_MIF_SWITCH 51
64
+
#define CLK_MOUT_CMU_PERIC0_BUS 52
65
+
#define CLK_MOUT_CMU_PERIC0_UART_DBG 53
66
+
#define CLK_MOUT_CMU_PERIC0_USI00 54
67
+
#define CLK_MOUT_CMU_PERIC0_USI01 55
68
+
#define CLK_MOUT_CMU_PERIC0_USI02 56
69
+
#define CLK_MOUT_CMU_PERIC0_USI03 57
70
+
#define CLK_MOUT_CMU_PERIC1_BUS 58
71
+
#define CLK_MOUT_CMU_PERIC1_SPEEDY2 59
72
+
#define CLK_MOUT_CMU_PERIC1_SPI_CAM0 60
73
+
#define CLK_MOUT_CMU_PERIC1_SPI_CAM1 61
74
+
#define CLK_MOUT_CMU_PERIC1_UART_BT 62
75
+
#define CLK_MOUT_CMU_PERIC1_USI04 63
76
+
#define CLK_MOUT_CMU_PERIC1_USI05 64
77
+
#define CLK_MOUT_CMU_PERIC1_USI06 65
78
+
#define CLK_MOUT_CMU_PERIC1_USI07 66
79
+
#define CLK_MOUT_CMU_PERIC1_USI08 67
80
+
#define CLK_MOUT_CMU_PERIC1_USI09 68
81
+
#define CLK_MOUT_CMU_PERIC1_USI10 69
82
+
#define CLK_MOUT_CMU_PERIC1_USI11 70
83
+
#define CLK_MOUT_CMU_PERIC1_USI12 71
84
+
#define CLK_MOUT_CMU_PERIC1_USI13 72
85
+
#define CLK_MOUT_CMU_PERIS_BUS 73
86
+
#define CLK_MOUT_CMU_SRDZ_BUS 74
87
+
#define CLK_MOUT_CMU_SRDZ_IMGD 75
88
+
#define CLK_MOUT_CMU_VPU_BUS 76
89
+
#define CLK_DOUT_CMU_ABOX_CPUABOX 77
90
+
#define CLK_DOUT_CMU_APM_BUS 78
91
+
#define CLK_DOUT_CMU_BUS1_BUS 79
92
+
#define CLK_DOUT_CMU_BUSC_BUS 80
93
+
#define CLK_DOUT_CMU_BUSC_BUSPHSI2C 81
94
+
#define CLK_DOUT_CMU_CAM_BUS 82
95
+
#define CLK_DOUT_CMU_CAM_TPU0 83
96
+
#define CLK_DOUT_CMU_CAM_TPU1 84
97
+
#define CLK_DOUT_CMU_CAM_VRA 85
98
+
#define CLK_DOUT_CMU_CIS_CLK0 86
99
+
#define CLK_DOUT_CMU_CIS_CLK1 87
100
+
#define CLK_DOUT_CMU_CIS_CLK2 88
101
+
#define CLK_DOUT_CMU_CIS_CLK3 89
102
+
#define CLK_DOUT_CMU_CORE_BUS 90
103
+
#define CLK_DOUT_CMU_CPUCL0_SWITCH 91
104
+
#define CLK_DOUT_CMU_CPUCL1_SWITCH 92
105
+
#define CLK_DOUT_CMU_DBG_BUS 93
106
+
#define CLK_DOUT_CMU_DCAM_BUS 94
107
+
#define CLK_DOUT_CMU_DCAM_IMGD 95
108
+
#define CLK_DOUT_CMU_DPU_BUS 96
109
+
#define CLK_DOUT_CMU_DSP_BUS 97
110
+
#define CLK_DOUT_CMU_FSYS0_BUS 98
111
+
#define CLK_DOUT_CMU_FSYS0_DPGTC 99
112
+
#define CLK_DOUT_CMU_FSYS0_MMC_EMBD 100
113
+
#define CLK_DOUT_CMU_FSYS0_UFS_EMBD 101
114
+
#define CLK_DOUT_CMU_FSYS0_USBDRD30 102
115
+
#define CLK_DOUT_CMU_FSYS1_BUS 103
116
+
#define CLK_DOUT_CMU_FSYS1_MMC_CARD 104
117
+
#define CLK_DOUT_CMU_FSYS1_UFS_CARD 105
118
+
#define CLK_DOUT_CMU_G2D_G2D 106
119
+
#define CLK_DOUT_CMU_G2D_JPEG 107
120
+
#define CLK_DOUT_CMU_G3D_SWITCH 108
121
+
#define CLK_DOUT_CMU_HPM 109
122
+
#define CLK_DOUT_CMU_IMEM_BUS 110
123
+
#define CLK_DOUT_CMU_ISPHQ_BUS 111
124
+
#define CLK_DOUT_CMU_ISPLP_BUS 112
125
+
#define CLK_DOUT_CMU_IVA_BUS 113
126
+
#define CLK_DOUT_CMU_MFC_BUS 114
127
+
#define CLK_DOUT_CMU_MODEM_SHARED0 115
128
+
#define CLK_DOUT_CMU_MODEM_SHARED1 116
129
+
#define CLK_DOUT_CMU_PERIC0_BUS 117
130
+
#define CLK_DOUT_CMU_PERIC0_UART_DBG 118
131
+
#define CLK_DOUT_CMU_PERIC0_USI00 119
132
+
#define CLK_DOUT_CMU_PERIC0_USI01 120
133
+
#define CLK_DOUT_CMU_PERIC0_USI02 121
134
+
#define CLK_DOUT_CMU_PERIC0_USI03 122
135
+
#define CLK_DOUT_CMU_PERIC1_BUS 123
136
+
#define CLK_DOUT_CMU_PERIC1_SPEEDY2 124
137
+
#define CLK_DOUT_CMU_PERIC1_SPI_CAM0 125
138
+
#define CLK_DOUT_CMU_PERIC1_SPI_CAM1 126
139
+
#define CLK_DOUT_CMU_PERIC1_UART_BT 127
140
+
#define CLK_DOUT_CMU_PERIC1_USI04 128
141
+
#define CLK_DOUT_CMU_PERIC1_USI05 129
142
+
#define CLK_DOUT_CMU_PERIC1_USI06 130
143
+
#define CLK_DOUT_CMU_PERIC1_USI07 131
144
+
#define CLK_DOUT_CMU_PERIC1_USI08 132
145
+
#define CLK_DOUT_CMU_PERIC1_USI09 133
146
+
#define CLK_DOUT_CMU_PERIC1_USI10 134
147
+
#define CLK_DOUT_CMU_PERIC1_USI11 135
148
+
#define CLK_DOUT_CMU_PERIC1_USI12 136
149
+
#define CLK_DOUT_CMU_PERIC1_USI13 137
150
+
#define CLK_DOUT_CMU_PERIS_BUS 138
151
+
#define CLK_DOUT_CMU_SRDZ_BUS 139
152
+
#define CLK_DOUT_CMU_SRDZ_IMGD 140
153
+
#define CLK_DOUT_CMU_VPU_BUS 141
154
+
#define CLK_DOUT_CMU_SHARED0_DIV2 142
155
+
#define CLK_DOUT_CMU_SHARED0_DIV4 143
156
+
#define CLK_DOUT_CMU_SHARED1_DIV2 144
157
+
#define CLK_DOUT_CMU_SHARED1_DIV4 145
158
+
#define CLK_DOUT_CMU_SHARED2_DIV2 146
159
+
#define CLK_DOUT_CMU_SHARED3_DIV2 147
160
+
#define CLK_DOUT_CMU_SHARED4_DIV2 148
161
+
#define CLK_DOUT_CMU_FSYS1_PCIE 149
162
+
#define CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2 150
163
+
#define CLK_DOUT_CMU_CMU_OTP 151
164
+
#define CLK_GOUT_CMU_DROOPDETECTOR 152
165
+
#define CLK_GOUT_CMU_MIF_SWITCH 153
166
+
#define CLK_GOUT_CMU_ABOX_CPUABOX 154
167
+
#define CLK_GOUT_CMU_APM_BUS 155
168
+
#define CLK_GOUT_CMU_BUS1_BUS 156
169
+
#define CLK_GOUT_CMU_BUSC_BUS 157
170
+
#define CLK_GOUT_CMU_BUSC_BUSPHSI2C 158
171
+
#define CLK_GOUT_CMU_CAM_BUS 159
172
+
#define CLK_GOUT_CMU_CAM_TPU0 160
173
+
#define CLK_GOUT_CMU_CAM_TPU1 161
174
+
#define CLK_GOUT_CMU_CAM_VRA 162
175
+
#define CLK_GOUT_CMU_CIS_CLK0 163
176
+
#define CLK_GOUT_CMU_CIS_CLK1 164
177
+
#define CLK_GOUT_CMU_CIS_CLK2 165
178
+
#define CLK_GOUT_CMU_CIS_CLK3 166
179
+
#define CLK_GOUT_CMU_CORE_BUS 167
180
+
#define CLK_GOUT_CMU_CPUCL0_SWITCH 168
181
+
#define CLK_GOUT_CMU_CPUCL1_SWITCH 169
182
+
#define CLK_GOUT_CMU_DBG_BUS 170
183
+
#define CLK_GOUT_CMU_DCAM_BUS 171
184
+
#define CLK_GOUT_CMU_DCAM_IMGD 172
185
+
#define CLK_GOUT_CMU_DPU_BUS 173
186
+
#define CLK_GOUT_CMU_DSP_BUS 174
187
+
#define CLK_GOUT_CMU_FSYS0_BUS 175
188
+
#define CLK_GOUT_CMU_FSYS0_DPGTC 176
189
+
#define CLK_GOUT_CMU_FSYS0_MMC_EMBD 177
190
+
#define CLK_GOUT_CMU_FSYS0_UFS_EMBD 178
191
+
#define CLK_GOUT_CMU_FSYS0_USBDRD30 179
192
+
#define CLK_GOUT_CMU_FSYS1_BUS 180
193
+
#define CLK_GOUT_CMU_FSYS1_MMC_CARD 181
194
+
#define CLK_GOUT_CMU_FSYS1_PCIE 182
195
+
#define CLK_GOUT_CMU_FSYS1_UFS_CARD 183
196
+
#define CLK_GOUT_CMU_G2D_G2D 184
197
+
#define CLK_GOUT_CMU_G2D_JPEG 185
198
+
#define CLK_GOUT_CMU_G3D_SWITCH 186
199
+
#define CLK_GOUT_CMU_HPM 187
200
+
#define CLK_GOUT_CMU_IMEM_BUS 188
201
+
#define CLK_GOUT_CMU_ISPHQ_BUS 189
202
+
#define CLK_GOUT_CMU_ISPLP_BUS 190
203
+
#define CLK_GOUT_CMU_IVA_BUS 191
204
+
#define CLK_GOUT_CMU_MFC_BUS 192
205
+
#define CLK_GOUT_CMU_MODEM_SHARED0 193
206
+
#define CLK_GOUT_CMU_MODEM_SHARED1 194
207
+
#define CLK_GOUT_CMU_PERIC0_BUS 195
208
+
#define CLK_GOUT_CMU_PERIC0_UART_DBG 196
209
+
#define CLK_GOUT_CMU_PERIC0_USI00 197
210
+
#define CLK_GOUT_CMU_PERIC0_USI01 198
211
+
#define CLK_GOUT_CMU_PERIC0_USI02 199
212
+
#define CLK_GOUT_CMU_PERIC0_USI03 200
213
+
#define CLK_GOUT_CMU_PERIC1_BUS 201
214
+
#define CLK_GOUT_CMU_PERIC1_SPEEDY2 202
215
+
#define CLK_GOUT_CMU_PERIC1_SPI_CAM0 203
216
+
#define CLK_GOUT_CMU_PERIC1_SPI_CAM1 204
217
+
#define CLK_GOUT_CMU_PERIC1_UART_BT 205
218
+
#define CLK_GOUT_CMU_PERIC1_USI04 206
219
+
#define CLK_GOUT_CMU_PERIC1_USI05 207
220
+
#define CLK_GOUT_CMU_PERIC1_USI06 208
221
+
#define CLK_GOUT_CMU_PERIC1_USI07 209
222
+
#define CLK_GOUT_CMU_PERIC1_USI08 210
223
+
#define CLK_GOUT_CMU_PERIC1_USI09 211
224
+
#define CLK_GOUT_CMU_PERIC1_USI10 212
225
+
#define CLK_GOUT_CMU_PERIC1_USI11 213
226
+
#define CLK_GOUT_CMU_PERIC1_USI12 214
227
+
#define CLK_GOUT_CMU_PERIC1_USI13 215
228
+
#define CLK_GOUT_CMU_PERIS_BUS 216
229
+
#define CLK_GOUT_CMU_SRDZ_BUS 217
230
+
#define CLK_GOUT_CMU_SRDZ_IMGD 218
231
+
#define CLK_GOUT_CMU_VPU_BUS 219
232
+
233
+
/* CMU_PERIS */
234
+
#define CLK_MOUT_PERIS_BUS_USER 1
235
+
#define CLK_MOUT_PERIS_GIC 2
236
+
#define CLK_GOUT_PERIS_CMU_PERIS_PCLK 3
237
+
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 4
238
+
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS 5
239
+
#define CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK 6
240
+
#define CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK 7
241
+
#define CLK_GOUT_PERIS_BUSIF_TMU_PCLK 8
242
+
#define CLK_GOUT_PERIS_GIC_CLK 9
243
+
#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK 10
244
+
#define CLK_GOUT_PERIS_MCT_PCLK 11
245
+
#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 12
246
+
#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 13
247
+
#define CLK_GOUT_PERIS_PMU_PERIS_PCLK 14
248
+
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK 15
249
+
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK 16
250
+
#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 17
251
+
#define CLK_GOUT_PERIS_TZPC00_PCLK 18
252
+
#define CLK_GOUT_PERIS_TZPC01_PCLK 19
253
+
#define CLK_GOUT_PERIS_TZPC02_PCLK 20
254
+
#define CLK_GOUT_PERIS_TZPC03_PCLK 21
255
+
#define CLK_GOUT_PERIS_TZPC04_PCLK 22
256
+
#define CLK_GOUT_PERIS_TZPC05_PCLK 23
257
+
#define CLK_GOUT_PERIS_TZPC06_PCLK 24
258
+
#define CLK_GOUT_PERIS_TZPC07_PCLK 25
259
+
#define CLK_GOUT_PERIS_TZPC08_PCLK 26
260
+
#define CLK_GOUT_PERIS_TZPC09_PCLK 27
261
+
#define CLK_GOUT_PERIS_TZPC10_PCLK 28
262
+
#define CLK_GOUT_PERIS_TZPC11_PCLK 29
263
+
#define CLK_GOUT_PERIS_TZPC12_PCLK 30
264
+
#define CLK_GOUT_PERIS_TZPC13_PCLK 31
265
+
#define CLK_GOUT_PERIS_TZPC14_PCLK 32
266
+
#define CLK_GOUT_PERIS_TZPC15_PCLK 33
267
+
#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 34
268
+
#define CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK 35
269
+
#define CLK_GOUT_PERIS_XIU_P_PERIS_ACLK 36
270
+
271
+
/* CMU_FSYS0 */
272
+
#define CLK_MOUT_FSYS0_BUS_USER 1
273
+
#define CLK_MOUT_FSYS0_DPGTC_USER 2
274
+
#define CLK_MOUT_FSYS0_MMC_EMBD_USER 3
275
+
#define CLK_MOUT_FSYS0_UFS_EMBD_USER 4
276
+
#define CLK_MOUT_FSYS0_USBDRD30_USER 5
277
+
#define CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK 6
278
+
#define CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK 7
279
+
#define CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK 8
280
+
#define CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK 9
281
+
#define CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK 10
282
+
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK 11
283
+
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK 12
284
+
#define CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK 13
285
+
#define CLK_GOUT_FSYS0_DP_LINK_I_PCLK 14
286
+
#define CLK_GOUT_FSYS0_ETR_MIU_I_ACLK 15
287
+
#define CLK_GOUT_FSYS0_ETR_MIU_I_PCLK 16
288
+
#define CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK 17
289
+
#define CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK 18
290
+
#define CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK 19
291
+
#define CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK 20
292
+
#define CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK 21
293
+
#define CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK 22
294
+
#define CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN 23
295
+
#define CLK_GOUT_FSYS0_PMU_FSYS0_PCLK 24
296
+
#define CLK_GOUT_FSYS0_BCM_FSYS0_ACLK 25
297
+
#define CLK_GOUT_FSYS0_BCM_FSYS0_PCLK 26
298
+
#define CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK 27
299
+
#define CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK 28
300
+
#define CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK 29
301
+
#define CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO 30
302
+
#define CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK 31
303
+
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK 32
304
+
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK 33
305
+
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK 34
306
+
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK 35
307
+
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK 36
308
+
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK 37
309
+
#define CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK 38
310
+
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK 39
311
+
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK 40
312
+
#define CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK 41
313
+
314
+
/* CMU_FSYS1 */
315
+
#define CLK_MOUT_FSYS1_BUS_USER 1
316
+
#define CLK_MOUT_FSYS1_MMC_CARD_USER 2
317
+
#define CLK_MOUT_FSYS1_PCIE_USER 3
318
+
#define CLK_MOUT_FSYS1_UFS_CARD_USER 4
319
+
#define CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN 5
320
+
#define CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM 6
321
+
#define CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK 7
322
+
#define CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK 8
323
+
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK 9
324
+
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK 10
325
+
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK 11
326
+
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK 12
327
+
#define CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK 13
328
+
#define CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK 14
329
+
#define CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK 15
330
+
#define CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK 16
331
+
#define CLK_GOUT_FSYS1_MMC_CARD_I_ACLK 17
332
+
#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 18
333
+
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0 19
334
+
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1 20
335
+
#define CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 21
336
+
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0 22
337
+
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1 23
338
+
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 24
339
+
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 25
340
+
#define CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 26
341
+
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0 27
342
+
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1 28
343
+
#define CLK_GOUT_FSYS1_PMU_FSYS1_PCLK 29
344
+
#define CLK_GOUT_FSYS1_BCM_FSYS1_ACLK 30
345
+
#define CLK_GOUT_FSYS1_BCM_FSYS1_PCLK 31
346
+
#define CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK 32
347
+
#define CLK_GOUT_FSYS1_RTIC_I_ACLK 33
348
+
#define CLK_GOUT_FSYS1_RTIC_I_PCLK 34
349
+
#define CLK_GOUT_FSYS1_SSS_I_ACLK 35
350
+
#define CLK_GOUT_FSYS1_SSS_I_PCLK 36
351
+
#define CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK 37
352
+
#define CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK 38
353
+
#define CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK 39
354
+
#define CLK_GOUT_FSYS1_UFS_CARD_I_ACLK 40
355
+
#define CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO 41
356
+
#define CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK 42
357
+
#define CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK 43
358
+
#define CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK 44
359
+
360
+
/* CMU_PERIC0 */
361
+
#define CLK_MOUT_PERIC0_BUS_USER 1
362
+
#define CLK_MOUT_PERIC0_UART_DBG_USER 2
363
+
#define CLK_MOUT_PERIC0_USI00_USER 3
364
+
#define CLK_MOUT_PERIC0_USI01_USER 4
365
+
#define CLK_MOUT_PERIC0_USI02_USER 5
366
+
#define CLK_MOUT_PERIC0_USI03_USER 6
367
+
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 7
368
+
#define CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK 8
369
+
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 9
370
+
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 10
371
+
#define CLK_GOUT_PERIC0_PMU_PERIC0_PCLK 11
372
+
#define CLK_GOUT_PERIC0_PWM_I_PCLK_S0 12
373
+
#define CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK 13
374
+
#define CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK 14
375
+
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 15
376
+
#define CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK 16
377
+
#define CLK_GOUT_PERIC0_UART_DBG_PCLK 17
378
+
#define CLK_GOUT_PERIC0_USI00_I_PCLK 18
379
+
#define CLK_GOUT_PERIC0_USI00_I_SCLK_USI 19
380
+
#define CLK_GOUT_PERIC0_USI01_I_PCLK 20
381
+
#define CLK_GOUT_PERIC0_USI01_I_SCLK_USI 21
382
+
#define CLK_GOUT_PERIC0_USI02_I_PCLK 22
383
+
#define CLK_GOUT_PERIC0_USI02_I_SCLK_USI 23
384
+
#define CLK_GOUT_PERIC0_USI03_I_PCLK 24
385
+
#define CLK_GOUT_PERIC0_USI03_I_SCLK_USI 25
386
+
387
+
/* CMU_PERIC1 */
388
+
#define CLK_MOUT_PERIC1_BUS_USER 1
389
+
#define CLK_MOUT_PERIC1_SPEEDY2_USER 2
390
+
#define CLK_MOUT_PERIC1_SPI_CAM0_USER 3
391
+
#define CLK_MOUT_PERIC1_SPI_CAM1_USER 4
392
+
#define CLK_MOUT_PERIC1_UART_BT_USER 5
393
+
#define CLK_MOUT_PERIC1_USI04_USER 6
394
+
#define CLK_MOUT_PERIC1_USI05_USER 7
395
+
#define CLK_MOUT_PERIC1_USI06_USER 8
396
+
#define CLK_MOUT_PERIC1_USI07_USER 9
397
+
#define CLK_MOUT_PERIC1_USI08_USER 10
398
+
#define CLK_MOUT_PERIC1_USI09_USER 11
399
+
#define CLK_MOUT_PERIC1_USI10_USER 12
400
+
#define CLK_MOUT_PERIC1_USI11_USER 13
401
+
#define CLK_MOUT_PERIC1_USI12_USER 14
402
+
#define CLK_MOUT_PERIC1_USI13_USER 15
403
+
#define CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK 16
404
+
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK 17
405
+
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK 18
406
+
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK 19
407
+
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK 20
408
+
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 21
409
+
#define CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK 22
410
+
#define CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK 23
411
+
#define CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK 24
412
+
#define CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK 25
413
+
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 26
414
+
#define CLK_GOUT_PERIC1_PMU_PERIC1_PCLK 27
415
+
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK 28
416
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK 29
417
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK 30
418
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK 31
419
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK 32
420
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK 33
421
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK 34
422
+
#define CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK 35
423
+
#define CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK 36
424
+
#define CLK_GOUT_PERIC1_SPI_CAM0_PCLK 37
425
+
#define CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK 38
426
+
#define CLK_GOUT_PERIC1_SPI_CAM1_PCLK 39
427
+
#define CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK 40
428
+
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 41
429
+
#define CLK_GOUT_PERIC1_UART_BT_EXT_UCLK 42
430
+
#define CLK_GOUT_PERIC1_UART_BT_PCLK 43
431
+
#define CLK_GOUT_PERIC1_USI04_I_PCLK 44
432
+
#define CLK_GOUT_PERIC1_USI04_I_SCLK_USI 45
433
+
#define CLK_GOUT_PERIC1_USI05_I_PCLK 46
434
+
#define CLK_GOUT_PERIC1_USI05_I_SCLK_USI 47
435
+
#define CLK_GOUT_PERIC1_USI06_I_PCLK 48
436
+
#define CLK_GOUT_PERIC1_USI06_I_SCLK_USI 49
437
+
#define CLK_GOUT_PERIC1_USI07_I_PCLK 50
438
+
#define CLK_GOUT_PERIC1_USI07_I_SCLK_USI 51
439
+
#define CLK_GOUT_PERIC1_USI08_I_PCLK 52
440
+
#define CLK_GOUT_PERIC1_USI08_I_SCLK_USI 53
441
+
#define CLK_GOUT_PERIC1_USI09_I_PCLK 54
442
+
#define CLK_GOUT_PERIC1_USI09_I_SCLK_USI 55
443
+
#define CLK_GOUT_PERIC1_USI10_I_PCLK 56
444
+
#define CLK_GOUT_PERIC1_USI10_I_SCLK_USI 57
445
+
#define CLK_GOUT_PERIC1_USI11_I_PCLK 58
446
+
#define CLK_GOUT_PERIC1_USI11_I_SCLK_USI 59
447
+
#define CLK_GOUT_PERIC1_USI12_I_PCLK 60
448
+
#define CLK_GOUT_PERIC1_USI12_I_SCLK_USI 61
449
+
#define CLK_GOUT_PERIC1_USI13_I_PCLK 62
450
+
#define CLK_GOUT_PERIC1_USI13_I_SCLK_USI 63
451
+
#define CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK 64
452
+
453
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS8895_H */
+47
include/dt-bindings/clock/samsung,exynosautov920.h
+47
include/dt-bindings/clock/samsung,exynosautov920.h
···
160
160
#define DOUT_CLKCMU_SNW_NOC 144
161
161
#define DOUT_CLKCMU_SSP_NOC 145
162
162
#define DOUT_CLKCMU_TAA_NOC 146
163
+
#define DOUT_TCXO_DIV2 147
163
164
164
165
/* CMU_PERIC0 */
165
166
#define CLK_MOUT_PERIC0_IP_USER 1
···
188
187
#define CLK_DOUT_PERIC0_USI08_USI 22
189
188
#define CLK_DOUT_PERIC0_USI_I2C 23
190
189
#define CLK_DOUT_PERIC0_I3C 24
190
+
191
+
/* CMU_PERIC1 */
192
+
#define CLK_MOUT_PERIC1_IP_USER 1
193
+
#define CLK_MOUT_PERIC1_NOC_USER 2
194
+
#define CLK_MOUT_PERIC1_USI09_USI 3
195
+
#define CLK_MOUT_PERIC1_USI10_USI 4
196
+
#define CLK_MOUT_PERIC1_USI11_USI 5
197
+
#define CLK_MOUT_PERIC1_USI12_USI 6
198
+
#define CLK_MOUT_PERIC1_USI13_USI 7
199
+
#define CLK_MOUT_PERIC1_USI14_USI 8
200
+
#define CLK_MOUT_PERIC1_USI15_USI 9
201
+
#define CLK_MOUT_PERIC1_USI16_USI 10
202
+
#define CLK_MOUT_PERIC1_USI17_USI 11
203
+
#define CLK_MOUT_PERIC1_USI_I2C 12
204
+
#define CLK_MOUT_PERIC1_I3C 13
205
+
206
+
#define CLK_DOUT_PERIC1_USI09_USI 14
207
+
#define CLK_DOUT_PERIC1_USI10_USI 15
208
+
#define CLK_DOUT_PERIC1_USI11_USI 16
209
+
#define CLK_DOUT_PERIC1_USI12_USI 17
210
+
#define CLK_DOUT_PERIC1_USI13_USI 18
211
+
#define CLK_DOUT_PERIC1_USI14_USI 19
212
+
#define CLK_DOUT_PERIC1_USI15_USI 20
213
+
#define CLK_DOUT_PERIC1_USI16_USI 21
214
+
#define CLK_DOUT_PERIC1_USI17_USI 22
215
+
#define CLK_DOUT_PERIC1_USI_I2C 23
216
+
#define CLK_DOUT_PERIC1_I3C 24
217
+
218
+
/* CMU_MISC */
219
+
#define CLK_MOUT_MISC_NOC_USER 1
220
+
#define CLK_MOUT_MISC_GIC 2
221
+
222
+
#define CLK_DOUT_MISC_OTP 3
223
+
#define CLK_DOUT_MISC_NOCP 4
224
+
#define CLK_DOUT_MISC_OSC_DIV2 5
225
+
226
+
/* CMU_HSI0 */
227
+
#define CLK_MOUT_HSI0_NOC_USER 1
228
+
229
+
#define CLK_DOUT_HSI0_PCIE_APB 2
230
+
231
+
/* CMU_HSI1 */
232
+
#define CLK_MOUT_HSI1_MMC_CARD_USER 1
233
+
#define CLK_MOUT_HSI1_NOC_USER 2
234
+
#define CLK_MOUT_HSI1_USBDRD_USER 3
235
+
#define CLK_MOUT_HSI1_USBDRD 4
191
236
192
237
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */