Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-fixes-v5.2-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
- three fixes for Intel VT-d to fix a potential dead-lock, a formatting
fix and a bit setting fix
- one fix for the ARM-SMMU to make it work on some platforms with
sub-optimal SMMU emulation
* tag 'iommu-fixes-v5.2-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/arm-smmu: Avoid constant zero in TLBI writes
iommu/vt-d: Set the right field for Page Walk Snoop
iommu/vt-d: Fix lock inversion between iommu->lock and device_domain_lock
iommu: Add missing new line for dma type
+18
-8
+12
-3
drivers/iommu/arm-smmu.c
+12
-3
drivers/iommu/arm-smmu.c
···
47
47
48
48
#include "arm-smmu-regs.h"
49
49
50
+
/*
51
+
* Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
52
+
* global register space are still, in fact, using a hypervisor to mediate it
53
+
* by trapping and emulating register accesses. Sadly, some deployed versions
54
+
* of said trapping code have bugs wherein they go horribly wrong for stores
55
+
* using r31 (i.e. XZR/WZR) as the source register.
56
+
*/
57
+
#define QCOM_DUMMY_VAL -1
58
+
50
59
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
51
60
52
61
#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
···
420
411
{
421
412
unsigned int spin_cnt, delay;
422
413
423
-
writel_relaxed(0, sync);
414
+
writel_relaxed(QCOM_DUMMY_VAL, sync);
424
415
for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
425
416
for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
426
417
if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE))
···
1760
1751
}
1761
1752
1762
1753
/* Invalidate the TLB, just in case */
1763
-
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1764
-
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1754
+
writel_relaxed(QCOM_DUMMY_VAL, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1755
+
writel_relaxed(QCOM_DUMMY_VAL, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1765
1756
1766
1757
reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1767
1758
+4
-3
drivers/iommu/intel-iommu.c
+4
-3
drivers/iommu/intel-iommu.c
···
2504
2504
}
2505
2505
}
2506
2506
2507
+
spin_lock(&iommu->lock);
2507
2508
spin_lock_irqsave(&device_domain_lock, flags);
2508
2509
if (dev)
2509
2510
found = find_domain(dev);
···
2520
2519
2521
2520
if (found) {
2522
2521
spin_unlock_irqrestore(&device_domain_lock, flags);
2522
+
spin_unlock(&iommu->lock);
2523
2523
free_devinfo_mem(info);
2524
2524
/* Caller must free the original domain */
2525
2525
return found;
2526
2526
}
2527
2527
2528
-
spin_lock(&iommu->lock);
2529
2528
ret = domain_attach_iommu(domain, iommu);
2530
-
spin_unlock(&iommu->lock);
2531
-
2532
2529
if (ret) {
2533
2530
spin_unlock_irqrestore(&device_domain_lock, flags);
2531
+
spin_unlock(&iommu->lock);
2534
2532
free_devinfo_mem(info);
2535
2533
return NULL;
2536
2534
}
···
2539
2539
if (dev)
2540
2540
dev->archdata.iommu = info;
2541
2541
spin_unlock_irqrestore(&device_domain_lock, flags);
2542
+
spin_unlock(&iommu->lock);
2542
2543
2543
2544
/* PASID table is mandatory for a PCI device in scalable mode. */
2544
2545
if (dev && dev_is_pci(dev) && sm_supported(iommu)) {
+1
-1
drivers/iommu/intel-pasid.c
+1
-1
drivers/iommu/intel-pasid.c