Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Update dml ssb from pmfw clock table
[why]
Need to use real clock table
[How]
Update the clock table
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Muhammad Ahmed
and committed by
Alex Deucher
c7c19779
72f7d6d3
+2
-26
+2
-2
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
···
698
698
.underflow_assert_delay_us = 0xFFFFFFFF,
699
699
.dwb_fi_phase = -1, // -1 = disable,
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700
.dmub_command_table = true,
701
-
.pstate_enabled = false,
701
+
.pstate_enabled = true,
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.use_max_lb = true,
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703
.enable_mem_low_power = {
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704
.bits = {
···
1840
1840
1841
1841
/* Use pipe context based otg sync logic */
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dc->config.use_pipe_ctx_sync_logic = true;
1843
-
dc->config.use_default_clock_table = true;
1843
+
dc->config.use_default_clock_table = false;
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/* read VBIOS LTTPR caps */
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1845
{
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if (ctx->dc_bios->funcs->get_lttpr_caps) {
-22
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
-22
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
···
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//TODO
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}
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-
void dcn35_patch_dpm_table(struct clk_bw_params *bw_params)
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-
{
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-
int i;
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-
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
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-
max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
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208
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-
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
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-
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
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-
max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
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-
if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
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-
max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
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-
if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
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-
max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
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-
if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
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-
max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
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-
if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
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-
max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
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-
if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
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-
max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
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-
if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
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-
max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
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-
}
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-
}
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/*
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* dcn35_update_bw_bounding_box
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*
-2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
-2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
···
34
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void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
35
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struct clk_bw_params *bw_params);
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-
void dcn35_patch_dpm_table(struct clk_bw_params *bw_params);
38
-
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int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
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struct dc_state *context,
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display_e2e_pipe_params_st *pipes,