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mips: dts: Add PCIe to EcoNet EN751221

Add PCIe based on EN7528 PCIe driver, also add two MT76 wifi devices
to SmartFiber XP8421-B.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Caleb James DeLisle and committed by
Thomas Bogendoerfer
c7dd395d ff8efe28

+137
+114
arch/mips/boot/dts/econet/en751221.dtsi
··· 1 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 /dts-v1/; 3 3 4 + #include <dt-bindings/clock/econet,en751221-scu.h> 5 + 4 6 / { 5 7 compatible = "econet,en751221"; 6 8 #address-cells = <1>; ··· 32 30 #interrupt-cells = <1>; 33 31 }; 34 32 33 + chip_scu: syscon@1fa20000 { 34 + compatible = "econet,en751221-chip-scu", "syscon"; 35 + reg = <0x1fa20000 0x388>; 36 + }; 37 + 38 + pcie_phy1: pcie-phy@1fac0000 { 39 + compatible = "econet,en751221-pcie-gen2"; 40 + reg = <0x1fac0000 0x1000>; 41 + #phy-cells = <0>; 42 + }; 43 + 44 + pcie_phy0: pcie-phy@1faf2000 { 45 + compatible = "econet,en751221-pcie-gen1"; 46 + reg = <0x1faf2000 0x1000>; 47 + #phy-cells = <0>; 48 + }; 49 + 50 + scuclk: clock-controller@1fb00000 { 51 + compatible = "econet,en751221-scu"; 52 + reg = <0x1fb00000 0x970>; 53 + #clock-cells = <1>; 54 + #reset-cells = <1>; 55 + }; 56 + 35 57 intc: interrupt-controller@1fb40000 { 36 58 compatible = "econet,en751221-intc"; 37 59 reg = <0x1fb40000 0x100>; ··· 65 39 interrupt-controller; 66 40 #interrupt-cells = <1>; 67 41 econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; 42 + }; 43 + 44 + pciecfg: pciecfg@1fb80000 { 45 + compatible = "mediatek,generic-pciecfg", "syscon"; 46 + reg = <0x1fb80000 0x1000>; 47 + }; 48 + 49 + pcie0: pcie@1fb81000 { 50 + compatible = "econet,en7528-pcie"; 51 + device_type = "pci"; 52 + reg = <0x1fb81000 0x1000>; 53 + reg-names = "port0"; 54 + linux,pci-domain = <0>; 55 + #address-cells = <3>; 56 + #size-cells = <2>; 57 + interrupt-parent = <&intc>; 58 + interrupts = <23>; 59 + interrupt-names = "pcie_irq"; 60 + clocks = <&scuclk EN751221_CLK_PCIE>; 61 + clock-names = "sys_ck0"; 62 + phys = <&pcie_phy0>; 63 + phy-names = "pcie-phy0"; 64 + bus-range = <0x00 0xff>; 65 + ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>, 66 + <0x82000000 0 0x20000000 0x20000000 0 0x08000000>; 67 + status = "disabled"; 68 + 69 + #interrupt-cells = <1>; 70 + interrupt-map-mask = <0 0 0 7>; 71 + interrupt-map = <0 0 0 1 &pcie_intc0 0>, 72 + <0 0 0 2 &pcie_intc0 1>, 73 + <0 0 0 3 &pcie_intc0 2>, 74 + <0 0 0 4 &pcie_intc0 3>; 75 + 76 + pcie_intc0: interrupt-controller { 77 + interrupt-controller; 78 + #address-cells = <0>; 79 + #interrupt-cells = <1>; 80 + }; 81 + 82 + slot0: pcie@0,0 { 83 + reg = <0x0000 0 0 0 0>; 84 + device_type = "pci"; 85 + #address-cells = <3>; 86 + #size-cells = <2>; 87 + ranges; 88 + }; 89 + }; 90 + 91 + pcie1: pcie@1fb83000 { 92 + compatible = "econet,en7528-pcie"; 93 + device_type = "pci"; 94 + reg = <0x1fb83000 0x1000>; 95 + reg-names = "port1"; 96 + linux,pci-domain = <1>; 97 + #address-cells = <3>; 98 + #size-cells = <2>; 99 + interrupt-parent = <&intc>; 100 + interrupts = <24>; 101 + interrupt-names = "pcie_irq"; 102 + clocks = <&scuclk EN751221_CLK_PCIE>; 103 + clock-names = "sys_ck1"; 104 + phys = <&pcie_phy1>; 105 + phy-names = "pcie-phy1"; 106 + bus-range = <0x00 0xff>; 107 + ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>, 108 + <0x82000000 0 0x28000000 0x28000000 0 0x08000000>; 109 + status = "disabled"; 110 + 111 + #interrupt-cells = <1>; 112 + interrupt-map-mask = <0 0 0 7>; 113 + interrupt-map = <0 0 0 1 &pcie_intc1 0>, 114 + <0 0 0 2 &pcie_intc1 1>, 115 + <0 0 0 3 &pcie_intc1 2>, 116 + <0 0 0 4 &pcie_intc1 3>; 117 + 118 + pcie_intc1: interrupt-controller { 119 + interrupt-controller; 120 + #address-cells = <0>; 121 + #interrupt-cells = <1>; 122 + }; 123 + 124 + slot1: pcie@1,0 { 125 + reg = <0x0800 0 0 0 0>; 126 + #address-cells = <3>; 127 + #size-cells = <2>; 128 + ranges; 129 + }; 68 130 }; 69 131 70 132 uart: serial@1fbf0000 {
+21
arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
··· 17 17 linux,usable-memory-range = <0x00020000 0x1bfe0000>; 18 18 }; 19 19 }; 20 + 21 + &pcie0 { 22 + status = "okay"; 23 + }; 24 + &slot0 { 25 + wifi@0,0 { 26 + /* MT7612E */ 27 + compatible = "mediatek,mt76"; 28 + reg = <0x0000 0 0 0 0>; 29 + }; 30 + }; 31 + &pcie1 { 32 + status = "okay"; 33 + }; 34 + &slot1 { 35 + wifi@0,0 { 36 + /* MT7592 */ 37 + compatible = "mediatek,mt76"; 38 + reg = <0x0000 0 0 0 0>; 39 + }; 40 + };
+2
arch/mips/econet/Kconfig
··· 13 13 bool "EN751221 family" 14 14 select COMMON_CLK 15 15 select ECONET_EN751221_INTC 16 + select HAVE_PCI 16 17 select IRQ_MIPS_CPU 18 + select PCI_DRIVERS_GENERIC 17 19 select SMP 18 20 select SMP_UP 19 21 select SYS_SUPPORTS_SMP