tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
sh: intc: Initialize radix tree gfp mask explicitly.
sh: Fix up SH7201 clkfwk build.
sh: mach-se: Fix up SE7206 build.
sh: Fix up SH4-202 clkfwk build.

Linus Torvalds c816d7c6 b094a870

+4 -4
+1 -1
arch/sh/boards/mach-se/7206/irq.c
··· 140 140 make_se7206_irq(IRQ1_IRQ); /* ATA */ 141 141 make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */ 142 142 143 - __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR); /* ICR1 */ 143 + __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */ 144 144 145 145 /* FPGA System register setup*/ 146 146 __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
+1 -1
arch/sh/kernel/cpu/sh2a/clock-sh7201.c
··· 34 34 35 35 static void master_clk_init(struct clk *clk) 36 36 { 37 - return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 37 + clk->rate = 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 38 38 } 39 39 40 40 static struct clk_ops sh7201_master_clk_ops = {
+1 -2
arch/sh/kernel/cpu/sh4/clock-sh4-202.c
··· 81 81 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) { 82 82 int divisor = frqcr3_divisors[i]; 83 83 84 - if (clk->ops->set_rate(clk, clk->parent->rate / 85 - divisor, 0) == 0) 84 + if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) 86 85 break; 87 86 } 88 87
+1
drivers/sh/intc/core.c
··· 198 198 list_add_tail(&d->list, &intc_list); 199 199 200 200 raw_spin_lock_init(&d->lock); 201 + INIT_RADIX_TREE(&d->tree, GFP_ATOMIC); 201 202 202 203 d->index = nr_intc_controllers; 203 204