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drm/amd/display: Clean up errors & warnings in amdgpu_dm.c

Fix the following errors & warnings reported by checkpatch:

ERROR: space required before the open brace '{'
ERROR: space required before the open parenthesis '('
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: else should follow close brace '}'
ERROR: open brace '{' following function definitions go on the next line
ERROR: code indent should use tabs where possible

WARNING: braces {} are not necessary for single statement blocks
WARNING: void function return statements are not generally useful
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line

Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Srinivasan Shanmugam and committed by
Alex Deucher c82eddf8 fe9aaddf

+65 -68
+65 -68
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 424 424 425 425 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 426 426 427 - if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 428 - DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 429 - amdgpu_crtc->pflip_status, 430 - AMDGPU_FLIP_SUBMITTED, 431 - amdgpu_crtc->crtc_id, 432 - amdgpu_crtc); 427 + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 428 + DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 429 + amdgpu_crtc->pflip_status, 430 + AMDGPU_FLIP_SUBMITTED, 431 + amdgpu_crtc->crtc_id, 432 + amdgpu_crtc); 433 433 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 434 434 return; 435 435 } ··· 883 883 } 884 884 885 885 /* Prototypes of private functions */ 886 - static int dm_early_init(void* handle); 886 + static int dm_early_init(void *handle); 887 887 888 888 /* Allocate memory for FBC compressed data */ 889 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector) ··· 1282 1282 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1283 1283 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1284 1284 1285 - pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1285 + pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1286 1286 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1287 1287 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1288 1288 ··· 1365 1365 DP_TEST_RESPONSE, 1366 1366 &test_response.raw, 1367 1367 sizeof(test_response)); 1368 - } 1369 - else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1368 + } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1370 1369 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1371 1370 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1372 1371 /* offload_work->data is from handle_hpd_rx_irq-> ··· 1553 1554 mutex_init(&adev->dm.dc_lock); 1554 1555 mutex_init(&adev->dm.audio_lock); 1555 1556 1556 - if(amdgpu_dm_irq_init(adev)) { 1557 + if (amdgpu_dm_irq_init(adev)) { 1557 1558 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1558 1559 goto error; 1559 1560 } ··· 1695 1696 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1696 1697 adev->dm.dc->debug.disable_stutter = true; 1697 1698 1698 - if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 1699 + if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1699 1700 adev->dm.dc->debug.disable_dsc = true; 1700 - } 1701 1701 1702 1702 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1703 1703 adev->dm.dc->debug.disable_clock_gate = true; ··· 1940 1942 mutex_destroy(&adev->dm.audio_lock); 1941 1943 mutex_destroy(&adev->dm.dc_lock); 1942 1944 mutex_destroy(&adev->dm.dpia_aux_lock); 1943 - 1944 - return; 1945 1945 } 1946 1946 1947 1947 static int load_dmcu_fw(struct amdgpu_device *adev) ··· 1948 1952 int r; 1949 1953 const struct dmcu_firmware_header_v1_0 *hdr; 1950 1954 1951 - switch(adev->asic_type) { 1955 + switch (adev->asic_type) { 1952 1956 #if defined(CONFIG_DRM_AMD_DC_SI) 1953 1957 case CHIP_TAHITI: 1954 1958 case CHIP_PITCAIRN: ··· 2705 2709 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2706 2710 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2707 2711 struct dc_stream_update stream_update; 2708 - } * bundle; 2712 + } *bundle; 2709 2713 int k, m; 2710 2714 2711 2715 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); ··· 2735 2739 2736 2740 cleanup: 2737 2741 kfree(bundle); 2738 - 2739 - return; 2740 2742 } 2741 2743 2742 2744 static int dm_resume(void *handle) ··· 2948 2954 .set_powergating_state = dm_set_powergating_state, 2949 2955 }; 2950 2956 2951 - const struct amdgpu_ip_block_version dm_ip_block = 2952 - { 2957 + const struct amdgpu_ip_block_version dm_ip_block = { 2953 2958 .type = AMD_IP_BLOCK_TYPE_DCE, 2954 2959 .major = 1, 2955 2960 .minor = 0, ··· 2993 3000 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 2994 3001 caps->aux_support = false; 2995 3002 2996 - if (caps->ext_caps->bits.oled == 1 /*|| 2997 - caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 2998 - caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 3003 + if (caps->ext_caps->bits.oled == 1 3004 + /* 3005 + * || 3006 + * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3007 + * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3008 + */) 2999 3009 caps->aux_support = true; 3000 3010 3001 3011 if (amdgpu_backlight == 0) ··· 3265 3269 process_count < max_process_count) { 3266 3270 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 3267 3271 u8 retry; 3272 + 3268 3273 dret = 0; 3269 3274 3270 3275 process_count++; ··· 3465 3468 aconnector = to_amdgpu_dm_connector(connector); 3466 3469 dc_link = aconnector->dc_link; 3467 3470 3468 - if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 3471 + if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3469 3472 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3470 3473 int_params.irq_source = dc_link->irq_source_hpd; 3471 3474 ··· 3474 3477 (void *) aconnector); 3475 3478 } 3476 3479 3477 - if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 3480 + if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3478 3481 3479 3482 /* Also register for DP short pulse (hpd_rx). */ 3480 3483 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; ··· 3500 3503 struct dc_interrupt_params int_params = {0}; 3501 3504 int r; 3502 3505 int i; 3503 - unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3506 + unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3504 3507 3505 3508 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3506 3509 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; ··· 3514 3517 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3515 3518 * coming from DC hardware. 3516 3519 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3517 - * for acknowledging and handling. */ 3520 + * for acknowledging and handling. 3521 + */ 3518 3522 3519 3523 /* Use VBLANK interrupt */ 3520 3524 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3521 - r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 3525 + r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3522 3526 if (r) { 3523 3527 DRM_ERROR("Failed to add crtc irq id!\n"); 3524 3528 return r; ··· 3527 3529 3528 3530 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3529 3531 int_params.irq_source = 3530 - dc_interrupt_to_irq_source(dc, i+1 , 0); 3532 + dc_interrupt_to_irq_source(dc, i + 1, 0); 3531 3533 3532 3534 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3533 3535 ··· 3583 3585 struct dc_interrupt_params int_params = {0}; 3584 3586 int r; 3585 3587 int i; 3586 - unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3588 + unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3587 3589 3588 3590 if (adev->family >= AMDGPU_FAMILY_AI) 3589 3591 client_id = SOC15_IH_CLIENTID_DCE; ··· 3600 3602 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3601 3603 * coming from DC hardware. 3602 3604 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3603 - * for acknowledging and handling. */ 3605 + * for acknowledging and handling. 3606 + */ 3604 3607 3605 3608 /* Use VBLANK interrupt */ 3606 3609 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { ··· 4048 4049 } 4049 4050 4050 4051 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4051 - unsigned *min, unsigned *max) 4052 + unsigned int *min, unsigned int *max) 4052 4053 { 4053 4054 if (!caps) 4054 4055 return 0; ··· 4068 4069 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4069 4070 uint32_t brightness) 4070 4071 { 4071 - unsigned min, max; 4072 + unsigned int min, max; 4072 4073 4073 4074 if (!get_brightness_range(caps, &min, &max)) 4074 4075 return brightness; ··· 4081 4082 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4082 4083 uint32_t brightness) 4083 4084 { 4084 - unsigned min, max; 4085 + unsigned int min, max; 4085 4086 4086 4087 if (!get_brightness_range(caps, &min, &max)) 4087 4088 return brightness; ··· 4561 4562 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4562 4563 { 4563 4564 drm_atomic_private_obj_fini(&dm->atomic_obj); 4564 - return; 4565 4565 } 4566 4566 4567 4567 /****************************************************************************** ··· 5392 5394 { 5393 5395 enum dc_color_depth depth = timing_out->display_color_depth; 5394 5396 int normalized_clk; 5397 + 5395 5398 do { 5396 5399 normalized_clk = timing_out->pix_clk_100hz / 10; 5397 5400 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ ··· 5608 5609 { 5609 5610 struct dc_sink_init_data sink_init_data = { 0 }; 5610 5611 struct dc_sink *sink = NULL; 5612 + 5611 5613 sink_init_data.link = aconnector->dc_link; 5612 5614 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5613 5615 ··· 5732 5732 return &aconnector->freesync_vid_base; 5733 5733 5734 5734 /* Find the preferred mode */ 5735 - list_for_each_entry (m, list_head, head) { 5735 + list_for_each_entry(m, list_head, head) { 5736 5736 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5737 5737 m_pref = m; 5738 5738 break; ··· 5756 5756 * For some monitors, preferred mode is not the mode with highest 5757 5757 * supported refresh rate. 5758 5758 */ 5759 - list_for_each_entry (m, list_head, head) { 5759 + list_for_each_entry(m, list_head, head) { 5760 5760 current_refresh = drm_mode_vrefresh(m); 5761 5761 5762 5762 if (m->hdisplay == m_pref->hdisplay && ··· 6028 6028 * This may not be an error, the use case is when we have no 6029 6029 * usermode calls to reset and set mode upon hotplug. In this 6030 6030 * case, we call set mode ourselves to restore the previous mode 6031 - * and the modelist may not be filled in in time. 6031 + * and the modelist may not be filled in time. 6032 6032 */ 6033 6033 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6034 6034 } else { ··· 6051 6051 drm_mode_set_crtcinfo(&mode, 0); 6052 6052 6053 6053 /* 6054 - * If scaling is enabled and refresh rate didn't change 6055 - * we copy the vic and polarities of the old timings 6056 - */ 6054 + * If scaling is enabled and refresh rate didn't change 6055 + * we copy the vic and polarities of the old timings 6056 + */ 6057 6057 if (!scale || mode_refresh != preferred_refresh) 6058 6058 fill_stream_properties_from_drm_display_mode( 6059 6059 stream, &mode, &aconnector->base, con_state, NULL, ··· 6817 6817 6818 6818 if (!state->duplicated) { 6819 6819 int max_bpc = conn_state->max_requested_bpc; 6820 + 6820 6821 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6821 6822 aconnector->force_yuv420_output; 6822 6823 color_depth = convert_color_depth_from_display_info(connector, ··· 7136 7135 { 7137 7136 struct drm_display_mode *m; 7138 7137 7139 - list_for_each_entry (m, &aconnector->base.probed_modes, head) { 7138 + list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7140 7139 if (drm_mode_equal(m, mode)) 7141 7140 return true; 7142 7141 } ··· 7455 7454 7456 7455 link->priv = aconnector; 7457 7456 7458 - DRM_DEBUG_DRIVER("%s()\n", __func__); 7459 7457 7460 7458 i2c = create_i2c(link->ddc, link->link_index, &res); 7461 7459 if (!i2c) { ··· 8168 8168 * DRI3/Present extension with defined target_msc. 8169 8169 */ 8170 8170 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8171 - } 8172 - else { 8171 + } else { 8173 8172 /* For variable refresh rate mode only: 8174 8173 * Get vblank of last completed flip to avoid > 1 vrr 8175 8174 * flips per video frame by use of throttling, but allow ··· 8501 8502 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8502 8503 } 8503 8504 8504 - for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8505 - new_crtc_state, i) { 8505 + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8506 + new_crtc_state, i) { 8506 8507 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8507 8508 8508 8509 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); ··· 8525 8526 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8526 8527 8527 8528 drm_dbg_state(state->dev, 8528 - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8529 - "planes_changed:%d, mode_changed:%d,active_changed:%d," 8530 - "connectors_changed:%d\n", 8529 + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 8531 8530 acrtc->crtc_id, 8532 8531 new_crtc_state->enable, 8533 8532 new_crtc_state->active, ··· 9101 9104 &commit->flip_done, 10*HZ); 9102 9105 9103 9106 if (ret == 0) 9104 - DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 9105 - "timed out\n", crtc->base.id, crtc->name); 9107 + DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9108 + crtc->base.id, crtc->name); 9106 9109 9107 9110 drm_crtc_commit_put(commit); 9108 9111 } ··· 9187 9190 return false; 9188 9191 } 9189 9192 9190 - static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 9193 + static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9194 + { 9191 9195 u64 num, den, res; 9192 9196 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9193 9197 ··· 9310 9312 goto skip_modeset; 9311 9313 9312 9314 drm_dbg_state(state->dev, 9313 - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 9314 - "planes_changed:%d, mode_changed:%d,active_changed:%d," 9315 - "connectors_changed:%d\n", 9315 + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9316 9316 acrtc->crtc_id, 9317 9317 new_crtc_state->enable, 9318 9318 new_crtc_state->active, ··· 9339 9343 old_crtc_state)) { 9340 9344 new_crtc_state->mode_changed = false; 9341 9345 DRM_DEBUG_DRIVER( 9342 - "Mode change not required for front porch change, " 9343 - "setting mode_changed to %d", 9346 + "Mode change not required for front porch change, setting mode_changed to %d", 9344 9347 new_crtc_state->mode_changed); 9345 9348 9346 9349 set_freesync_fixed_config(dm_new_crtc_state); ··· 9351 9356 struct drm_display_mode *high_mode; 9352 9357 9353 9358 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9354 - if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 9359 + if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 9355 9360 set_freesync_fixed_config(dm_new_crtc_state); 9356 - } 9357 9361 } 9358 9362 9359 9363 ret = dm_atomic_get_state(state, &dm_state); ··· 9520 9526 */ 9521 9527 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9522 9528 struct amdgpu_framebuffer *old_afb, *new_afb; 9529 + 9523 9530 if (other->type == DRM_PLANE_TYPE_CURSOR) 9524 9531 continue; 9525 9532 ··· 9619 9624 } 9620 9625 9621 9626 /* Core DRM takes care of checking FB modifiers, so we only need to 9622 - * check tiling flags when the FB doesn't have a modifier. */ 9627 + * check tiling flags when the FB doesn't have a modifier. 9628 + */ 9623 9629 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9624 9630 if (adev->family < AMDGPU_FAMILY_AI) { 9625 9631 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9626 - AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9632 + AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9627 9633 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9628 9634 } else { 9629 9635 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; ··· 9846 9850 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9847 9851 * cursor per pipe but it's going to inherit the scaling and 9848 9852 * positioning from the underlying pipe. Check the cursor plane's 9849 - * blending properties match the underlying planes'. */ 9853 + * blending properties match the underlying planes'. 9854 + */ 9850 9855 9851 9856 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); 9852 - if (!new_cursor_state || !new_cursor_state->fb) { 9857 + if (!new_cursor_state || !new_cursor_state->fb) 9853 9858 return 0; 9854 - } 9855 9859 9856 9860 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); 9857 9861 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; ··· 9896 9900 struct drm_connector_state *conn_state, *old_conn_state; 9897 9901 struct amdgpu_dm_connector *aconnector = NULL; 9898 9902 int i; 9903 + 9899 9904 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 9900 9905 if (!conn_state->crtc) 9901 9906 conn_state = old_conn_state; ··· 10331 10334 } 10332 10335 10333 10336 /* Store the overall update type for use later in atomic check. */ 10334 - for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 10337 + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10335 10338 struct dm_crtc_state *dm_new_crtc_state = 10336 10339 to_dm_crtc_state(new_crtc_state); 10337 10340 ··· 10353 10356 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10354 10357 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10355 10358 else 10356 - DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 10359 + DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 10357 10360 10358 10361 trace_amdgpu_dm_atomic_check_finish(state, ret); 10359 10362