Merge tag 'powerpc-5.7-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

+1 -1

arch/powerpc/Kconfig

··· 130 130 select ARCH_HAS_PTE_SPECIAL 131 131 select ARCH_HAS_MEMBARRIER_CALLBACKS 132 132 select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64 133 - select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION) 133 + select ARCH_HAS_STRICT_KERNEL_RWX if (PPC32 && !HIBERNATION) 134 134 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 135 135 select ARCH_HAS_UACCESS_FLUSHCACHE 136 136 select ARCH_HAS_UACCESS_MCSAFE if PPC64

+4 -4

arch/powerpc/include/asm/book3s/32/hash.h

··· 17 17 * updating the accessed and modified bits in the page table tree. 18 18 */ 19 19 20 - #define _PAGE_USER 0x001 /* usermode access allowed */ 21 - #define _PAGE_RW 0x002 /* software: user write access allowed */ 22 - #define _PAGE_PRESENT 0x004 /* software: pte contains a translation */ 20 + #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ 21 + #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ 22 + #define _PAGE_USER 0x004 /* usermode access allowed */ 23 23 #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ 24 24 #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ 25 25 #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ ··· 27 27 #define _PAGE_DIRTY 0x080 /* C: page changed */ 28 28 #define _PAGE_ACCESSED 0x100 /* R: page referenced */ 29 29 #define _PAGE_EXEC 0x200 /* software: exec allowed */ 30 - #define _PAGE_HASHPTE 0x400 /* hash_page has made an HPTE for this pte */ 30 + #define _PAGE_RW 0x400 /* software: user write access allowed */ 31 31 #define _PAGE_SPECIAL 0x800 /* software: Special page */ 32 32 33 33 #ifdef CONFIG_PTE_64BIT

+6 -3

arch/powerpc/kernel/head_32.S

··· 348 348 andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h 349 349 #endif 350 350 bne handle_page_fault_tramp_2 /* if not, try to put a PTE */ 351 - rlwinm r3, r5, 32 - 24, 30, 30 /* DSISR_STORE -> _PAGE_RW */ 351 + rlwinm r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */ 352 352 bl hash_page 353 353 b handle_page_fault_tramp_1 354 354 FTR_SECTION_ELSE ··· 497 497 andc. r1,r1,r0 /* check access & ~permission */ 498 498 bne- InstructionAddressInvalid /* return if access not permitted */ 499 499 /* Convert linux-style PTE to low word of PPC-style PTE */ 500 + rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */ 500 501 ori r1, r1, 0xe06 /* clear out reserved bits */ 501 502 andc r1, r0, r1 /* PP = user? 1 : 0 */ 502 503 BEGIN_FTR_SECTION ··· 565 564 * we would need to update the pte atomically with lwarx/stwcx. 566 565 */ 567 566 /* Convert linux-style PTE to low word of PPC-style PTE */ 568 - rlwinm r1,r0,0,30,30 /* _PAGE_RW -> PP msb */ 569 - rlwimi r0,r0,1,30,30 /* _PAGE_USER -> PP msb */ 567 + rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */ 568 + rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ 569 + rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */ 570 570 ori r1,r1,0xe04 /* clear out reserved bits */ 571 571 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */ 572 572 BEGIN_FTR_SECTION ··· 645 643 * we would need to update the pte atomically with lwarx/stwcx. 646 644 */ 647 645 /* Convert linux-style PTE to low word of PPC-style PTE */ 646 + rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */ 648 647 li r1,0xe06 /* clear out reserved bits & PP msb */ 649 648 andc r1,r0,r1 /* PP = user? 1: 0 */ 650 649 BEGIN_FTR_SECTION

+8 -6

arch/powerpc/mm/book3s32/hash_low.S

··· 35 35 /* 36 36 * Load a PTE into the hash table, if possible. 37 37 * The address is in r4, and r3 contains an access flag: 38 - * _PAGE_RW (0x002) if a write. 38 + * _PAGE_RW (0x400) if a write. 39 39 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 40 40 * SPRG_THREAD contains the physical address of the current task's thread. 41 41 * ··· 69 69 blt+ 112f /* assume user more likely */ 70 70 lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ 71 71 addi r5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */ 72 - rlwimi r3,r9,32-14,31,31 /* MSR_PR -> _PAGE_USER */ 72 + rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 73 73 112: 74 74 #ifndef CONFIG_PTE_64BIT 75 75 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ ··· 94 94 #else 95 95 rlwimi r8,r4,23,20,28 /* compute pte address */ 96 96 #endif 97 - rlwinm r0,r3,6,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 97 + rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 98 98 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 99 99 100 100 /* ··· 310 310 311 311 _GLOBAL(create_hpte) 312 312 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 313 + rlwinm r8,r5,32-9,30,30 /* _PAGE_RW -> PP msb */ 313 314 rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */ 314 - and r8,r5,r0 /* writable if _RW & _DIRTY */ 315 - rlwimi r5,r5,1,30,30 /* _PAGE_USER -> PP msb */ 315 + and r8,r8,r0 /* writable if _RW & _DIRTY */ 316 + rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 317 + rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 316 318 ori r8,r8,0xe04 /* clear out reserved bits */ 317 319 andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */ 318 320 BEGIN_FTR_SECTION ··· 566 564 33: lwarx r8,0,r5 /* fetch the pte flags word */ 567 565 andi. r0,r8,_PAGE_HASHPTE 568 566 beq 8f /* done if HASHPTE is already clear */ 569 - rlwinm r8,r8,0,~_PAGE_HASHPTE /* clear HASHPTE bit */ 567 + rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 570 568 stwcx. r8,0,r5 /* update the pte */ 571 569 bne- 33b 572 570

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