Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Fix EV64120 and Ocelot builds by providing a plat_timer_setup().
[MIPS] EV64120: Fix PCI interrupt allocation.
[MIPS] Make irq number allocator generally available for fixing EV64120.
[MIPS] EV64120: Fix timer initialization for HZ != 100.
[MIPS] Ocelot 3: Fix MAC address detection after platform_device conversion.
[MIPS] Ocelot C: Fix MAC address detection after platform_device conversion.
[MIPS] SB1: On bootup only flush cache on local CPU.
[MIPS] Ocelot 3: Fix large number of warnings.
[MIPS] Ocelot C: Fix mapping of ioport address range.
[MIPS] Ocelot C: Fix warning about missmatching format string.
[MIPS] Ocelot C: fix eth registration after conversion to platform_device
[MIPS] Ocelot C: Fix large number of warnings.
+528
-206
+2
-2
arch/mips/gt64120/common/time.c
+2
-2
arch/mips/gt64120/common/time.c
···
64
64
* as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
65
65
* handling.
66
66
*/
67
-
void gt64120_time_init(void)
67
+
void __init plat_timer_setup(struct irqaction *irq)
68
68
{
69
69
static struct irqaction timer;
70
70
71
71
/* Disable timer first */
72
72
GT_WRITE(GT_TC_CONTROL_OFS, 0);
73
73
/* Load timer value for 100 Hz */
74
-
GT_WRITE(GT_TC3_OFS, Sys_clock / 100);
74
+
GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);
75
75
76
76
/*
77
77
* Create the IRQ structure entry for the timer. Since we're too early
-2
arch/mips/gt64120/ev64120/setup.c
-2
arch/mips/gt64120/ev64120/setup.c
···
68
68
* Initializes basic routines and structures pointers, memory size (as
69
69
* given by the bios and saves the command line.
70
70
*/
71
-
extern void gt64120_time_init(void);
72
71
73
72
void __init plat_mem_setup(void)
74
73
{
···
75
76
_machine_halt = galileo_machine_halt;
76
77
pm_power_off = galileo_machine_power_off;
77
78
78
-
board_time_init = gt64120_time_init;
79
79
set_io_port_base(KSEG1);
80
80
}
81
81
-3
arch/mips/gt64120/momenco_ocelot/setup.c
-3
arch/mips/gt64120/momenco_ocelot/setup.c
···
70
70
extern void momenco_ocelot_halt(void);
71
71
extern void momenco_ocelot_power_off(void);
72
72
73
-
extern void gt64120_time_init(void);
74
73
extern void momenco_ocelot_irq_setup(void);
75
74
76
75
static char reset_reason;
···
154
155
{
155
156
void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
156
157
unsigned int tmpword;
157
-
158
-
board_time_init = gt64120_time_init;
159
158
160
159
_machine_restart = momenco_ocelot_restart;
161
160
_machine_halt = momenco_ocelot_halt;
+42
arch/mips/kernel/irq.c
+42
arch/mips/kernel/irq.c
···
26
26
#include <asm/system.h>
27
27
#include <asm/uaccess.h>
28
28
29
+
static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
30
+
31
+
int __devinit allocate_irqno(void)
32
+
{
33
+
int irq;
34
+
35
+
again:
36
+
irq = find_first_zero_bit(irq_map, NR_IRQS);
37
+
38
+
if (irq >= NR_IRQS)
39
+
return -ENOSPC;
40
+
41
+
if (test_and_set_bit(irq, irq_map))
42
+
goto again;
43
+
44
+
return irq;
45
+
}
46
+
47
+
EXPORT_SYMBOL_GPL(allocate_irqno);
48
+
49
+
/*
50
+
* Allocate the 16 legacy interrupts for i8259 devices. This happens early
51
+
* in the kernel initialization so treating allocation failure as BUG() is
52
+
* ok.
53
+
*/
54
+
void __init alloc_legacy_irqno(void)
55
+
{
56
+
int i;
57
+
58
+
for (i = 0; i <= 16; i++)
59
+
BUG_ON(test_and_set_bit(i, irq_map));
60
+
}
61
+
62
+
void __devinit free_irqno(unsigned int irq)
63
+
{
64
+
smp_mb__before_clear_bit();
65
+
clear_bit(irq, irq_map);
66
+
smp_mb__after_clear_bit();
67
+
}
68
+
69
+
EXPORT_SYMBOL_GPL(free_irqno);
70
+
29
71
/*
30
72
* 'what should we do if we get a hw irq event on an illegal vector'.
31
73
* each architecture has to answer this themselves.
+1
-1
arch/mips/mm/c-sb1.c
+1
-1
arch/mips/mm/c-sb1.c
+1
-1
arch/mips/momentum/ocelot_3/Makefile
+1
-1
arch/mips/momentum/ocelot_3/Makefile
+4
-2
arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
+4
-2
arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
···
51
51
52
52
extern unsigned long ocelot_fpga_base;
53
53
54
-
#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y)
55
-
#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x)
54
+
#define __FPGA_REG_TO_ADDR(reg) \
55
+
((void *) ocelot_fpga_base + OCELOT_3_REG_##reg)
56
+
#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
57
+
#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
56
58
57
59
#endif
+235
arch/mips/momentum/ocelot_3/platform.c
+235
arch/mips/momentum/ocelot_3/platform.c
···
1
+
#include <linux/delay.h>
2
+
#include <linux/if_ether.h>
3
+
#include <linux/ioport.h>
4
+
#include <linux/mv643xx.h>
5
+
#include <linux/platform_device.h>
6
+
7
+
#include "ocelot_3_fpga.h"
8
+
9
+
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
+
11
+
static struct resource mv643xx_eth_shared_resources[] = {
12
+
[0] = {
13
+
.name = "ethernet shared base",
14
+
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15
+
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16
+
MV643XX_ETH_SHARED_REGS_SIZE - 1,
17
+
.flags = IORESOURCE_MEM,
18
+
},
19
+
};
20
+
21
+
static struct platform_device mv643xx_eth_shared_device = {
22
+
.name = MV643XX_ETH_SHARED_NAME,
23
+
.id = 0,
24
+
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25
+
.resource = mv643xx_eth_shared_resources,
26
+
};
27
+
28
+
#define MV_SRAM_BASE 0xfe000000UL
29
+
#define MV_SRAM_SIZE (256 * 1024)
30
+
31
+
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32
+
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
+
34
+
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35
+
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
+
37
+
#define MV64x60_IRQ_ETH_0 48
38
+
#define MV64x60_IRQ_ETH_1 49
39
+
#define MV64x60_IRQ_ETH_2 50
40
+
41
+
#ifdef CONFIG_MV643XX_ETH_0
42
+
43
+
static struct resource mv64x60_eth0_resources[] = {
44
+
[0] = {
45
+
.name = "eth0 irq",
46
+
.start = MV64x60_IRQ_ETH_0,
47
+
.end = MV64x60_IRQ_ETH_0,
48
+
.flags = IORESOURCE_IRQ,
49
+
},
50
+
};
51
+
52
+
static char eth0_mac_addr[ETH_ALEN];
53
+
54
+
static struct mv643xx_eth_platform_data eth0_pd = {
55
+
.mac_addr = eth0_mac_addr,
56
+
57
+
.tx_sram_addr = MV_SRAM_BASE_ETH0,
58
+
.tx_sram_size = MV_SRAM_TXRING_SIZE,
59
+
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
60
+
61
+
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
62
+
.rx_sram_size = MV_SRAM_RXRING_SIZE,
63
+
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
64
+
};
65
+
66
+
static struct platform_device eth0_device = {
67
+
.name = MV643XX_ETH_NAME,
68
+
.id = 0,
69
+
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
70
+
.resource = mv64x60_eth0_resources,
71
+
.dev = {
72
+
.platform_data = ð0_pd,
73
+
},
74
+
};
75
+
#endif /* CONFIG_MV643XX_ETH_0 */
76
+
77
+
#ifdef CONFIG_MV643XX_ETH_1
78
+
79
+
static struct resource mv64x60_eth1_resources[] = {
80
+
[0] = {
81
+
.name = "eth1 irq",
82
+
.start = MV64x60_IRQ_ETH_1,
83
+
.end = MV64x60_IRQ_ETH_1,
84
+
.flags = IORESOURCE_IRQ,
85
+
},
86
+
};
87
+
88
+
static char eth1_mac_addr[ETH_ALEN];
89
+
90
+
static struct mv643xx_eth_platform_data eth1_pd = {
91
+
.mac_addr = eth1_mac_addr,
92
+
93
+
.tx_sram_addr = MV_SRAM_BASE_ETH1,
94
+
.tx_sram_size = MV_SRAM_TXRING_SIZE,
95
+
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
96
+
97
+
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
98
+
.rx_sram_size = MV_SRAM_RXRING_SIZE,
99
+
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
100
+
};
101
+
102
+
static struct platform_device eth1_device = {
103
+
.name = MV643XX_ETH_NAME,
104
+
.id = 1,
105
+
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
106
+
.resource = mv64x60_eth1_resources,
107
+
.dev = {
108
+
.platform_data = ð1_pd,
109
+
},
110
+
};
111
+
#endif /* CONFIG_MV643XX_ETH_1 */
112
+
113
+
#ifdef CONFIG_MV643XX_ETH_2
114
+
115
+
static struct resource mv64x60_eth2_resources[] = {
116
+
[0] = {
117
+
.name = "eth2 irq",
118
+
.start = MV64x60_IRQ_ETH_2,
119
+
.end = MV64x60_IRQ_ETH_2,
120
+
.flags = IORESOURCE_IRQ,
121
+
},
122
+
};
123
+
124
+
static char eth2_mac_addr[ETH_ALEN];
125
+
126
+
static struct mv643xx_eth_platform_data eth2_pd = {
127
+
.mac_addr = eth2_mac_addr,
128
+
};
129
+
130
+
static struct platform_device eth2_device = {
131
+
.name = MV643XX_ETH_NAME,
132
+
.id = 1,
133
+
.num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
134
+
.resource = mv64x60_eth2_resources,
135
+
.dev = {
136
+
.platform_data = ð2_pd,
137
+
},
138
+
};
139
+
#endif /* CONFIG_MV643XX_ETH_2 */
140
+
141
+
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
142
+
&mv643xx_eth_shared_device,
143
+
#ifdef CONFIG_MV643XX_ETH_0
144
+
ð0_device,
145
+
#endif
146
+
#ifdef CONFIG_MV643XX_ETH_1
147
+
ð1_device,
148
+
#endif
149
+
#ifdef CONFIG_MV643XX_ETH_2
150
+
ð2_device,
151
+
#endif
152
+
};
153
+
154
+
static u8 __init exchange_bit(u8 val, u8 cs)
155
+
{
156
+
/* place the data */
157
+
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
158
+
udelay(1);
159
+
160
+
/* turn the clock on */
161
+
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
162
+
udelay(1);
163
+
164
+
/* turn the clock off and read-strobe */
165
+
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
166
+
167
+
/* return the data */
168
+
return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
169
+
}
170
+
171
+
static void __init get_mac(char dest[6])
172
+
{
173
+
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
174
+
int i,j;
175
+
176
+
for (i = 0; i < 12; i++)
177
+
exchange_bit(read_opcode[i], 1);
178
+
179
+
for (j = 0; j < 6; j++) {
180
+
dest[j] = 0;
181
+
for (i = 0; i < 8; i++) {
182
+
dest[j] <<= 1;
183
+
dest[j] |= exchange_bit(0, 1);
184
+
}
185
+
}
186
+
187
+
/* turn off CS */
188
+
exchange_bit(0,0);
189
+
}
190
+
191
+
/*
192
+
* Copy and increment ethernet MAC address by a small value.
193
+
*
194
+
* This is useful for systems where the only one MAC address is stored in
195
+
* non-volatile memory for multiple ports.
196
+
*/
197
+
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
198
+
unsigned int add)
199
+
{
200
+
int i;
201
+
202
+
BUG_ON(add >= 256);
203
+
204
+
for (i = ETH_ALEN; i >= 0; i--) {
205
+
dst[i] = src[i] + add;
206
+
add = dst[i] < src[i]; /* compute carry */
207
+
}
208
+
209
+
WARN_ON(add);
210
+
}
211
+
212
+
static int __init mv643xx_eth_add_pds(void)
213
+
{
214
+
unsigned char mac[ETH_ALEN];
215
+
int ret;
216
+
217
+
get_mac(mac);
218
+
#ifdef CONFIG_MV643XX_ETH_0
219
+
eth_mac_add(eth1_mac_addr, mac, 0);
220
+
#endif
221
+
#ifdef CONFIG_MV643XX_ETH_1
222
+
eth_mac_add(eth1_mac_addr, mac, 1);
223
+
#endif
224
+
#ifdef CONFIG_MV643XX_ETH_2
225
+
eth_mac_add(eth2_mac_addr, mac, 2);
226
+
#endif
227
+
ret = platform_add_devices(mv643xx_eth_pd_devs,
228
+
ARRAY_SIZE(mv643xx_eth_pd_devs));
229
+
230
+
return ret;
231
+
}
232
+
233
+
device_initcall(mv643xx_eth_add_pds);
234
+
235
+
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
-58
arch/mips/momentum/ocelot_3/prom.c
-58
arch/mips/momentum/ocelot_3/prom.c
···
34
34
extern unsigned long marvell_base;
35
35
extern unsigned long cpu_clock;
36
36
37
-
#ifdef CONFIG_MV643XX_ETH
38
-
extern unsigned char prom_mac_addr_base[6];
39
-
#endif
40
-
41
37
const char *get_system_type(void)
42
38
{
43
39
return "Momentum Ocelot-3";
44
40
}
45
-
46
-
#ifdef CONFIG_MV643XX_ETH
47
-
void burn_clocks(void)
48
-
{
49
-
int i;
50
-
51
-
/* this loop should burn at least 1us -- this should be plenty */
52
-
for (i = 0; i < 0x10000; i++)
53
-
;
54
-
}
55
-
56
-
u8 exchange_bit(u8 val, u8 cs)
57
-
{
58
-
/* place the data */
59
-
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
60
-
burn_clocks();
61
-
62
-
/* turn the clock on */
63
-
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
64
-
burn_clocks();
65
-
66
-
/* turn the clock off and read-strobe */
67
-
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
68
-
69
-
/* return the data */
70
-
return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
71
-
}
72
-
73
-
void get_mac(char dest[6])
74
-
{
75
-
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
76
-
int i,j;
77
-
78
-
for (i = 0; i < 12; i++)
79
-
exchange_bit(read_opcode[i], 1);
80
-
81
-
for (j = 0; j < 6; j++) {
82
-
dest[j] = 0;
83
-
for (i = 0; i < 8; i++) {
84
-
dest[j] <<= 1;
85
-
dest[j] |= exchange_bit(0, 1);
86
-
}
87
-
}
88
-
89
-
/* turn off CS */
90
-
exchange_bit(0,0);
91
-
}
92
-
#endif
93
-
94
41
95
42
#ifdef CONFIG_64BIT
96
43
···
174
227
175
228
mips_machgroup = MACH_GROUP_MOMENCO;
176
229
mips_machtype = MACH_MOMENCO_OCELOT_3;
177
-
178
-
#ifdef CONFIG_MV643XX_ETH
179
-
/* get the base MAC address for on-board ethernet ports */
180
-
get_mac(prom_mac_addr_base);
181
-
#endif
182
230
183
231
#ifndef CONFIG_64BIT
184
232
debug_vectors->printf("Booting Linux kernel...\n");
+1
-1
arch/mips/momentum/ocelot_3/setup.c
+1
-1
arch/mips/momentum/ocelot_3/setup.c
···
4
4
* BRIEF MODULE DESCRIPTION
5
5
* Momentum Computer Ocelot-3 board dependent boot routines
6
6
*
7
-
* Copyright (C) 1996, 1997, 01, 05 Ralf Baechle
7
+
* Copyright (C) 1996, 1997, 01, 05 - 06 Ralf Baechle
8
8
* Copyright (C) 2000 RidgeRun, Inc.
9
9
* Copyright (C) 2001 Red Hat, Inc.
10
10
* Copyright (C) 2002 Momentum Computer
+1
-1
arch/mips/momentum/ocelot_c/Makefile
+1
-1
arch/mips/momentum/ocelot_c/Makefile
+4
-2
arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
+4
-2
arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
···
53
53
#define OCELOT_C_REG_INTSET 0xe
54
54
#define OCELOT_C_REG_INTCLR 0xf
55
55
56
-
#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y)
57
-
#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x)
56
+
#define __FPGA_REG_TO_ADDR(reg) \
57
+
((void *) OCELOT_C_CS0_ADDR + OCELOT_C_REG_##reg)
58
+
#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
59
+
#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
58
60
59
61
#endif
+201
arch/mips/momentum/ocelot_c/platform.c
+201
arch/mips/momentum/ocelot_c/platform.c
···
1
+
#include <linux/delay.h>
2
+
#include <linux/if_ether.h>
3
+
#include <linux/ioport.h>
4
+
#include <linux/mv643xx.h>
5
+
#include <linux/platform_device.h>
6
+
7
+
#include "ocelot_c_fpga.h"
8
+
9
+
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
+
11
+
static struct resource mv643xx_eth_shared_resources[] = {
12
+
[0] = {
13
+
.name = "ethernet shared base",
14
+
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15
+
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16
+
MV643XX_ETH_SHARED_REGS_SIZE - 1,
17
+
.flags = IORESOURCE_MEM,
18
+
},
19
+
};
20
+
21
+
static struct platform_device mv643xx_eth_shared_device = {
22
+
.name = MV643XX_ETH_SHARED_NAME,
23
+
.id = 0,
24
+
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25
+
.resource = mv643xx_eth_shared_resources,
26
+
};
27
+
28
+
#define MV_SRAM_BASE 0xfe000000UL
29
+
#define MV_SRAM_SIZE (256 * 1024)
30
+
31
+
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32
+
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
+
34
+
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35
+
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
+
37
+
#define MV64x60_IRQ_ETH_0 48
38
+
#define MV64x60_IRQ_ETH_1 49
39
+
40
+
#ifdef CONFIG_MV643XX_ETH_0
41
+
42
+
static struct resource mv64x60_eth0_resources[] = {
43
+
[0] = {
44
+
.name = "eth0 irq",
45
+
.start = MV64x60_IRQ_ETH_0,
46
+
.end = MV64x60_IRQ_ETH_0,
47
+
.flags = IORESOURCE_IRQ,
48
+
},
49
+
};
50
+
51
+
static char eth0_mac_addr[ETH_ALEN];
52
+
53
+
static struct mv643xx_eth_platform_data eth0_pd = {
54
+
.mac_addr = eth0_mac_addr,
55
+
56
+
.tx_sram_addr = MV_SRAM_BASE_ETH0,
57
+
.tx_sram_size = MV_SRAM_TXRING_SIZE,
58
+
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
59
+
60
+
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
61
+
.rx_sram_size = MV_SRAM_RXRING_SIZE,
62
+
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
63
+
};
64
+
65
+
static struct platform_device eth0_device = {
66
+
.name = MV643XX_ETH_NAME,
67
+
.id = 0,
68
+
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
69
+
.resource = mv64x60_eth0_resources,
70
+
.dev = {
71
+
.platform_data = ð0_pd,
72
+
},
73
+
};
74
+
#endif /* CONFIG_MV643XX_ETH_0 */
75
+
76
+
#ifdef CONFIG_MV643XX_ETH_1
77
+
78
+
static struct resource mv64x60_eth1_resources[] = {
79
+
[0] = {
80
+
.name = "eth1 irq",
81
+
.start = MV64x60_IRQ_ETH_1,
82
+
.end = MV64x60_IRQ_ETH_1,
83
+
.flags = IORESOURCE_IRQ,
84
+
},
85
+
};
86
+
87
+
static char eth1_mac_addr[ETH_ALEN];
88
+
89
+
static struct mv643xx_eth_platform_data eth1_pd = {
90
+
.mac_addr = eth1_mac_addr,
91
+
92
+
.tx_sram_addr = MV_SRAM_BASE_ETH1,
93
+
.tx_sram_size = MV_SRAM_TXRING_SIZE,
94
+
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
95
+
96
+
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
97
+
.rx_sram_size = MV_SRAM_RXRING_SIZE,
98
+
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
99
+
};
100
+
101
+
static struct platform_device eth1_device = {
102
+
.name = MV643XX_ETH_NAME,
103
+
.id = 1,
104
+
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
105
+
.resource = mv64x60_eth1_resources,
106
+
.dev = {
107
+
.platform_data = ð1_pd,
108
+
},
109
+
};
110
+
#endif /* CONFIG_MV643XX_ETH_1 */
111
+
112
+
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
113
+
&mv643xx_eth_shared_device,
114
+
#ifdef CONFIG_MV643XX_ETH_0
115
+
ð0_device,
116
+
#endif
117
+
#ifdef CONFIG_MV643XX_ETH_1
118
+
ð1_device,
119
+
#endif
120
+
/* The third port is not wired up on the Ocelot C */
121
+
};
122
+
123
+
static u8 __init exchange_bit(u8 val, u8 cs)
124
+
{
125
+
/* place the data */
126
+
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
127
+
udelay(1);
128
+
129
+
/* turn the clock on */
130
+
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
131
+
udelay(1);
132
+
133
+
/* turn the clock off and read-strobe */
134
+
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
135
+
136
+
/* return the data */
137
+
return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
138
+
}
139
+
140
+
static void __init get_mac(char dest[6])
141
+
{
142
+
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
143
+
int i,j;
144
+
145
+
for (i = 0; i < 12; i++)
146
+
exchange_bit(read_opcode[i], 1);
147
+
148
+
for (j = 0; j < 6; j++) {
149
+
dest[j] = 0;
150
+
for (i = 0; i < 8; i++) {
151
+
dest[j] <<= 1;
152
+
dest[j] |= exchange_bit(0, 1);
153
+
}
154
+
}
155
+
156
+
/* turn off CS */
157
+
exchange_bit(0,0);
158
+
}
159
+
160
+
/*
161
+
* Copy and increment ethernet MAC address by a small value.
162
+
*
163
+
* This is useful for systems where the only one MAC address is stored in
164
+
* non-volatile memory for multiple ports.
165
+
*/
166
+
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
167
+
unsigned int add)
168
+
{
169
+
int i;
170
+
171
+
BUG_ON(add >= 256);
172
+
173
+
for (i = ETH_ALEN; i >= 0; i--) {
174
+
dst[i] = src[i] + add;
175
+
add = dst[i] < src[i]; /* compute carry */
176
+
}
177
+
178
+
WARN_ON(add);
179
+
}
180
+
181
+
static int __init mv643xx_eth_add_pds(void)
182
+
{
183
+
unsigned char mac[ETH_ALEN];
184
+
int ret;
185
+
186
+
get_mac(mac);
187
+
#ifdef CONFIG_MV643XX_ETH_0
188
+
eth_mac_add(eth1_mac_addr, mac, 0);
189
+
#endif
190
+
#ifdef CONFIG_MV643XX_ETH_1
191
+
eth_mac_add(eth1_mac_addr, mac, 1);
192
+
#endif
193
+
ret = platform_add_devices(mv643xx_eth_pd_devs,
194
+
ARRAY_SIZE(mv643xx_eth_pd_devs));
195
+
196
+
return ret;
197
+
}
198
+
199
+
device_initcall(mv643xx_eth_add_pds);
200
+
201
+
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
+1
-59
arch/mips/momentum/ocelot_c/prom.c
+1
-59
arch/mips/momentum/ocelot_c/prom.c
···
29
29
struct callvectors* debug_vectors;
30
30
31
31
extern unsigned long marvell_base;
32
-
extern unsigned long cpu_clock;
33
-
34
-
#ifdef CONFIG_MV643XX_ETH
35
-
extern unsigned char prom_mac_addr_base[6];
36
-
#endif
32
+
extern unsigned int cpu_clock;
37
33
38
34
const char *get_system_type(void)
39
35
{
···
39
43
return "Momentum Ocelot-C";
40
44
#endif
41
45
}
42
-
43
-
#ifdef CONFIG_MV643XX_ETH
44
-
static void burn_clocks(void)
45
-
{
46
-
int i;
47
-
48
-
/* this loop should burn at least 1us -- this should be plenty */
49
-
for (i = 0; i < 0x10000; i++)
50
-
;
51
-
}
52
-
53
-
static u8 exchange_bit(u8 val, u8 cs)
54
-
{
55
-
/* place the data */
56
-
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
57
-
burn_clocks();
58
-
59
-
/* turn the clock on */
60
-
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
61
-
burn_clocks();
62
-
63
-
/* turn the clock off and read-strobe */
64
-
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
65
-
66
-
/* return the data */
67
-
return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
68
-
}
69
-
70
-
void get_mac(char dest[6])
71
-
{
72
-
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
73
-
int i,j;
74
-
75
-
for (i = 0; i < 12; i++)
76
-
exchange_bit(read_opcode[i], 1);
77
-
78
-
for (j = 0; j < 6; j++) {
79
-
dest[j] = 0;
80
-
for (i = 0; i < 8; i++) {
81
-
dest[j] <<= 1;
82
-
dest[j] |= exchange_bit(0, 1);
83
-
}
84
-
}
85
-
86
-
/* turn off CS */
87
-
exchange_bit(0,0);
88
-
}
89
-
#endif
90
-
91
46
92
47
#ifdef CONFIG_64BIT
93
48
···
172
225
173
226
mips_machgroup = MACH_GROUP_MOMENCO;
174
227
mips_machtype = MACH_MOMENCO_OCELOT_C;
175
-
176
-
#ifdef CONFIG_MV643XX_ETH
177
-
/* get the base MAC address for on-board ethernet ports */
178
-
get_mac(prom_mac_addr_base);
179
-
#endif
180
228
181
229
#ifndef CONFIG_64BIT
182
230
debug_vectors->printf("Booting Linux kernel...\n");
+9
-14
arch/mips/momentum/ocelot_c/setup.c
+9
-14
arch/mips/momentum/ocelot_c/setup.c
···
69
69
#include "ocelot_c_fpga.h"
70
70
71
71
unsigned long marvell_base;
72
-
extern unsigned long mv64340_sram_base;
73
-
unsigned long cpu_clock;
72
+
unsigned int cpu_clock;
74
73
75
74
/* These functions are used for rebooting or halting the machine*/
76
75
extern void momenco_ocelot_restart(char *command);
···
118
119
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
119
120
120
121
marvell_base = 0xfffffffff4000000;
121
-
mv64340_sram_base = 0xfffffffffe000000;
122
122
#else
123
123
/* marvell and extra space */
124
124
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
···
127
129
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
128
130
129
131
marvell_base = 0xf4000000;
130
-
mv64340_sram_base = 0xfe000000;
131
132
#endif
132
133
}
133
134
···
343
346
}
344
347
}
345
348
346
-
#ifndef CONFIG_64BIT
347
-
/* This needs to be one of the first initcalls, because no I/O port access
348
-
can work before this */
349
+
/*
350
+
* This needs to be one of the first initcalls, because no I/O port access
351
+
* can work before this
352
+
*/
349
353
static int io_base_ioremap(void)
350
354
{
351
-
/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
352
-
void *io_remap_range = ioremap(0xc0000000, 0x30000000);
355
+
void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
353
356
354
-
if (!io_remap_range) {
357
+
if (!io_remap_range)
355
358
panic("Could not ioremap I/O port range");
356
-
}
357
-
printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
358
-
set_io_port_base(io_remap_range - 0xc0000000);
359
+
360
+
set_io_port_base((unsigned long) io_remap_range);
359
361
360
362
return 0;
361
363
}
362
364
363
365
module_init(io_base_ioremap);
364
-
#endif
+1
-1
arch/mips/pci/Makefile
+1
-1
arch/mips/pci/Makefile
···
26
26
obj-$(CONFIG_LASAT) += pci-lasat.o
27
27
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
28
28
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
29
-
obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o
29
+
obj-$(CONFIG_MIPS_EV64120) += pci-ev64120.o
30
30
obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
31
31
obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
32
32
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
-34
arch/mips/pci/fixup-ev64120.c
-34
arch/mips/pci/fixup-ev64120.c
···
1
-
#include <linux/pci.h>
2
-
#include <linux/init.h>
3
-
4
-
int pci_range_ck(unsigned char bus, unsigned char dev)
5
-
{
6
-
if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8))
7
-
return 0;
8
-
9
-
return -1;
10
-
}
11
-
12
-
/*
13
-
* After detecting all agents over the PCI , this function is called
14
-
* in order to give an interrupt number for each PCI device starting
15
-
* from IRQ 20. It does also enables master for each device.
16
-
*/
17
-
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
18
-
{
19
-
unsigned int irq = 20;
20
-
struct pci_bus *current_bus = bus;
21
-
struct pci_dev *dev;
22
-
struct list_head *devices_link;
23
-
24
-
list_for_each(devices_link, &(current_bus->devices)) {
25
-
dev = pci_dev_b(devices_link);
26
-
if (dev != NULL) {
27
-
dev->irq = irq++;
28
-
29
-
/* Assign an interrupt number for the device */
30
-
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
31
-
pcibios_set_master(dev);
32
-
}
33
-
}
34
-
}
+21
arch/mips/pci/pci-ev64120.c
+21
arch/mips/pci/pci-ev64120.c
···
1
+
#include <linux/pci.h>
2
+
3
+
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
4
+
{
5
+
int irq;
6
+
7
+
if (!pin)
8
+
return 0;
9
+
10
+
irq = allocate_irqno();
11
+
if (irq < 0)
12
+
return 0;
13
+
14
+
return irq;
15
+
}
16
+
17
+
/* Do platform specific device initialization at pci_enable_device() time */
18
+
int pcibios_plat_dev_init(struct pci_dev *dev)
19
+
{
20
+
return 0;
21
+
}
-23
arch/mips/sgi-ip27/ip27-irq.c
-23
arch/mips/sgi-ip27/ip27-irq.c
···
354
354
.end = end_bridge_irq,
355
355
};
356
356
357
-
static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
358
-
359
-
int allocate_irqno(void)
360
-
{
361
-
int irq;
362
-
363
-
again:
364
-
irq = find_first_zero_bit(irq_map, NR_IRQS);
365
-
366
-
if (irq >= NR_IRQS)
367
-
return -ENOSPC;
368
-
369
-
if (test_and_set_bit(irq, irq_map))
370
-
goto again;
371
-
372
-
return irq;
373
-
}
374
-
375
-
void free_irqno(unsigned int irq)
376
-
{
377
-
clear_bit(irq, irq_map);
378
-
}
379
-
380
357
void __devinit register_bridge_irq(unsigned int irq)
381
358
{
382
359
irq_desc[irq].status = IRQ_DISABLED;
-2
arch/mips/sgi-ip27/ip27-timer.c
-2
arch/mips/sgi-ip27/ip27-timer.c