tjh.dev / kernel
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perf/x86/intel: Add core PMU support for Novalake

This patch enables core PMU support for Novalake, covering both P-core
and E-core. It includes Arctic Wolf-specific counters and PEBS
constraints, and the model-specific OMR extra registers table.

Since Coyote Cove shares the same PMU capabilities as Panther Cove, the
existing Panther Cove PMU enabling functions are reused for Coyote Cove.

For detailed information about counter constraints, please refer to
section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260114011750.350569-6-dapeng1.mi@linux.intel.com

authored by

Dapeng Mi and committed by
Peter Zijlstra c847a208 7cd264d1

+112
+99
arch/x86/events/intel/core.c
··· 232 232 EVENT_CONSTRAINT_END 233 233 }; 234 234 235 + static struct event_constraint intel_arw_event_constraints[] __read_mostly = { 236 + FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 237 + FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 238 + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 239 + FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 240 + FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 241 + FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 242 + FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 243 + INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1), 244 + INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2), 245 + INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4), 246 + INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8), 247 + INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1), 248 + INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2), 249 + INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4), 250 + INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8), 251 + INTEL_UEVENT_CONSTRAINT(0x0175, 0x1), 252 + INTEL_UEVENT_CONSTRAINT(0x0275, 0x2), 253 + INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1), 254 + INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1), 255 + EVENT_CONSTRAINT_END 256 + }; 257 + 235 258 static struct event_constraint intel_skl_event_constraints[] = { 236 259 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 237 260 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ ··· 2342 2319 }, 2343 2320 }; 2344 2321 2322 + static __initconst const u64 arw_hw_cache_extra_regs 2323 + [PERF_COUNT_HW_CACHE_MAX] 2324 + [PERF_COUNT_HW_CACHE_OP_MAX] 2325 + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2326 + [C(LL)] = { 2327 + [C(OP_READ)] = { 2328 + [C(RESULT_ACCESS)] = 0x4000000000000001, 2329 + [C(RESULT_MISS)] = 0xFFFFF000000001, 2330 + }, 2331 + [C(OP_WRITE)] = { 2332 + [C(RESULT_ACCESS)] = 0x4000000000000002, 2333 + [C(RESULT_MISS)] = 0xFFFFF000000002, 2334 + }, 2335 + [C(OP_PREFETCH)] = { 2336 + [C(RESULT_ACCESS)] = 0x0, 2337 + [C(RESULT_MISS)] = 0x0, 2338 + }, 2339 + }, 2340 + }; 2341 + 2345 2342 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2346 2343 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2347 2344 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); ··· 2414 2371 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2415 2372 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2416 2373 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2374 + INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2375 + INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2376 + INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2377 + EVENT_EXTRA_END 2378 + }; 2379 + 2380 + static struct extra_reg intel_arw_extra_regs[] __read_mostly = { 2381 + /* must define OMR_X first, see intel_alt_er() */ 2382 + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0), 2383 + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), 2384 + INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), 2385 + INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), 2386 + INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0), 2387 + INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), 2388 + INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), 2389 + INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), 2417 2390 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2418 2391 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2419 2392 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), ··· 7469 7410 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7470 7411 } 7471 7412 7413 + static __always_inline void intel_pmu_init_arw(struct pmu *pmu) 7414 + { 7415 + intel_pmu_init_grt(pmu); 7416 + x86_pmu.flags &= ~PMU_FL_HAS_RSP_1; 7417 + x86_pmu.flags |= PMU_FL_HAS_OMR; 7418 + memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7419 + arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7420 + hybrid(pmu, event_constraints) = intel_arw_event_constraints; 7421 + hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints; 7422 + hybrid(pmu, extra_regs) = intel_arw_extra_regs; 7423 + static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7424 + } 7425 + 7472 7426 __init int intel_pmu_init(void) 7473 7427 { 7474 7428 struct attribute **extra_skl_attr = &empty_attrs; ··· 8320 8248 intel_pmu_pebs_data_source_arl_h(); 8321 8249 pr_cont("ArrowLake-H Hybrid events, "); 8322 8250 name = "arrowlake_h_hybrid"; 8251 + break; 8252 + 8253 + case INTEL_NOVALAKE: 8254 + case INTEL_NOVALAKE_L: 8255 + pr_cont("Novalake Hybrid events, "); 8256 + name = "novalake_hybrid"; 8257 + intel_pmu_init_hybrid(hybrid_big_small); 8258 + 8259 + x86_pmu.pebs_latency_data = nvl_latency_data; 8260 + x86_pmu.get_event_constraints = mtl_get_event_constraints; 8261 + x86_pmu.hw_config = adl_hw_config; 8262 + 8263 + td_attr = lnl_hybrid_events_attrs; 8264 + mem_attr = mtl_hybrid_mem_attrs; 8265 + tsx_attr = adl_hybrid_tsx_attrs; 8266 + extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8267 + mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8268 + 8269 + /* Initialize big core specific PerfMon capabilities.*/ 8270 + pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8271 + intel_pmu_init_pnc(&pmu->pmu); 8272 + 8273 + /* Initialize Atom core specific PerfMon capabilities.*/ 8274 + pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8275 + intel_pmu_init_arw(&pmu->pmu); 8276 + 8277 + intel_pmu_pebs_data_source_lnl(); 8323 8278 break; 8324 8279 8325 8280 default:
+11
arch/x86/events/intel/ds.c
··· 1293 1293 EVENT_CONSTRAINT_END 1294 1294 }; 1295 1295 1296 + struct event_constraint intel_arw_pebs_event_constraints[] = { 1297 + /* Allow all events as PEBS with no flags */ 1298 + INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff), 1299 + INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff), 1300 + INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1), 1301 + INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2), 1302 + INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4), 1303 + INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8), 1304 + EVENT_CONSTRAINT_END 1305 + }; 1306 + 1296 1307 struct event_constraint intel_nehalem_pebs_event_constraints[] = { 1297 1308 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 1298 1309 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
+2
arch/x86/events/perf_event.h
··· 1680 1680 1681 1681 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1682 1682 1683 + extern struct event_constraint intel_arw_pebs_event_constraints[]; 1684 + 1683 1685 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1684 1686 1685 1687 extern struct event_constraint intel_westmere_pebs_event_constraints[];