Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'i3c/for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
Pull i3c updates from Alexandre Belloni:
"This cycle, there are new features for the Designware controller and
fixes for the other IPs:
- dw: optional apb clock and power management support, IBI handling
fixes
- mipi-i3c-hci: IBI handling fixes
- svc: a few fixes"
* tag 'i3c/for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux:
dt-bindings: i3c: add header for generic I3C flags
i3c: master: svc: Fix error code in svc_i3c_master_do_daa_locked()
i3c: master: Enhance i3c_bus_type visibility for device searching & event monitoring
i3c: dw: Add power management support
i3c: dw: Add some functions for reusability
i3c: dw: Save timing registers and other values
i3c: master: svc: Improve DAA STOP handle code logic
i3c: dw: Add optional apb clock
i3c: dw: Use new *_enabled clk API
dt-bindings: i3c: dw: Add apb clock binding
i3c: master: svc: Convert comma to semicolon
i3c: mipi-i3c-hci: Round IBI data chunk size to HW supported value
i3c: mipi-i3c-hci: Error out instead on BUG_ON() in IBI DMA setup
i3c: mipi-i3c-hci: Set IBI Status and Data Ring base addresses
i3c: mipi-i3c-hci: Switch to lower_32_bits()/upper_32_bits() helpers
i3c: dw: Remove ibi_capable property
i3c: dw: Fix IBI intr programming
i3c: dw: Fix clearing queue thld
i3c: mipi-i3c-hci: Fix number of DAT/DCT entries for HCI versions < 1.1
i3c: master: svc: resend target address when get NACK
+431
-143
+4
-1
Documentation/devicetree/bindings/i3c/i3c.yaml
+4
-1
Documentation/devicetree/bindings/i3c/i3c.yaml
···
91
91
- const: 0
92
92
- description: |
93
93
Shall encode the I3C LVR (Legacy Virtual Register):
94
+
See include/dt-bindings/i3c/i3c.h
94
95
bit[31:8]: unused/ignored
95
96
bit[7:5]: I2C device index. Possible values:
96
97
* 0: I2C device has a 50 ns spike filter
···
154
153
155
154
examples:
156
155
- |
156
+
#include <dt-bindings/i3c/i3c.h>
157
+
157
158
i3c@d040000 {
158
159
compatible = "cdns,i3c-master";
159
160
clocks = <&coreclock>, <&i3csysclock>;
···
169
166
/* I2C device. */
170
167
eeprom@57 {
171
168
compatible = "atmel,24c01";
172
-
reg = <0x57 0x0 0x10>;
169
+
reg = <0x57 0x0 (I2C_FM | I2C_FILTER)>;
173
170
pagesize = <0x8>;
174
171
};
175
172
+10
-1
Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+10
-1
Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+1
MAINTAINERS
+1
MAINTAINERS
-2
drivers/i3c/internals.h
-2
drivers/i3c/internals.h
+1
drivers/i3c/master.c
+1
drivers/i3c/master.c
-1
drivers/i3c/master/ast2600-i3c-master.c
-1
drivers/i3c/master/ast2600-i3c-master.c
+268
-81
drivers/i3c/master/dw-i3c-master.c
+268
-81
drivers/i3c/master/dw-i3c-master.c
···
17
17
#include <linux/list.h>
18
18
#include <linux/module.h>
19
19
#include <linux/of.h>
20
+
#include <linux/pinctrl/consumer.h>
20
21
#include <linux/platform_device.h>
22
+
#include <linux/pm_runtime.h>
21
23
#include <linux/reset.h>
22
24
#include <linux/slab.h>
23
25
···
219
217
#define I3C_BUS_THIGH_MAX_NS 41
220
218
221
219
#define XFER_TIMEOUT (msecs_to_jiffies(1000))
222
-
220
+
#define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */
223
221
struct dw_i3c_cmd {
224
222
u32 cmd_lo;
225
223
u32 cmd_hi;
···
302
300
303
301
static void dw_i3c_master_enable(struct dw_i3c_master *master)
304
302
{
305
-
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
303
+
u32 dev_ctrl;
304
+
305
+
dev_ctrl = readl(master->regs + DEVICE_CTRL);
306
+
/* For now don't support Hot-Join */
307
+
dev_ctrl |= DEV_CTRL_HOT_JOIN_NACK;
308
+
if (master->i2c_slv_prsnt)
309
+
dev_ctrl |= DEV_CTRL_I2C_SLAVE_PRESENT;
310
+
writel(dev_ctrl | DEV_CTRL_ENABLE,
306
311
master->regs + DEVICE_CTRL);
307
312
}
308
313
···
530
521
dw_i3c_master_start_xfer_locked(master);
531
522
}
532
523
524
+
static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master)
525
+
{
526
+
u32 thld_ctrl;
527
+
528
+
thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
529
+
thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK |
530
+
QUEUE_THLD_CTRL_IBI_STAT_MASK |
531
+
QUEUE_THLD_CTRL_IBI_DATA_MASK);
532
+
thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) |
533
+
QUEUE_THLD_CTRL_IBI_DATA(31);
534
+
writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
535
+
536
+
thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
537
+
thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
538
+
writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
539
+
540
+
writel(INTR_ALL, master->regs + INTR_STATUS);
541
+
writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
542
+
writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
543
+
544
+
master->sir_rej_mask = IBI_REQ_REJECT_ALL;
545
+
writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
546
+
547
+
writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
548
+
}
549
+
533
550
static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
534
551
{
535
552
unsigned long core_rate, core_period;
···
578
543
579
544
scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
580
545
writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
546
+
master->i3c_pp_timing = scl_timing;
581
547
582
548
/*
583
549
* In pure i3c mode, MST_FREE represents tCAS. In shared mode, this
584
550
* will be set up by dw_i2c_clk_cfg as tLOW.
585
551
*/
586
-
if (master->base.bus.mode == I3C_BUS_MODE_PURE)
552
+
if (master->base.bus.mode == I3C_BUS_MODE_PURE) {
587
553
writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
554
+
master->bus_free_timing = BUS_I3C_MST_FREE(lcnt);
555
+
}
588
556
589
557
lcnt = max_t(u8,
590
558
DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt);
591
559
scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
592
560
writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
561
+
master->i3c_od_timing = scl_timing;
593
562
594
563
lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
595
564
scl_timing = SCL_EXT_LCNT_1(lcnt);
···
604
565
lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
605
566
scl_timing |= SCL_EXT_LCNT_4(lcnt);
606
567
writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
568
+
master->ext_lcnt_timing = scl_timing;
607
569
608
570
return 0;
609
571
}
···
626
586
scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
627
587
SCL_I2C_FMP_TIMING_LCNT(lcnt);
628
588
writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
589
+
master->i2c_fmp_timing = scl_timing;
629
590
630
591
lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
631
592
hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt;
632
593
scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
633
594
SCL_I2C_FM_TIMING_LCNT(lcnt);
634
595
writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
596
+
master->i2c_fm_timing = scl_timing;
635
597
636
598
writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
599
+
master->bus_free_timing = BUS_I3C_MST_FREE(lcnt);
600
+
637
601
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
638
602
master->regs + DEVICE_CTRL);
603
+
master->i2c_slv_prsnt = true;
639
604
640
605
return 0;
641
606
}
···
650
605
struct dw_i3c_master *master = to_dw_i3c_master(m);
651
606
struct i3c_bus *bus = i3c_master_get_bus(m);
652
607
struct i3c_device_info info = { };
653
-
u32 thld_ctrl;
654
608
int ret;
609
+
610
+
ret = pm_runtime_resume_and_get(master->dev);
611
+
if (ret < 0) {
612
+
dev_err(master->dev,
613
+
"<%s> cannot resume i3c bus master, err: %d\n",
614
+
__func__, ret);
615
+
return ret;
616
+
}
655
617
656
618
ret = master->platform_ops->init(master);
657
619
if (ret)
658
-
return ret;
620
+
goto rpm_out;
659
621
660
622
switch (bus->mode) {
661
623
case I3C_BUS_MODE_MIXED_FAST:
662
624
case I3C_BUS_MODE_MIXED_LIMITED:
663
625
ret = dw_i2c_clk_cfg(master);
664
626
if (ret)
665
-
return ret;
627
+
goto rpm_out;
666
628
fallthrough;
667
629
case I3C_BUS_MODE_PURE:
668
630
ret = dw_i3c_clk_cfg(master);
669
631
if (ret)
670
-
return ret;
632
+
goto rpm_out;
671
633
break;
672
634
default:
673
-
return -EINVAL;
635
+
ret = -EINVAL;
636
+
goto rpm_out;
674
637
}
675
-
676
-
thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
677
-
thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK |
678
-
QUEUE_THLD_CTRL_IBI_STAT_MASK |
679
-
QUEUE_THLD_CTRL_IBI_STAT_MASK);
680
-
thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) |
681
-
QUEUE_THLD_CTRL_IBI_DATA(31);
682
-
writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
683
-
684
-
thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
685
-
thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
686
-
writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
687
-
688
-
writel(INTR_ALL, master->regs + INTR_STATUS);
689
-
writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
690
-
writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
691
638
692
639
ret = i3c_master_get_free_addr(m, 0);
693
640
if (ret < 0)
694
-
return ret;
641
+
goto rpm_out;
695
642
696
643
writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
697
644
master->regs + DEVICE_ADDR);
698
-
645
+
master->dev_addr = ret;
699
646
memset(&info, 0, sizeof(info));
700
647
info.dyn_addr = ret;
701
648
702
649
ret = i3c_master_set_info(&master->base, &info);
703
650
if (ret)
704
-
return ret;
651
+
goto rpm_out;
705
652
706
-
writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
707
-
writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
708
-
709
-
/* For now don't support Hot-Join */
710
-
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
711
-
master->regs + DEVICE_CTRL);
712
-
653
+
dw_i3c_master_set_intr_regs(master);
713
654
dw_i3c_master_enable(master);
714
655
715
-
return 0;
656
+
rpm_out:
657
+
pm_runtime_mark_last_busy(master->dev);
658
+
pm_runtime_put_autosuspend(master->dev);
659
+
return ret;
716
660
}
717
661
718
662
static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
···
803
769
if (ccc->id == I3C_CCC_ENTDAA)
804
770
return -EINVAL;
805
771
772
+
ret = pm_runtime_resume_and_get(master->dev);
773
+
if (ret < 0) {
774
+
dev_err(master->dev,
775
+
"<%s> cannot resume i3c bus master, err: %d\n",
776
+
__func__, ret);
777
+
return ret;
778
+
}
779
+
806
780
if (ccc->rnw)
807
781
ret = dw_i3c_ccc_get(master, ccc);
808
782
else
809
783
ret = dw_i3c_ccc_set(master, ccc);
810
784
785
+
pm_runtime_mark_last_busy(master->dev);
786
+
pm_runtime_put_autosuspend(master->dev);
811
787
return ret;
812
788
}
813
789
···
830
786
u8 p, last_addr = 0;
831
787
int ret, pos;
832
788
789
+
ret = pm_runtime_resume_and_get(master->dev);
790
+
if (ret < 0) {
791
+
dev_err(master->dev,
792
+
"<%s> cannot resume i3c bus master, err: %d\n",
793
+
__func__, ret);
794
+
return ret;
795
+
}
796
+
833
797
olddevs = ~(master->free_pos);
834
798
835
799
/* Prepare DAT before launching DAA. */
···
846
794
continue;
847
795
848
796
ret = i3c_master_get_free_addr(m, last_addr + 1);
849
-
if (ret < 0)
850
-
return -ENOSPC;
797
+
if (ret < 0) {
798
+
ret = -ENOSPC;
799
+
goto rpm_out;
800
+
}
851
801
852
802
master->devs[pos].addr = ret;
853
803
p = even_parity(ret);
···
859
805
writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
860
806
master->regs +
861
807
DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
808
+
809
+
ret = 0;
862
810
}
863
811
864
812
xfer = dw_i3c_master_alloc_xfer(master, 1);
865
-
if (!xfer)
866
-
return -ENOMEM;
813
+
if (!xfer) {
814
+
ret = -ENOMEM;
815
+
goto rpm_out;
816
+
}
867
817
868
818
pos = dw_i3c_master_get_free_pos(master);
869
819
if (pos < 0) {
870
820
dw_i3c_master_free_xfer(xfer);
871
-
return pos;
821
+
ret = pos;
822
+
goto rpm_out;
872
823
}
873
824
cmd = &xfer->cmds[0];
874
825
cmd->cmd_hi = 0x1;
···
898
839
899
840
dw_i3c_master_free_xfer(xfer);
900
841
901
-
return 0;
842
+
rpm_out:
843
+
pm_runtime_mark_last_busy(master->dev);
844
+
pm_runtime_put_autosuspend(master->dev);
845
+
return ret;
902
846
}
903
847
904
848
static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
···
935
873
xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
936
874
if (!xfer)
937
875
return -ENOMEM;
876
+
877
+
ret = pm_runtime_resume_and_get(master->dev);
878
+
if (ret < 0) {
879
+
dev_err(master->dev,
880
+
"<%s> cannot resume i3c bus master, err: %d\n",
881
+
__func__, ret);
882
+
return ret;
883
+
}
938
884
939
885
for (i = 0; i < i3c_nxfers; i++) {
940
886
struct dw_i3c_cmd *cmd = &xfer->cmds[i];
···
985
915
ret = xfer->ret;
986
916
dw_i3c_master_free_xfer(xfer);
987
917
918
+
pm_runtime_mark_last_busy(master->dev);
919
+
pm_runtime_put_autosuspend(master->dev);
988
920
return ret;
989
921
}
990
922
···
1097
1025
if (!xfer)
1098
1026
return -ENOMEM;
1099
1027
1028
+
ret = pm_runtime_resume_and_get(master->dev);
1029
+
if (ret < 0) {
1030
+
dev_err(master->dev,
1031
+
"<%s> cannot resume i3c bus master, err: %d\n",
1032
+
__func__, ret);
1033
+
return ret;
1034
+
}
1035
+
1100
1036
for (i = 0; i < i2c_nxfers; i++) {
1101
1037
struct dw_i3c_cmd *cmd = &xfer->cmds[i];
1102
1038
···
1135
1055
ret = xfer->ret;
1136
1056
dw_i3c_master_free_xfer(xfer);
1137
1057
1058
+
pm_runtime_mark_last_busy(master->dev);
1059
+
pm_runtime_put_autosuspend(master->dev);
1138
1060
return ret;
1139
1061
}
1140
1062
···
1157
1075
1158
1076
data->index = pos;
1159
1077
master->devs[pos].addr = dev->addr;
1078
+
master->devs[pos].is_i2c_addr = true;
1160
1079
master->free_pos &= ~BIT(pos);
1161
1080
i2c_dev_set_master_data(dev, data);
1162
1081
···
1258
1175
master->platform_ops->set_dat_ibi(master, dev, enable, ®);
1259
1176
writel(reg, master->regs + dat_entry);
1260
1177
1261
-
reg = readl(master->regs + IBI_SIR_REQ_REJECT);
1262
1178
if (enable) {
1263
-
global = reg == 0xffffffff;
1264
-
reg &= ~BIT(idx);
1179
+
global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL);
1180
+
master->sir_rej_mask &= ~BIT(idx);
1265
1181
} else {
1266
1182
bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK);
1267
1183
1268
-
reg |= BIT(idx);
1269
-
global = (reg == 0xffffffff) && hj_rejected;
1184
+
master->sir_rej_mask |= BIT(idx);
1185
+
global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected;
1270
1186
}
1271
-
writel(reg, master->regs + IBI_SIR_REQ_REJECT);
1187
+
writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
1272
1188
1273
1189
if (global)
1274
1190
dw_i3c_master_enable_sir_signal(master, enable);
···
1279
1197
static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m)
1280
1198
{
1281
1199
struct dw_i3c_master *master = to_dw_i3c_master(m);
1200
+
int ret;
1201
+
1202
+
ret = pm_runtime_resume_and_get(master->dev);
1203
+
if (ret < 0) {
1204
+
dev_err(master->dev,
1205
+
"<%s> cannot resume i3c bus master, err: %d\n",
1206
+
__func__, ret);
1207
+
return ret;
1208
+
}
1282
1209
1283
1210
dw_i3c_master_enable_sir_signal(master, true);
1284
1211
writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK,
···
1303
1212
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
1304
1213
master->regs + DEVICE_CTRL);
1305
1214
1215
+
pm_runtime_mark_last_busy(master->dev);
1216
+
pm_runtime_put_autosuspend(master->dev);
1306
1217
return 0;
1307
1218
}
1308
1219
···
1315
1222
struct dw_i3c_master *master = to_dw_i3c_master(m);
1316
1223
int rc;
1317
1224
1225
+
rc = pm_runtime_resume_and_get(master->dev);
1226
+
if (rc < 0) {
1227
+
dev_err(master->dev,
1228
+
"<%s> cannot resume i3c bus master, err: %d\n",
1229
+
__func__, rc);
1230
+
return rc;
1231
+
}
1232
+
1318
1233
dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
1319
1234
1320
1235
rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1321
1236
1322
-
if (rc)
1237
+
if (rc) {
1323
1238
dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1239
+
pm_runtime_mark_last_busy(master->dev);
1240
+
pm_runtime_put_autosuspend(master->dev);
1241
+
}
1324
1242
1325
1243
return rc;
1326
1244
}
···
1349
1245
1350
1246
dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1351
1247
1248
+
pm_runtime_mark_last_busy(master->dev);
1249
+
pm_runtime_put_autosuspend(master->dev);
1352
1250
return 0;
1353
1251
}
1354
1252
···
1509
1403
.attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1510
1404
.detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1511
1405
.i2c_xfers = dw_i3c_master_i2c_xfers,
1512
-
};
1513
-
1514
-
static const struct i3c_master_controller_ops dw_mipi_i3c_ibi_ops = {
1515
-
.bus_init = dw_i3c_master_bus_init,
1516
-
.bus_cleanup = dw_i3c_master_bus_cleanup,
1517
-
.attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
1518
-
.reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
1519
-
.detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
1520
-
.do_daa = dw_i3c_master_daa,
1521
-
.supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
1522
-
.send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
1523
-
.priv_xfers = dw_i3c_master_priv_xfers,
1524
-
.attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1525
-
.detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1526
-
.i2c_xfers = dw_i3c_master_i2c_xfers,
1527
1406
.request_ibi = dw_i3c_master_request_ibi,
1528
1407
.free_ibi = dw_i3c_master_free_ibi,
1529
1408
.enable_ibi = dw_i3c_master_enable_ibi,
···
1546
1455
int dw_i3c_common_probe(struct dw_i3c_master *master,
1547
1456
struct platform_device *pdev)
1548
1457
{
1549
-
const struct i3c_master_controller_ops *ops;
1550
1458
int ret, irq;
1551
1459
1552
1460
if (!master->platform_ops)
1553
1461
master->platform_ops = &dw_i3c_platform_ops_default;
1554
1462
1463
+
master->dev = &pdev->dev;
1464
+
1555
1465
master->regs = devm_platform_ioremap_resource(pdev, 0);
1556
1466
if (IS_ERR(master->regs))
1557
1467
return PTR_ERR(master->regs);
1558
1468
1559
-
master->core_clk = devm_clk_get(&pdev->dev, NULL);
1469
+
master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL);
1560
1470
if (IS_ERR(master->core_clk))
1561
1471
return PTR_ERR(master->core_clk);
1472
+
1473
+
master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
1474
+
if (IS_ERR(master->pclk))
1475
+
return PTR_ERR(master->pclk);
1562
1476
1563
1477
master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1564
1478
"core_rst");
1565
1479
if (IS_ERR(master->core_rst))
1566
1480
return PTR_ERR(master->core_rst);
1567
-
1568
-
ret = clk_prepare_enable(master->core_clk);
1569
-
if (ret)
1570
-
goto err_disable_core_clk;
1571
1481
1572
1482
reset_control_deassert(master->core_rst);
1573
1483
···
1585
1493
1586
1494
platform_set_drvdata(pdev, master);
1587
1495
1496
+
pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT);
1497
+
pm_runtime_use_autosuspend(&pdev->dev);
1498
+
pm_runtime_set_active(&pdev->dev);
1499
+
pm_runtime_enable(&pdev->dev);
1500
+
1588
1501
/* Information regarding the FIFOs/QUEUEs depth */
1589
1502
ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1590
1503
master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
···
1602
1505
master->maxdevs = ret >> 16;
1603
1506
master->free_pos = GENMASK(master->maxdevs - 1, 0);
1604
1507
1605
-
ops = &dw_mipi_i3c_ops;
1606
-
if (master->ibi_capable)
1607
-
ops = &dw_mipi_i3c_ibi_ops;
1608
-
1609
1508
INIT_WORK(&master->hj_work, dw_i3c_hj_work);
1610
-
ret = i3c_master_register(&master->base, &pdev->dev, ops, false);
1509
+
ret = i3c_master_register(&master->base, &pdev->dev,
1510
+
&dw_mipi_i3c_ops, false);
1611
1511
if (ret)
1612
-
goto err_assert_rst;
1512
+
goto err_disable_pm;
1613
1513
1614
1514
return 0;
1615
1515
1516
+
err_disable_pm:
1517
+
pm_runtime_disable(&pdev->dev);
1518
+
pm_runtime_set_suspended(&pdev->dev);
1519
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
1520
+
1616
1521
err_assert_rst:
1617
1522
reset_control_assert(master->core_rst);
1618
-
1619
-
err_disable_core_clk:
1620
-
clk_disable_unprepare(master->core_clk);
1621
1523
1622
1524
return ret;
1623
1525
}
···
1626
1530
{
1627
1531
i3c_master_unregister(&master->base);
1628
1532
1629
-
reset_control_assert(master->core_rst);
1630
-
1631
-
clk_disable_unprepare(master->core_clk);
1533
+
pm_runtime_disable(master->dev);
1534
+
pm_runtime_set_suspended(master->dev);
1535
+
pm_runtime_dont_use_autosuspend(master->dev);
1632
1536
}
1633
1537
EXPORT_SYMBOL_GPL(dw_i3c_common_remove);
1634
1538
···
1652
1556
dw_i3c_common_remove(master);
1653
1557
}
1654
1558
1559
+
static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master)
1560
+
{
1561
+
u32 pos, reg_val;
1562
+
1563
+
writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr),
1564
+
master->regs + DEVICE_ADDR);
1565
+
1566
+
for (pos = 0; pos < master->maxdevs; pos++) {
1567
+
if (master->free_pos & BIT(pos))
1568
+
continue;
1569
+
1570
+
if (master->devs[pos].is_i2c_addr)
1571
+
reg_val = DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1572
+
DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr);
1573
+
else
1574
+
reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
1575
+
1576
+
writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1577
+
}
1578
+
}
1579
+
1580
+
static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master)
1581
+
{
1582
+
writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
1583
+
writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING);
1584
+
writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
1585
+
writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING);
1586
+
1587
+
if (master->i2c_slv_prsnt) {
1588
+
writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING);
1589
+
writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING);
1590
+
}
1591
+
}
1592
+
1593
+
static int dw_i3c_master_enable_clks(struct dw_i3c_master *master)
1594
+
{
1595
+
int ret = 0;
1596
+
1597
+
ret = clk_prepare_enable(master->core_clk);
1598
+
if (ret)
1599
+
return ret;
1600
+
1601
+
ret = clk_prepare_enable(master->pclk);
1602
+
if (ret) {
1603
+
clk_disable_unprepare(master->core_clk);
1604
+
return ret;
1605
+
}
1606
+
1607
+
return 0;
1608
+
}
1609
+
1610
+
static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master)
1611
+
{
1612
+
clk_disable_unprepare(master->pclk);
1613
+
clk_disable_unprepare(master->core_clk);
1614
+
}
1615
+
1616
+
static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
1617
+
{
1618
+
struct dw_i3c_master *master = dev_get_drvdata(dev);
1619
+
1620
+
dw_i3c_master_disable(master);
1621
+
1622
+
reset_control_assert(master->core_rst);
1623
+
dw_i3c_master_disable_clks(master);
1624
+
pinctrl_pm_select_sleep_state(dev);
1625
+
return 0;
1626
+
}
1627
+
1628
+
static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
1629
+
{
1630
+
struct dw_i3c_master *master = dev_get_drvdata(dev);
1631
+
1632
+
pinctrl_pm_select_default_state(dev);
1633
+
dw_i3c_master_enable_clks(master);
1634
+
reset_control_deassert(master->core_rst);
1635
+
1636
+
dw_i3c_master_set_intr_regs(master);
1637
+
dw_i3c_master_restore_timing_regs(master);
1638
+
dw_i3c_master_restore_addrs(master);
1639
+
1640
+
dw_i3c_master_enable(master);
1641
+
return 0;
1642
+
}
1643
+
1644
+
static const struct dev_pm_ops dw_i3c_pm_ops = {
1645
+
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1646
+
SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL)
1647
+
};
1648
+
1655
1649
static const struct of_device_id dw_i3c_master_of_match[] = {
1656
1650
{ .compatible = "snps,dw-i3c-master-1.00a", },
1657
1651
{},
···
1754
1568
.driver = {
1755
1569
.name = "dw-i3c-master",
1756
1570
.of_match_table = dw_i3c_master_of_match,
1571
+
.pm = &dw_i3c_pm_ops,
1757
1572
},
1758
1573
};
1759
1574
module_platform_driver(dw_i3c_driver);
+12
-2
drivers/i3c/master/dw-i3c-master.h
+12
-2
drivers/i3c/master/dw-i3c-master.h
···
19
19
20
20
struct dw_i3c_dat_entry {
21
21
u8 addr;
22
+
bool is_i2c_addr;
22
23
struct i3c_dev_desc *ibi_dev;
23
24
};
24
25
25
26
struct dw_i3c_master {
26
27
struct i3c_master_controller base;
28
+
struct device *dev;
27
29
u16 maxdevs;
28
30
u16 datstartaddr;
29
31
u32 free_pos;
···
38
36
void __iomem *regs;
39
37
struct reset_control *core_rst;
40
38
struct clk *core_clk;
39
+
struct clk *pclk;
41
40
char version[5];
42
41
char type[5];
43
-
bool ibi_capable;
44
-
42
+
u32 sir_rej_mask;
43
+
bool i2c_slv_prsnt;
44
+
u32 dev_addr;
45
+
u32 i3c_pp_timing;
46
+
u32 i3c_od_timing;
47
+
u32 ext_lcnt_timing;
48
+
u32 bus_free_timing;
49
+
u32 i2c_fm_timing;
50
+
u32 i2c_fmp_timing;
45
51
/*
46
52
* Per-device hardware data, used to manage the device address table
47
53
* (DAT)
+8
drivers/i3c/master/mipi-i3c-hci/core.c
+8
drivers/i3c/master/mipi-i3c-hci/core.c
···
631
631
static int i3c_hci_init(struct i3c_hci *hci)
632
632
{
633
633
u32 regval, offset;
634
+
bool size_in_dwords;
634
635
int ret;
635
636
636
637
/* Validate HCI hardware version */
···
655
654
hci->caps = reg_read(HC_CAPABILITIES);
656
655
DBG("caps = %#x", hci->caps);
657
656
657
+
size_in_dwords = hci->version_major < 1 ||
658
+
(hci->version_major == 1 && hci->version_minor < 1);
659
+
658
660
regval = reg_read(DAT_SECTION);
659
661
offset = FIELD_GET(DAT_TABLE_OFFSET, regval);
660
662
hci->DAT_regs = offset ? hci->base_regs + offset : NULL;
661
663
hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval);
662
664
hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;
665
+
if (size_in_dwords)
666
+
hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size;
663
667
dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n",
664
668
hci->DAT_entries, hci->DAT_entry_size, offset);
665
669
···
673
667
hci->DCT_regs = offset ? hci->base_regs + offset : NULL;
674
668
hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval);
675
669
hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16;
670
+
if (size_in_dwords)
671
+
hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size;
676
672
dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n",
677
673
hci->DCT_entries, hci->DCT_entry_size, offset);
678
674
+22
-22
drivers/i3c/master/mipi-i3c-hci/dma.c
+22
-22
drivers/i3c/master/mipi-i3c-hci/dma.c
···
147
147
unsigned int max_len;
148
148
};
149
149
150
-
static inline u32 lo32(dma_addr_t physaddr)
151
-
{
152
-
return physaddr;
153
-
}
154
-
155
-
static inline u32 hi32(dma_addr_t physaddr)
156
-
{
157
-
/* trickery to avoid compiler warnings on 32-bit build targets */
158
-
if (sizeof(dma_addr_t) > 4) {
159
-
u64 hi = physaddr;
160
-
return hi >> 32;
161
-
}
162
-
return 0;
163
-
}
164
-
165
150
static void hci_dma_cleanup(struct i3c_hci *hci)
166
151
{
167
152
struct hci_rings_data *rings = hci->io_data;
···
250
265
if (!rh->xfer || !rh->resp || !rh->src_xfers)
251
266
goto err_out;
252
267
253
-
rh_reg_write(CMD_RING_BASE_LO, lo32(rh->xfer_dma));
254
-
rh_reg_write(CMD_RING_BASE_HI, hi32(rh->xfer_dma));
255
-
rh_reg_write(RESP_RING_BASE_LO, lo32(rh->resp_dma));
256
-
rh_reg_write(RESP_RING_BASE_HI, hi32(rh->resp_dma));
268
+
rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma));
269
+
rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma));
270
+
rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma));
271
+
rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma));
257
272
258
273
regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);
259
274
rh_reg_write(CR_SETUP, regval);
···
279
294
280
295
rh->ibi_chunk_sz = dma_get_cache_alignment();
281
296
rh->ibi_chunk_sz *= IBI_CHUNK_CACHELINES;
282
-
BUG_ON(rh->ibi_chunk_sz > 256);
297
+
/*
298
+
* Round IBI data chunk size to number of bytes supported by
299
+
* the HW. Chunk size can be 2^n number of DWORDs which is the
300
+
* same as 2^(n+2) bytes, where n is 0..6.
301
+
*/
302
+
rh->ibi_chunk_sz = umax(4, rh->ibi_chunk_sz);
303
+
rh->ibi_chunk_sz = roundup_pow_of_two(rh->ibi_chunk_sz);
304
+
if (rh->ibi_chunk_sz > 256) {
305
+
ret = -EINVAL;
306
+
goto err_out;
307
+
}
283
308
284
309
ibi_status_ring_sz = rh->ibi_status_sz * rh->ibi_status_entries;
285
310
ibi_data_ring_sz = rh->ibi_chunk_sz * rh->ibi_chunks_total;
···
309
314
ret = -ENOMEM;
310
315
goto err_out;
311
316
}
317
+
318
+
rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma));
319
+
rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma));
320
+
rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma));
321
+
rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma));
312
322
313
323
regval = FIELD_PREP(IBI_STATUS_RING_SIZE,
314
324
rh->ibi_status_entries) |
···
404
404
hci_dma_unmap_xfer(hci, xfer_list, i);
405
405
return -ENOMEM;
406
406
}
407
-
*ring_data++ = lo32(xfer->data_dma);
408
-
*ring_data++ = hi32(xfer->data_dma);
407
+
*ring_data++ = lower_32_bits(xfer->data_dma);
408
+
*ring_data++ = upper_32_bits(xfer->data_dma);
409
409
} else {
410
410
*ring_data++ = 0;
411
411
*ring_data++ = 0;
+88
-33
drivers/i3c/master/svc-i3c-master.c
+88
-33
drivers/i3c/master/svc-i3c-master.c
···
790
790
int ret, i;
791
791
792
792
while (true) {
793
-
/* Enter/proceed with DAA */
793
+
/* SVC_I3C_MCTRL_REQUEST_PROC_DAA have two mode, ENTER DAA or PROCESS DAA.
794
+
*
795
+
* ENTER DAA:
796
+
* 1 will issue START, 7E, ENTDAA, and then emits 7E/R to process first target.
797
+
* 2 Stops just before the new Dynamic Address (DA) is to be emitted.
798
+
*
799
+
* PROCESS DAA:
800
+
* 1 The DA is written using MWDATAB or ADDR bits 6:0.
801
+
* 2 ProcessDAA is requested again to write the new address, and then starts the
802
+
* next (START, 7E, ENTDAA) unless marked to STOP; an MSTATUS indicating NACK
803
+
* means DA was not accepted (e.g. parity error). If PROCESSDAA is NACKed on the
804
+
* 7E/R, which means no more Slaves need a DA, then a COMPLETE will be signaled
805
+
* (along with DONE), and a STOP issued automatically.
806
+
*/
794
807
writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA |
795
808
SVC_I3C_MCTRL_TYPE_I3C |
796
809
SVC_I3C_MCTRL_IBIRESP_NACK |
···
820
807
SVC_I3C_MSTATUS_MCTRLDONE(reg),
821
808
1, 1000);
822
809
if (ret)
823
-
return ret;
810
+
break;
824
811
825
812
if (SVC_I3C_MSTATUS_RXPEND(reg)) {
826
813
u8 data[6];
···
832
819
*/
833
820
ret = svc_i3c_master_readb(master, data, 6);
834
821
if (ret)
835
-
return ret;
822
+
break;
836
823
837
824
for (i = 0; i < 6; i++)
838
825
prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i));
···
840
827
/* We do not care about the BCR and DCR yet */
841
828
ret = svc_i3c_master_readb(master, data, 2);
842
829
if (ret)
843
-
return ret;
830
+
break;
844
831
} else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) {
845
832
if (SVC_I3C_MSTATUS_STATE_IDLE(reg) &&
846
833
SVC_I3C_MSTATUS_COMPLETE(reg)) {
···
848
835
* All devices received and acked they dynamic
849
836
* address, this is the natural end of the DAA
850
837
* procedure.
838
+
*
839
+
* Hardware will auto emit STOP at this case.
851
840
*/
852
-
break;
841
+
*count = dev_nb;
842
+
return 0;
843
+
853
844
} else if (SVC_I3C_MSTATUS_NACKED(reg)) {
854
845
/* No I3C devices attached */
855
-
if (dev_nb == 0)
846
+
if (dev_nb == 0) {
847
+
/*
848
+
* Hardware can't treat first NACK for ENTAA as normal
849
+
* COMPLETE. So need manual emit STOP.
850
+
*/
851
+
ret = 0;
852
+
*count = 0;
856
853
break;
854
+
}
857
855
858
856
/*
859
857
* A slave device nacked the address, this is
···
873
849
* answer again immediately and shall ack the
874
850
* address this time.
875
851
*/
876
-
if (prov_id[dev_nb] == nacking_prov_id)
877
-
return -EIO;
852
+
if (prov_id[dev_nb] == nacking_prov_id) {
853
+
ret = -EIO;
854
+
break;
855
+
}
878
856
879
857
dev_nb--;
880
858
nacking_prov_id = prov_id[dev_nb];
···
884
858
885
859
continue;
886
860
} else {
887
-
return -EIO;
861
+
break;
888
862
}
889
863
}
890
864
···
896
870
SVC_I3C_MSTATUS_BETWEEN(reg),
897
871
0, 1000);
898
872
if (ret)
899
-
return ret;
873
+
break;
900
874
901
875
/* Give the slave device a suitable dynamic address */
902
876
ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
903
877
if (ret < 0)
904
-
return ret;
878
+
break;
905
879
906
880
addrs[dev_nb] = ret;
907
881
dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n",
···
911
885
last_addr = addrs[dev_nb++];
912
886
}
913
887
914
-
*count = dev_nb;
915
-
916
-
return 0;
888
+
/* Need manual issue STOP except for Complete condition */
889
+
svc_i3c_master_emit_stop(master);
890
+
return ret;
917
891
}
918
892
919
893
static int svc_i3c_update_ibirules(struct svc_i3c_master *master)
···
987
961
spin_lock_irqsave(&master->xferqueue.lock, flags);
988
962
ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb);
989
963
spin_unlock_irqrestore(&master->xferqueue.lock, flags);
990
-
if (ret) {
991
-
svc_i3c_master_emit_stop(master);
992
-
svc_i3c_master_clear_merrwarn(master);
964
+
965
+
svc_i3c_master_clear_merrwarn(master);
966
+
if (ret)
993
967
goto rpm_out;
994
-
}
995
968
996
969
/* Register all devices who participated to the core */
997
970
for (i = 0; i < dev_nb; i++) {
···
1077
1052
u8 *in, const u8 *out, unsigned int xfer_len,
1078
1053
unsigned int *actual_len, bool continued)
1079
1054
{
1055
+
int retry = 2;
1080
1056
u32 reg;
1081
1057
int ret;
1082
1058
1083
1059
/* clean SVC_I3C_MINT_IBIWON w1c bits */
1084
1060
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
1085
1061
1086
-
writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
1087
-
xfer_type |
1088
-
SVC_I3C_MCTRL_IBIRESP_NACK |
1089
-
SVC_I3C_MCTRL_DIR(rnw) |
1090
-
SVC_I3C_MCTRL_ADDR(addr) |
1091
-
SVC_I3C_MCTRL_RDTERM(*actual_len),
1092
-
master->regs + SVC_I3C_MCTRL);
1093
1062
1094
-
ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1063
+
while (retry--) {
1064
+
writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
1065
+
xfer_type |
1066
+
SVC_I3C_MCTRL_IBIRESP_NACK |
1067
+
SVC_I3C_MCTRL_DIR(rnw) |
1068
+
SVC_I3C_MCTRL_ADDR(addr) |
1069
+
SVC_I3C_MCTRL_RDTERM(*actual_len),
1070
+
master->regs + SVC_I3C_MCTRL);
1071
+
1072
+
ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1095
1073
SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
1096
-
if (ret)
1097
-
goto emit_stop;
1074
+
if (ret)
1075
+
goto emit_stop;
1098
1076
1099
-
if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1100
-
ret = -ENXIO;
1101
-
*actual_len = 0;
1102
-
goto emit_stop;
1077
+
if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1078
+
/*
1079
+
* According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.
1080
+
* If the Controller chooses to start an I3C Message with an I3C Dynamic
1081
+
* Address, then special provisions shall be made because that same I3C
1082
+
* Target may be initiating an IBI or a Controller Role Request. So, one of
1083
+
* three things may happen: (skip 1, 2)
1084
+
*
1085
+
* 3. The Addresses match and the RnW bits also match, and so neither
1086
+
* Controller nor Target will ACK since both are expecting the other side to
1087
+
* provide ACK. As a result, each side might think it had "won" arbitration,
1088
+
* but neither side would continue, as each would subsequently see that the
1089
+
* other did not provide ACK.
1090
+
* ...
1091
+
* For either value of RnW: Due to the NACK, the Controller shall defer the
1092
+
* Private Write or Private Read, and should typically transmit the Target
1093
+
* Address again after a Repeated START (i.e., the next one or any one prior
1094
+
* to a STOP in the Frame). Since the Address Header following a Repeated
1095
+
* START is not arbitrated, the Controller will always win (see Section
1096
+
* 5.1.2.2.4).
1097
+
*/
1098
+
if (retry && addr != 0x7e) {
1099
+
writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN);
1100
+
} else {
1101
+
ret = -ENXIO;
1102
+
*actual_len = 0;
1103
+
goto emit_stop;
1104
+
}
1105
+
} else {
1106
+
break;
1107
+
}
1103
1108
}
1104
1109
1105
1110
/*
···
1376
1321
cmd->addr = ccc->dests[0].addr;
1377
1322
cmd->rnw = ccc->rnw;
1378
1323
cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL;
1379
-
cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data,
1324
+
cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data;
1380
1325
cmd->len = xfer_len;
1381
1326
cmd->actual_len = actual_len;
1382
1327
cmd->continued = false;
+16
include/dt-bindings/i3c/i3c.h
+16
include/dt-bindings/i3c/i3c.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright 2024 NXP
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_I3C_I3C_H
7
+
#define _DT_BINDINGS_I3C_I3C_H
8
+
9
+
#define I2C_FM (1 << 4)
10
+
#define I2C_FM_PLUS (0 << 4)
11
+
12
+
#define I2C_FILTER (0 << 5)
13
+
#define I2C_NO_FILTER_HIGH_FREQUENCY (1 << 5)
14
+
#define I2C_NO_FILTER_LOW_FREQUENCY (2 << 5)
15
+
16
+
#endif