Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'irq-final-for-linus-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-final-for-linus-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (111 commits)
gpio: ab8500: Mark broken
genirq: Remove move_*irq leftovers
genirq: Remove compat code
drivers: Final irq namespace conversion
mn10300: Use generic show_interrupts()
mn10300: Cleanup irq_desc access
mn10300: Convert genirq namespace
frv: Use generic show_interrupts()
frv: Convert genirq namespace
frv: Select GENERIC_HARDIRQS_NO_DEPRECATED
frv: Convert cpu irq_chip to new functions
frv: Convert mb93493 irq_chip to new functions
frv: Convert mb93093 irq_chip to new function
frv: Convert mb93091 irq_chip to new functions
frv: Fix typo from __do_IRQ overhaul
frv: Remove stale irq_chip.end
m68k: Convert irq function namespace
xen: Use new irq_move functions
xen: Cleanup genirq namespace
unicore32: Use generic show_interrupts()
...
+2787
-3782
+1
arch/alpha/Kconfig
+1
arch/alpha/Kconfig
+10
-57
arch/alpha/kernel/irq.c
+10
-57
arch/alpha/kernel/irq.c
···
67
67
}
68
68
#endif /* CONFIG_SMP */
69
69
70
-
int
71
-
show_interrupts(struct seq_file *p, void *v)
70
+
int arch_show_interrupts(struct seq_file *p, int prec)
72
71
{
73
72
int j;
74
-
int irq = *(loff_t *) v;
75
-
struct irqaction * action;
76
-
struct irq_desc *desc;
77
-
unsigned long flags;
78
73
79
74
#ifdef CONFIG_SMP
80
-
if (irq == 0) {
81
-
seq_puts(p, " ");
82
-
for_each_online_cpu(j)
83
-
seq_printf(p, "CPU%d ", j);
84
-
seq_putc(p, '\n');
85
-
}
75
+
seq_puts(p, "IPI: ");
76
+
for_each_online_cpu(j)
77
+
seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
78
+
seq_putc(p, '\n');
86
79
#endif
87
-
88
-
if (irq < ACTUAL_NR_IRQS) {
89
-
desc = irq_to_desc(irq);
90
-
91
-
if (!desc)
92
-
return 0;
93
-
94
-
raw_spin_lock_irqsave(&desc->lock, flags);
95
-
action = desc->action;
96
-
if (!action)
97
-
goto unlock;
98
-
seq_printf(p, "%3d: ", irq);
99
-
#ifndef CONFIG_SMP
100
-
seq_printf(p, "%10u ", kstat_irqs(irq));
101
-
#else
102
-
for_each_online_cpu(j)
103
-
seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j));
104
-
#endif
105
-
seq_printf(p, " %14s", get_irq_desc_chip(desc)->name);
106
-
seq_printf(p, " %c%s",
107
-
(action->flags & IRQF_DISABLED)?'+':' ',
108
-
action->name);
109
-
110
-
for (action=action->next; action; action = action->next) {
111
-
seq_printf(p, ", %c%s",
112
-
(action->flags & IRQF_DISABLED)?'+':' ',
113
-
action->name);
114
-
}
115
-
116
-
seq_putc(p, '\n');
117
-
unlock:
118
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
119
-
} else if (irq == ACTUAL_NR_IRQS) {
120
-
#ifdef CONFIG_SMP
121
-
seq_puts(p, "IPI: ");
122
-
for_each_online_cpu(j)
123
-
seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
124
-
seq_putc(p, '\n');
125
-
#endif
126
-
seq_puts(p, "PMI: ");
127
-
for_each_online_cpu(j)
128
-
seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
129
-
seq_puts(p, " Performance Monitoring\n");
130
-
seq_printf(p, "ERR: %10lu\n", irq_err_count);
131
-
}
80
+
seq_puts(p, "PMI: ");
81
+
for_each_online_cpu(j)
82
+
seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
83
+
seq_puts(p, " Performance Monitoring\n");
84
+
seq_printf(p, "ERR: %10lu\n", irq_err_count);
132
85
return 0;
133
86
}
134
87
+1
-1
arch/alpha/kernel/irq_alpha.c
+1
-1
arch/alpha/kernel/irq_alpha.c
+1
-1
arch/alpha/kernel/irq_i8259.c
+1
-1
arch/alpha/kernel/irq_i8259.c
+1
-1
arch/alpha/kernel/irq_pyxis.c
+1
-1
arch/alpha/kernel/irq_pyxis.c
+1
-1
arch/alpha/kernel/irq_srm.c
+1
-1
arch/alpha/kernel/irq_srm.c
+1
-1
arch/alpha/kernel/sys_alcor.c
+1
-1
arch/alpha/kernel/sys_alcor.c
···
125
125
on while IRQ probing. */
126
126
if (i >= 16+20 && i <= 16+30)
127
127
continue;
128
-
set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
128
+
irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
129
129
irq_set_status_flags(i, IRQ_LEVEL);
130
130
}
131
131
i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
+2
-2
arch/alpha/kernel/sys_cabriolet.c
+2
-2
arch/alpha/kernel/sys_cabriolet.c
+1
-1
arch/alpha/kernel/sys_dp264.c
+1
-1
arch/alpha/kernel/sys_dp264.c
+1
-1
arch/alpha/kernel/sys_eb64p.c
+1
-1
arch/alpha/kernel/sys_eb64p.c
+1
-1
arch/alpha/kernel/sys_eiger.c
+1
-1
arch/alpha/kernel/sys_eiger.c
+5
-5
arch/alpha/kernel/sys_jensen.c
+5
-5
arch/alpha/kernel/sys_jensen.c
···
171
171
{
172
172
init_i8259a_irqs();
173
173
174
-
set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
175
-
set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
176
-
set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
177
-
set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
178
-
set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
174
+
irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
175
+
irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
176
+
irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
177
+
irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
178
+
irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
179
179
180
180
common_init_isa_dma();
181
181
}
+4
-4
arch/alpha/kernel/sys_marvel.c
+4
-4
arch/alpha/kernel/sys_marvel.c
···
276
276
277
277
/* Set up the lsi irqs. */
278
278
for (i = 0; i < 128; ++i) {
279
-
set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
279
+
irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
280
280
irq_set_status_flags(i, IRQ_LEVEL);
281
281
}
282
282
···
290
290
291
291
/* Set up the msi irqs. */
292
292
for (i = 128; i < (128 + 512); ++i) {
293
-
set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
293
+
irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
294
294
irq_set_status_flags(i, IRQ_LEVEL);
295
295
}
296
296
···
308
308
309
309
/* Reserve the legacy irqs. */
310
310
for (i = 0; i < 16; ++i) {
311
-
set_irq_chip_and_handler(i, &marvel_legacy_irq_type,
312
-
handle_level_irq);
311
+
irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
312
+
handle_level_irq);
313
313
}
314
314
315
315
/* Init the io7 irqs. */
+2
-1
arch/alpha/kernel/sys_mikasa.c
+2
-1
arch/alpha/kernel/sys_mikasa.c
+2
-1
arch/alpha/kernel/sys_noritake.c
+2
-1
arch/alpha/kernel/sys_noritake.c
+2
-1
arch/alpha/kernel/sys_rawhide.c
+2
-1
arch/alpha/kernel/sys_rawhide.c
+1
-1
arch/alpha/kernel/sys_rx164.c
+1
-1
arch/alpha/kernel/sys_rx164.c
+2
-2
arch/alpha/kernel/sys_sable.c
+2
-2
arch/alpha/kernel/sys_sable.c
+2
-1
arch/alpha/kernel/sys_takara.c
+2
-1
arch/alpha/kernel/sys_takara.c
+1
-1
arch/alpha/kernel/sys_titan.c
+1
-1
arch/alpha/kernel/sys_titan.c
+6
-6
arch/alpha/kernel/sys_wildfire.c
+6
-6
arch/alpha/kernel/sys_wildfire.c
···
183
183
for (i = 0; i < 16; ++i) {
184
184
if (i == 2)
185
185
continue;
186
-
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
187
-
handle_level_irq);
186
+
irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
187
+
handle_level_irq);
188
188
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
189
189
}
190
190
191
-
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
192
-
handle_level_irq);
191
+
irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
192
+
handle_level_irq);
193
193
irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
194
194
for (i = 40; i < 64; ++i) {
195
-
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
196
-
handle_level_irq);
195
+
irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
196
+
handle_level_irq);
197
197
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
198
198
}
199
199
+1
arch/arm/Kconfig
+1
arch/arm/Kconfig
+7
-8
arch/arm/common/gic.c
+7
-8
arch/arm/common/gic.c
···
213
213
214
214
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
215
215
{
216
-
struct gic_chip_data *chip_data = get_irq_data(irq);
217
-
struct irq_chip *chip = get_irq_chip(irq);
216
+
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
217
+
struct irq_chip *chip = irq_get_chip(irq);
218
218
unsigned int cascade_irq, gic_irq;
219
219
unsigned long status;
220
220
···
257
257
{
258
258
if (gic_nr >= MAX_GIC_NR)
259
259
BUG();
260
-
if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
260
+
if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
261
261
BUG();
262
-
set_irq_chained_handler(irq, gic_handle_cascade_irq);
262
+
irq_set_chained_handler(irq, gic_handle_cascade_irq);
263
263
}
264
264
265
265
static void __init gic_dist_init(struct gic_chip_data *gic,
···
319
319
* Setup the Linux IRQ subsystem.
320
320
*/
321
321
for (i = irq_start; i < irq_limit; i++) {
322
-
set_irq_chip(i, &gic_chip);
323
-
set_irq_chip_data(i, gic);
324
-
set_irq_handler(i, handle_level_irq);
322
+
irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
323
+
irq_set_chip_data(i, gic);
325
324
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
326
325
}
327
326
···
381
382
unsigned long flags;
382
383
383
384
local_irq_save(flags);
384
-
irq_to_desc(irq)->status |= IRQ_NOPROBE;
385
+
irq_set_status_flags(irq, IRQ_NOPROBE);
385
386
gic_unmask_irq(irq_get_irq_data(irq));
386
387
local_irq_restore(flags);
387
388
}
+2
-2
arch/arm/common/it8152.c
+2
-2
arch/arm/common/it8152.c
···
88
88
__raw_writel((0), IT8152_INTC_LDCNIRR);
89
89
90
90
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
91
-
set_irq_chip(irq, &it8152_irq_chip);
92
-
set_irq_handler(irq, handle_level_irq);
91
+
irq_set_chip_and_handler(irq, &it8152_irq_chip,
92
+
handle_level_irq);
93
93
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
94
94
}
95
95
}
+8
-9
arch/arm/common/locomo.c
+8
-9
arch/arm/common/locomo.c
···
140
140
141
141
static void locomo_handler(unsigned int irq, struct irq_desc *desc)
142
142
{
143
-
struct locomo *lchip = get_irq_chip_data(irq);
143
+
struct locomo *lchip = irq_get_chip_data(irq);
144
144
int req, i;
145
145
146
146
/* Acknowledge the parent IRQ */
···
197
197
/*
198
198
* Install handler for IRQ_LOCOMO_HW.
199
199
*/
200
-
set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
201
-
set_irq_chip_data(lchip->irq, lchip);
202
-
set_irq_chained_handler(lchip->irq, locomo_handler);
200
+
irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
201
+
irq_set_chip_data(lchip->irq, lchip);
202
+
irq_set_chained_handler(lchip->irq, locomo_handler);
203
203
204
204
/* Install handlers for IRQ_LOCOMO_* */
205
205
for ( ; irq <= lchip->irq_base + 3; irq++) {
206
-
set_irq_chip(irq, &locomo_chip);
207
-
set_irq_chip_data(irq, lchip);
208
-
set_irq_handler(irq, handle_level_irq);
206
+
irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
207
+
irq_set_chip_data(irq, lchip);
209
208
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
210
209
}
211
210
}
···
475
476
device_for_each_child(lchip->dev, NULL, locomo_remove_child);
476
477
477
478
if (lchip->irq != NO_IRQ) {
478
-
set_irq_chained_handler(lchip->irq, NULL);
479
-
set_irq_data(lchip->irq, NULL);
479
+
irq_set_chained_handler(lchip->irq, NULL);
480
+
irq_set_handler_data(lchip->irq, NULL);
480
481
}
481
482
482
483
iounmap(lchip->base);
+12
-12
arch/arm/common/sa1111.c
+12
-12
arch/arm/common/sa1111.c
···
202
202
sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
203
203
{
204
204
unsigned int stat0, stat1, i;
205
-
struct sa1111 *sachip = get_irq_data(irq);
205
+
struct sa1111 *sachip = irq_get_handler_data(irq);
206
206
void __iomem *mapbase = sachip->base + SA1111_INTC;
207
207
208
208
stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
···
472
472
sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
473
473
474
474
for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
475
-
set_irq_chip(irq, &sa1111_low_chip);
476
-
set_irq_chip_data(irq, sachip);
477
-
set_irq_handler(irq, handle_edge_irq);
475
+
irq_set_chip_and_handler(irq, &sa1111_low_chip,
476
+
handle_edge_irq);
477
+
irq_set_chip_data(irq, sachip);
478
478
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
479
479
}
480
480
481
481
for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
482
-
set_irq_chip(irq, &sa1111_high_chip);
483
-
set_irq_chip_data(irq, sachip);
484
-
set_irq_handler(irq, handle_edge_irq);
482
+
irq_set_chip_and_handler(irq, &sa1111_high_chip,
483
+
handle_edge_irq);
484
+
irq_set_chip_data(irq, sachip);
485
485
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
486
486
}
487
487
488
488
/*
489
489
* Register SA1111 interrupt
490
490
*/
491
-
set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
492
-
set_irq_data(sachip->irq, sachip);
493
-
set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
491
+
irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
492
+
irq_set_handler_data(sachip->irq, sachip);
493
+
irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
494
494
}
495
495
496
496
/*
···
815
815
clk_disable(sachip->clk);
816
816
817
817
if (sachip->irq != NO_IRQ) {
818
-
set_irq_chained_handler(sachip->irq, NULL);
819
-
set_irq_data(sachip->irq, NULL);
818
+
irq_set_chained_handler(sachip->irq, NULL);
819
+
irq_set_handler_data(sachip->irq, NULL);
820
820
821
821
release_mem_region(sachip->phys + SA1111_INTC, 512);
822
822
}
+3
-3
arch/arm/common/vic.c
+3
-3
arch/arm/common/vic.c
···
305
305
if (vic_sources & (1 << i)) {
306
306
unsigned int irq = irq_start + i;
307
307
308
-
set_irq_chip(irq, &vic_chip);
309
-
set_irq_chip_data(irq, base);
310
-
set_irq_handler(irq, handle_level_irq);
308
+
irq_set_chip_and_handler(irq, &vic_chip,
309
+
handle_level_irq);
310
+
irq_set_chip_data(irq, base);
311
311
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
312
312
}
313
313
}
-8
arch/arm/include/asm/hw_irq.h
-8
arch/arm/include/asm/hw_irq.h
···
10
10
irq_err_count++;
11
11
}
12
12
13
-
/*
14
-
* Obsolete inline function for calling irq descriptor handlers.
15
-
*/
16
-
static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
17
-
{
18
-
desc->handle_irq(irq, desc);
19
-
}
20
-
21
13
void set_irq_flags(unsigned int irq, unsigned int flags);
22
14
23
15
#define IRQF_VALID (1 << 0)
-25
arch/arm/kernel/bios32.c
-25
arch/arm/kernel/bios32.c
···
159
159
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
160
160
161
161
/*
162
-
* Same as above. The PrPMC800 carrier board for the PrPMC1100
163
-
* card maps the host-bridge @ 00:01:00 for some reason and it
164
-
* ends up getting scanned. Note that we only want to do this
165
-
* fixup when we find the IXP4xx on a PrPMC system, which is why
166
-
* we check the machine type. We could be running on a board
167
-
* with an IXP4xx target device and we don't want to kill the
168
-
* resources in that case.
169
-
*/
170
-
static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
171
-
{
172
-
int i;
173
-
174
-
if (machine_is_prpmc1100()) {
175
-
dev->class &= 0xff;
176
-
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
177
-
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
178
-
dev->resource[i].start = 0;
179
-
dev->resource[i].end = 0;
180
-
dev->resource[i].flags = 0;
181
-
}
182
-
}
183
-
}
184
-
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100);
185
-
186
-
/*
187
162
* PCI IDE controllers use non-standard I/O port decoding, respect it.
188
163
*/
189
164
static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
+3
-3
arch/arm/kernel/ecard.c
+3
-3
arch/arm/kernel/ecard.c
···
1043
1043
*/
1044
1044
if (slot < 8) {
1045
1045
ec->irq = 32 + slot;
1046
-
set_irq_chip(ec->irq, &ecard_chip);
1047
-
set_irq_handler(ec->irq, handle_level_irq);
1046
+
irq_set_chip_and_handler(ec->irq, &ecard_chip,
1047
+
handle_level_irq);
1048
1048
set_irq_flags(ec->irq, IRQF_VALID);
1049
1049
}
1050
1050
···
1103
1103
1104
1104
irqhw = ecard_probeirqhw();
1105
1105
1106
-
set_irq_chained_handler(IRQ_EXPANSIONCARD,
1106
+
irq_set_chained_handler(IRQ_EXPANSIONCARD,
1107
1107
irqhw ? ecard_irqexp_handler : ecard_irq_handler);
1108
1108
1109
1109
ecard_proc_init();
+11
-59
arch/arm/kernel/irq.c
+11
-59
arch/arm/kernel/irq.c
···
51
51
52
52
unsigned long irq_err_count;
53
53
54
-
int show_interrupts(struct seq_file *p, void *v)
54
+
int arch_show_interrupts(struct seq_file *p, int prec)
55
55
{
56
-
int i = *(loff_t *) v, cpu;
57
-
struct irq_desc *desc;
58
-
struct irqaction * action;
59
-
unsigned long flags;
60
-
int prec, n;
61
-
62
-
for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++)
63
-
n *= 10;
64
-
65
-
#ifdef CONFIG_SMP
66
-
if (prec < 4)
67
-
prec = 4;
68
-
#endif
69
-
70
-
if (i == 0) {
71
-
char cpuname[12];
72
-
73
-
seq_printf(p, "%*s ", prec, "");
74
-
for_each_present_cpu(cpu) {
75
-
sprintf(cpuname, "CPU%d", cpu);
76
-
seq_printf(p, " %10s", cpuname);
77
-
}
78
-
seq_putc(p, '\n');
79
-
}
80
-
81
-
if (i < nr_irqs) {
82
-
desc = irq_to_desc(i);
83
-
raw_spin_lock_irqsave(&desc->lock, flags);
84
-
action = desc->action;
85
-
if (!action)
86
-
goto unlock;
87
-
88
-
seq_printf(p, "%*d: ", prec, i);
89
-
for_each_present_cpu(cpu)
90
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
91
-
seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
92
-
seq_printf(p, " %s", action->name);
93
-
for (action = action->next; action; action = action->next)
94
-
seq_printf(p, ", %s", action->name);
95
-
96
-
seq_putc(p, '\n');
97
-
unlock:
98
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
99
-
} else if (i == nr_irqs) {
100
56
#ifdef CONFIG_FIQ
101
-
show_fiq_list(p, prec);
57
+
show_fiq_list(p, prec);
102
58
#endif
103
59
#ifdef CONFIG_SMP
104
-
show_ipi_list(p, prec);
60
+
show_ipi_list(p, prec);
105
61
#endif
106
62
#ifdef CONFIG_LOCAL_TIMERS
107
-
show_local_irqs(p, prec);
63
+
show_local_irqs(p, prec);
108
64
#endif
109
-
seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
110
-
}
65
+
seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
111
66
return 0;
112
67
}
113
68
···
99
144
100
145
void set_irq_flags(unsigned int irq, unsigned int iflags)
101
146
{
102
-
struct irq_desc *desc;
103
-
unsigned long flags;
147
+
unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
104
148
105
149
if (irq >= nr_irqs) {
106
150
printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
107
151
return;
108
152
}
109
153
110
-
desc = irq_to_desc(irq);
111
-
raw_spin_lock_irqsave(&desc->lock, flags);
112
-
desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
113
154
if (iflags & IRQF_VALID)
114
-
desc->status &= ~IRQ_NOREQUEST;
155
+
clr |= IRQ_NOREQUEST;
115
156
if (iflags & IRQF_PROBE)
116
-
desc->status &= ~IRQ_NOPROBE;
157
+
clr |= IRQ_NOPROBE;
117
158
if (!(iflags & IRQF_NOAUTOEN))
118
-
desc->status &= ~IRQ_NOAUTOEN;
119
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
159
+
clr |= IRQ_NOAUTOEN;
160
+
/* Order is clear bits in "clr" then set bits in "set" */
161
+
irq_modify_status(irq, clr, set & ~clr);
120
162
}
121
163
122
164
void __init init_IRQ(void)
+3
-3
arch/arm/mach-at91/at91cap9_devices.c
+3
-3
arch/arm/mach-at91/at91cap9_devices.c
···
72
72
return;
73
73
74
74
if (cpu_is_at91cap9_revB())
75
-
set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
75
+
irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
76
76
77
77
/* Enable VBus control for UHP ports */
78
78
for (i = 0; i < data->ports; i++) {
···
157
157
void __init at91_add_device_usba(struct usba_platform_data *data)
158
158
{
159
159
if (cpu_is_at91cap9_revB()) {
160
-
set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
160
+
irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
161
161
at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
162
162
AT91_MATRIX_UDPHS_BYPASS_LOCK);
163
163
}
···
861
861
return;
862
862
863
863
if (cpu_is_at91cap9_revB())
864
-
set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
864
+
irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
865
865
866
866
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
867
867
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
+15
-28
arch/arm/mach-at91/gpio.c
+15
-28
arch/arm/mach-at91/gpio.c
···
287
287
else
288
288
wakeups[bank] &= ~mask;
289
289
290
-
set_irq_wake(gpio_chip[bank].bank->id, state);
290
+
irq_set_irq_wake(gpio_chip[bank].bank->id, state);
291
291
292
292
return 0;
293
293
}
···
375
375
376
376
static struct irq_chip gpio_irqchip = {
377
377
.name = "GPIO",
378
+
.irq_disable = gpio_irq_mask,
378
379
.irq_mask = gpio_irq_mask,
379
380
.irq_unmask = gpio_irq_unmask,
380
381
.irq_set_type = gpio_irq_type,
···
385
384
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
386
385
{
387
386
unsigned pin;
388
-
struct irq_desc *gpio;
389
-
struct at91_gpio_chip *at91_gpio;
390
-
void __iomem *pio;
387
+
struct irq_data *idata = irq_desc_get_irq_data(desc);
388
+
struct irq_chip *chip = irq_data_get_irq_chip(idata);
389
+
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
390
+
void __iomem *pio = at91_gpio->regbase;
391
391
u32 isr;
392
392
393
-
at91_gpio = get_irq_chip_data(irq);
394
-
pio = at91_gpio->regbase;
395
-
396
393
/* temporarily mask (level sensitive) parent IRQ */
397
-
desc->irq_data.chip->irq_ack(&desc->irq_data);
394
+
chip->irq_ack(idata);
398
395
for (;;) {
399
396
/* Reading ISR acks pending (edge triggered) GPIO interrupts.
400
397
* When there none are pending, we're finished unless we need
···
408
409
}
409
410
410
411
pin = at91_gpio->chip.base;
411
-
gpio = &irq_desc[pin];
412
412
413
413
while (isr) {
414
-
if (isr & 1) {
415
-
if (unlikely(gpio->depth)) {
416
-
/*
417
-
* The core ARM interrupt handler lazily disables IRQs so
418
-
* another IRQ must be generated before it actually gets
419
-
* here to be disabled on the GPIO controller.
420
-
*/
421
-
gpio_irq_mask(irq_get_irq_data(pin));
422
-
}
423
-
else
424
-
generic_handle_irq(pin);
425
-
}
414
+
if (isr & 1)
415
+
generic_handle_irq(pin);
426
416
pin++;
427
-
gpio++;
428
417
isr >>= 1;
429
418
}
430
419
}
431
-
desc->irq_data.chip->irq_unmask(&desc->irq_data);
420
+
chip->irq_unmask(idata);
432
421
/* now it may re-trigger */
433
422
}
434
423
···
505
518
__raw_writel(~0, this->regbase + PIO_IDR);
506
519
507
520
for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
508
-
lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
521
+
irq_set_lockdep_class(pin, &gpio_lock_class);
509
522
510
523
/*
511
524
* Can use the "simple" and not "edge" handler since it's
512
525
* shorter, and the AIC handles interrupts sanely.
513
526
*/
514
-
set_irq_chip(pin, &gpio_irqchip);
515
-
set_irq_handler(pin, handle_simple_irq);
527
+
irq_set_chip_and_handler(pin, &gpio_irqchip,
528
+
handle_simple_irq);
516
529
set_irq_flags(pin, IRQF_VALID);
517
530
}
518
531
···
523
536
if (prev && prev->next == this)
524
537
continue;
525
538
526
-
set_irq_chip_data(id, this);
527
-
set_irq_chained_handler(id, gpio_irq_handler);
539
+
irq_set_chip_data(id, this);
540
+
irq_set_chained_handler(id, gpio_irq_handler);
528
541
}
529
542
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
530
543
}
+1
-1
arch/arm/mach-at91/include/mach/at572d940hf.h
+1
-1
arch/arm/mach-at91/include/mach/at572d940hf.h
···
89
89
/*
90
90
* System Peripherals (offset from AT91_BASE_SYS)
91
91
*/
92
-
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
92
+
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
93
93
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94
94
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95
95
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+1
-2
arch/arm/mach-at91/irq.c
+1
-2
arch/arm/mach-at91/irq.c
···
143
143
/* Active Low interrupt, with the specified priority */
144
144
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
145
145
146
-
set_irq_chip(i, &at91_aic_chip);
147
-
set_irq_handler(i, handle_level_irq);
146
+
irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
148
147
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
149
148
150
149
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
+5
-5
arch/arm/mach-bcmring/irq.c
+5
-5
arch/arm/mach-bcmring/irq.c
···
93
93
unsigned int i;
94
94
for (i = 0; i < 32; i++) {
95
95
unsigned int irq = irq_start + i;
96
-
set_irq_chip(irq, chip);
97
-
set_irq_chip_data(irq, base);
96
+
irq_set_chip(irq, chip);
97
+
irq_set_chip_data(irq, base);
98
98
99
99
if (vic_sources & (1 << i)) {
100
-
set_irq_handler(irq, handle_level_irq);
100
+
irq_set_handler(irq, handle_level_irq);
101
101
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
102
102
}
103
103
}
···
119
119
120
120
/* special cases */
121
121
if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
122
-
set_irq_handler(IRQ_GPIO0, handle_simple_irq);
122
+
irq_set_handler(IRQ_GPIO0, handle_simple_irq);
123
123
}
124
124
if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
125
-
set_irq_handler(IRQ_GPIO1, handle_simple_irq);
125
+
irq_set_handler(IRQ_GPIO1, handle_simple_irq);
126
126
}
127
127
}
+4
-4
arch/arm/mach-clps711x/irq.c
+4
-4
arch/arm/mach-clps711x/irq.c
···
112
112
113
113
for (i = 0; i < NR_IRQS; i++) {
114
114
if (INT1_IRQS & (1 << i)) {
115
-
set_irq_handler(i, handle_level_irq);
116
-
set_irq_chip(i, &int1_chip);
115
+
irq_set_chip_and_handler(i, &int1_chip,
116
+
handle_level_irq);
117
117
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
118
118
}
119
119
if (INT2_IRQS & (1 << i)) {
120
-
set_irq_handler(i, handle_level_irq);
121
-
set_irq_chip(i, &int2_chip);
120
+
irq_set_chip_and_handler(i, &int2_chip,
121
+
handle_level_irq);
122
122
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123
123
}
124
124
}
+2
-2
arch/arm/mach-davinci/cp_intc.c
+2
-2
arch/arm/mach-davinci/cp_intc.c
···
167
167
168
168
/* Set up genirq dispatching for cp_intc */
169
169
for (i = 0; i < num_irq; i++) {
170
-
set_irq_chip(i, &cp_intc_irq_chip);
170
+
irq_set_chip(i, &cp_intc_irq_chip);
171
171
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
172
-
set_irq_handler(i, handle_edge_irq);
172
+
irq_set_handler(i, handle_edge_irq);
173
173
}
174
174
175
175
/* Enable global interrupt */
+20
-29
arch/arm/mach-davinci/gpio.c
+20
-29
arch/arm/mach-davinci/gpio.c
···
62
62
{
63
63
struct davinci_gpio_regs __iomem *g;
64
64
65
-
g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
65
+
g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
66
66
67
67
return g;
68
68
}
···
208
208
static void gpio_irq_disable(struct irq_data *d)
209
209
{
210
210
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
211
-
u32 mask = (u32) irq_data_get_irq_data(d);
211
+
u32 mask = (u32) irq_data_get_irq_handler_data(d);
212
212
213
213
__raw_writel(mask, &g->clr_falling);
214
214
__raw_writel(mask, &g->clr_rising);
···
217
217
static void gpio_irq_enable(struct irq_data *d)
218
218
{
219
219
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
220
-
u32 mask = (u32) irq_data_get_irq_data(d);
221
-
unsigned status = irq_desc[d->irq].status;
220
+
u32 mask = (u32) irq_data_get_irq_handler_data(d);
221
+
unsigned status = irqd_get_trigger_type(d);
222
222
223
223
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224
224
if (!status)
···
233
233
static int gpio_irq_type(struct irq_data *d, unsigned trigger)
234
234
{
235
235
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
236
-
u32 mask = (u32) irq_data_get_irq_data(d);
236
+
u32 mask = (u32) irq_data_get_irq_handler_data(d);
237
237
238
238
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
239
239
return -EINVAL;
240
240
241
-
irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
242
-
irq_desc[d->irq].status |= trigger;
243
-
244
-
/* don't enable the IRQ if it's currently disabled */
245
-
if (irq_desc[d->irq].depth == 0) {
246
-
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
247
-
? &g->set_falling : &g->clr_falling);
248
-
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
249
-
? &g->set_rising : &g->clr_rising);
250
-
}
251
241
return 0;
252
242
}
253
243
···
246
256
.irq_enable = gpio_irq_enable,
247
257
.irq_disable = gpio_irq_disable,
248
258
.irq_set_type = gpio_irq_type,
259
+
.flags = IRQCHIP_SET_TYPE_MASKED,
249
260
};
250
261
251
262
static void
···
276
285
status >>= 16;
277
286
278
287
/* now demux them to the right lowlevel handler */
279
-
n = (int)get_irq_data(irq);
288
+
n = (int)irq_get_handler_data(irq);
280
289
while (status) {
281
290
res = ffs(status);
282
291
n += res;
···
314
323
static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
315
324
{
316
325
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
317
-
u32 mask = (u32) irq_data_get_irq_data(d);
326
+
u32 mask = (u32) irq_data_get_irq_handler_data(d);
318
327
319
328
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
320
329
return -EINVAL;
···
386
395
387
396
/* AINTC handles mask/unmask; GPIO handles triggering */
388
397
irq = bank_irq;
389
-
gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
398
+
gpio_irqchip_unbanked = *irq_get_chip(irq);
390
399
gpio_irqchip_unbanked.name = "GPIO-AINTC";
391
400
gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
392
401
···
397
406
398
407
/* set the direct IRQs up to use that irqchip */
399
408
for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
400
-
set_irq_chip(irq, &gpio_irqchip_unbanked);
401
-
set_irq_data(irq, (void *) __gpio_mask(gpio));
402
-
set_irq_chip_data(irq, (__force void *) g);
403
-
irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
409
+
irq_set_chip(irq, &gpio_irqchip_unbanked);
410
+
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
411
+
irq_set_chip_data(irq, (__force void *)g);
412
+
irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
404
413
}
405
414
406
415
goto done;
···
421
430
__raw_writel(~0, &g->clr_rising);
422
431
423
432
/* set up all irqs in this bank */
424
-
set_irq_chained_handler(bank_irq, gpio_irq_handler);
425
-
set_irq_chip_data(bank_irq, (__force void *) g);
426
-
set_irq_data(bank_irq, (void *) irq);
433
+
irq_set_chained_handler(bank_irq, gpio_irq_handler);
434
+
irq_set_chip_data(bank_irq, (__force void *)g);
435
+
irq_set_handler_data(bank_irq, (void *)irq);
427
436
428
437
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
429
-
set_irq_chip(irq, &gpio_irqchip);
430
-
set_irq_chip_data(irq, (__force void *) g);
431
-
set_irq_data(irq, (void *) __gpio_mask(gpio));
432
-
set_irq_handler(irq, handle_simple_irq);
438
+
irq_set_chip(irq, &gpio_irqchip);
439
+
irq_set_chip_data(irq, (__force void *)g);
440
+
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
441
+
irq_set_handler(irq, handle_simple_irq);
433
442
set_irq_flags(irq, IRQF_VALID);
434
443
}
435
444
+3
-3
arch/arm/mach-davinci/irq.c
+3
-3
arch/arm/mach-davinci/irq.c
···
154
154
155
155
/* set up genirq dispatch for ARM INTC */
156
156
for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
157
-
set_irq_chip(i, &davinci_irq_chip_0);
157
+
irq_set_chip(i, &davinci_irq_chip_0);
158
158
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
159
159
if (i != IRQ_TINT1_TINT34)
160
-
set_irq_handler(i, handle_edge_irq);
160
+
irq_set_handler(i, handle_edge_irq);
161
161
else
162
-
set_irq_handler(i, handle_level_irq);
162
+
irq_set_handler(i, handle_level_irq);
163
163
}
164
164
}
+1
-1
arch/arm/mach-dove/include/mach/dove.h
+1
-1
arch/arm/mach-dove/include/mach/dove.h
···
136
136
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
137
137
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
138
138
#define DOVE_NAND_GPIO_EN (1 << 0)
139
-
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
139
+
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
140
140
#define DOVE_SPI_GPIO_SEL (1 << 5)
141
141
#define DOVE_UART1_GPIO_SEL (1 << 4)
142
142
#define DOVE_AU1_GPIO_SEL (1 << 3)
+9
-11
arch/arm/mach-dove/irq.c
+9
-11
arch/arm/mach-dove/irq.c
···
86
86
if (!(cause & (1 << irq)))
87
87
continue;
88
88
irq = pmu_to_irq(irq);
89
-
desc = irq_desc + irq;
90
-
desc_handle_irq(irq, desc);
89
+
generic_handle_irq(irq);
91
90
}
92
91
}
93
92
···
102
103
*/
103
104
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
104
105
IRQ_DOVE_GPIO_START);
105
-
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
106
-
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
107
-
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
108
-
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
106
+
irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
107
+
irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
108
+
irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
109
+
irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
109
110
110
111
orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
111
112
IRQ_DOVE_GPIO_START + 32);
112
-
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
113
+
irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
113
114
114
115
orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
115
116
IRQ_DOVE_GPIO_START + 64);
···
121
122
writel(0, PMU_INTERRUPT_CAUSE);
122
123
123
124
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
124
-
set_irq_chip(i, &pmu_irq_chip);
125
-
set_irq_handler(i, handle_level_irq);
126
-
irq_desc[i].status |= IRQ_LEVEL;
125
+
irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
126
+
irq_set_status_flags(i, IRQ_LEVEL);
127
127
set_irq_flags(i, IRQF_VALID);
128
128
}
129
-
set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
129
+
irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
130
130
}
-3
arch/arm/mach-dove/mpp.c
-3
arch/arm/mach-dove/mpp.c
+2
-2
arch/arm/mach-ebsa110/core.c
+2
-2
arch/arm/mach-ebsa110/core.c
···
66
66
local_irq_restore(flags);
67
67
68
68
for (irq = 0; irq < NR_IRQS; irq++) {
69
-
set_irq_chip(irq, &ebsa110_irq_chip);
70
-
set_irq_handler(irq, handle_level_irq);
69
+
irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
70
+
handle_level_irq);
71
71
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
72
72
}
73
73
}
+30
-22
arch/arm/mach-ep93xx/gpio.c
+30
-22
arch/arm/mach-ep93xx/gpio.c
···
117
117
int port = line >> 3;
118
118
int port_mask = 1 << (line & 7);
119
119
120
-
if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
120
+
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
121
121
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
122
122
ep93xx_gpio_update_int_params(port);
123
123
}
···
131
131
int port = line >> 3;
132
132
int port_mask = 1 << (line & 7);
133
133
134
-
if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
134
+
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
135
135
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
136
136
137
137
gpio_int_unmasked[port] &= ~port_mask;
···
165
165
*/
166
166
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
167
167
{
168
-
struct irq_desc *desc = irq_desc + d->irq;
169
168
const int gpio = irq_to_gpio(d->irq);
170
169
const int port = gpio >> 3;
171
170
const int port_mask = 1 << (gpio & 7);
171
+
irq_flow_handler_t handler;
172
172
173
173
gpio_direction_input(gpio);
174
174
···
176
176
case IRQ_TYPE_EDGE_RISING:
177
177
gpio_int_type1[port] |= port_mask;
178
178
gpio_int_type2[port] |= port_mask;
179
-
desc->handle_irq = handle_edge_irq;
179
+
handler = handle_edge_irq;
180
180
break;
181
181
case IRQ_TYPE_EDGE_FALLING:
182
182
gpio_int_type1[port] |= port_mask;
183
183
gpio_int_type2[port] &= ~port_mask;
184
-
desc->handle_irq = handle_edge_irq;
184
+
handler = handle_edge_irq;
185
185
break;
186
186
case IRQ_TYPE_LEVEL_HIGH:
187
187
gpio_int_type1[port] &= ~port_mask;
188
188
gpio_int_type2[port] |= port_mask;
189
-
desc->handle_irq = handle_level_irq;
189
+
handler = handle_level_irq;
190
190
break;
191
191
case IRQ_TYPE_LEVEL_LOW:
192
192
gpio_int_type1[port] &= ~port_mask;
193
193
gpio_int_type2[port] &= ~port_mask;
194
-
desc->handle_irq = handle_level_irq;
194
+
handler = handle_level_irq;
195
195
break;
196
196
case IRQ_TYPE_EDGE_BOTH:
197
197
gpio_int_type1[port] |= port_mask;
···
200
200
gpio_int_type2[port] &= ~port_mask; /* falling */
201
201
else
202
202
gpio_int_type2[port] |= port_mask; /* rising */
203
-
desc->handle_irq = handle_edge_irq;
203
+
handler = handle_edge_irq;
204
204
break;
205
205
default:
206
206
pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
207
207
return -EINVAL;
208
208
}
209
209
210
-
gpio_int_enabled[port] |= port_mask;
210
+
__irq_set_handler_locked(d->irq, handler);
211
211
212
-
desc->status &= ~IRQ_TYPE_SENSE_MASK;
213
-
desc->status |= type & IRQ_TYPE_SENSE_MASK;
212
+
gpio_int_enabled[port] |= port_mask;
214
213
215
214
ep93xx_gpio_update_int_params(port);
216
215
···
231
232
232
233
for (gpio_irq = gpio_to_irq(0);
233
234
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
234
-
set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
235
-
set_irq_handler(gpio_irq, handle_level_irq);
235
+
irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
236
+
handle_level_irq);
236
237
set_irq_flags(gpio_irq, IRQF_VALID);
237
238
}
238
239
239
-
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
240
-
set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
241
-
set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
242
-
set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
243
-
set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
244
-
set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
245
-
set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
246
-
set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
247
-
set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
240
+
irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
241
+
ep93xx_gpio_ab_irq_handler);
242
+
irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
243
+
ep93xx_gpio_f_irq_handler);
244
+
irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
245
+
ep93xx_gpio_f_irq_handler);
246
+
irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
247
+
ep93xx_gpio_f_irq_handler);
248
+
irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
249
+
ep93xx_gpio_f_irq_handler);
250
+
irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
251
+
ep93xx_gpio_f_irq_handler);
252
+
irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
253
+
ep93xx_gpio_f_irq_handler);
254
+
irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
255
+
ep93xx_gpio_f_irq_handler);
256
+
irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
257
+
ep93xx_gpio_f_irq_handler);
248
258
}
249
259
250
260
+6
-7
arch/arm/mach-exynos4/irq-combiner.c
+6
-7
arch/arm/mach-exynos4/irq-combiner.c
···
54
54
55
55
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56
56
{
57
-
struct combiner_chip_data *chip_data = get_irq_data(irq);
58
-
struct irq_chip *chip = get_irq_chip(irq);
57
+
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58
+
struct irq_chip *chip = irq_get_chip(irq);
59
59
unsigned int cascade_irq, combiner_irq;
60
60
unsigned long status;
61
61
···
93
93
{
94
94
if (combiner_nr >= MAX_COMBINER_NR)
95
95
BUG();
96
-
if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
96
+
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
97
97
BUG();
98
-
set_irq_chained_handler(irq, combiner_handle_cascade_irq);
98
+
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
99
99
}
100
100
101
101
void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
···
119
119
120
120
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
121
121
+ MAX_IRQ_IN_COMBINER; i++) {
122
-
set_irq_chip(i, &combiner_chip);
123
-
set_irq_chip_data(i, &combiner_data[combiner_nr]);
124
-
set_irq_handler(i, handle_level_irq);
122
+
irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
123
+
irq_set_chip_data(i, &combiner_data[combiner_nr]);
125
124
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126
125
}
127
126
}
+8
-7
arch/arm/mach-exynos4/irq-eint.c
+8
-7
arch/arm/mach-exynos4/irq-eint.c
···
190
190
191
191
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192
192
{
193
-
u32 *irq_data = get_irq_data(irq);
194
-
struct irq_chip *chip = get_irq_chip(irq);
193
+
u32 *irq_data = irq_get_handler_data(irq);
194
+
struct irq_chip *chip = irq_get_chip(irq);
195
195
196
196
chip->irq_mask(&desc->irq_data);
197
197
···
208
208
int irq;
209
209
210
210
for (irq = 0 ; irq <= 31 ; irq++) {
211
-
set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
212
-
set_irq_handler(IRQ_EINT(irq), handle_level_irq);
211
+
irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
212
+
handle_level_irq);
213
213
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214
214
}
215
215
216
-
set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
216
+
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
217
217
218
218
for (irq = 0 ; irq <= 15 ; irq++) {
219
219
eint0_15_data[irq] = IRQ_EINT(irq);
220
220
221
-
set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
222
-
set_irq_chained_handler(exynos4_get_irq_nr(irq),
221
+
irq_set_handler_data(exynos4_get_irq_nr(irq),
222
+
&eint0_15_data[irq]);
223
+
irq_set_chained_handler(exynos4_get_irq_nr(irq),
223
224
exynos4_irq_eint0_15);
224
225
}
225
226
+1
-2
arch/arm/mach-footbridge/common.c
+1
-2
arch/arm/mach-footbridge/common.c
···
102
102
*CSR_FIQ_DISABLE = -1;
103
103
104
104
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
105
-
set_irq_chip(irq, &fb_chip);
106
-
set_irq_handler(irq, handle_level_irq);
105
+
irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
107
106
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
108
107
}
109
108
}
+1
-1
arch/arm/mach-footbridge/dc21285-timer.c
+1
-1
arch/arm/mach-footbridge/dc21285-timer.c
+5
-5
arch/arm/mach-footbridge/isa-irq.c
+5
-5
arch/arm/mach-footbridge/isa-irq.c
···
151
151
152
152
if (host_irq != (unsigned int)-1) {
153
153
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
154
-
set_irq_chip(irq, &isa_lo_chip);
155
-
set_irq_handler(irq, handle_level_irq);
154
+
irq_set_chip_and_handler(irq, &isa_lo_chip,
155
+
handle_level_irq);
156
156
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
157
157
}
158
158
159
159
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
160
-
set_irq_chip(irq, &isa_hi_chip);
161
-
set_irq_handler(irq, handle_level_irq);
160
+
irq_set_chip_and_handler(irq, &isa_hi_chip,
161
+
handle_level_irq);
162
162
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
163
163
}
164
164
···
166
166
request_resource(&ioport_resource, &pic2_resource);
167
167
setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
168
168
169
-
set_irq_chained_handler(host_irq, isa_irq_handler);
169
+
irq_set_chained_handler(host_irq, isa_irq_handler);
170
170
171
171
/*
172
172
* On the NetWinder, don't automatically
+6
-8
arch/arm/mach-gemini/gpio.c
+6
-8
arch/arm/mach-gemini/gpio.c
···
127
127
128
128
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
129
129
{
130
+
unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
130
131
unsigned int gpio_irq_no, irq_stat;
131
-
unsigned int port = (unsigned int)get_irq_data(irq);
132
132
133
133
irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
134
134
···
138
138
if ((irq_stat & 1) == 0)
139
139
continue;
140
140
141
-
BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
142
-
irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
143
-
&irq_desc[gpio_irq_no]);
141
+
generic_handle_irq(gpio_irq_no);
144
142
}
145
143
}
146
144
···
217
219
218
220
for (j = GPIO_IRQ_BASE + i * 32;
219
221
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
220
-
set_irq_chip(j, &gpio_irq_chip);
221
-
set_irq_handler(j, handle_edge_irq);
222
+
irq_set_chip_and_handler(j, &gpio_irq_chip,
223
+
handle_edge_irq);
222
224
set_irq_flags(j, IRQF_VALID);
223
225
}
224
226
225
-
set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
226
-
set_irq_data(IRQ_GPIO(i), (void *)i);
227
+
irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
228
+
irq_set_handler_data(IRQ_GPIO(i), (void *)i);
227
229
}
228
230
229
231
BUG_ON(gpiochip_add(&gemini_gpio_chip));
+3
-3
arch/arm/mach-gemini/irq.c
+3
-3
arch/arm/mach-gemini/irq.c
···
81
81
request_resource(&iomem_resource, &irq_resource);
82
82
83
83
for (i = 0; i < NR_IRQS; i++) {
84
-
set_irq_chip(i, &gemini_irq_chip);
84
+
irq_set_chip(i, &gemini_irq_chip);
85
85
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
86
-
set_irq_handler(i, handle_edge_irq);
86
+
irq_set_handler(i, handle_edge_irq);
87
87
mode |= 1 << i;
88
88
level |= 1 << i;
89
89
} else {
90
-
set_irq_handler(i, handle_level_irq);
90
+
irq_set_handler(i, handle_level_irq);
91
91
}
92
92
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
93
93
}
+11
-11
arch/arm/mach-h720x/common.c
+11
-11
arch/arm/mach-h720x/common.c
···
199
199
200
200
/* Initialize global IRQ's, fast path */
201
201
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
202
-
set_irq_chip(irq, &h720x_global_chip);
203
-
set_irq_handler(irq, handle_level_irq);
202
+
irq_set_chip_and_handler(irq, &h720x_global_chip,
203
+
handle_level_irq);
204
204
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
205
205
}
206
206
207
207
/* Initialize multiplexed IRQ's, slow path */
208
208
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
209
-
set_irq_chip(irq, &h720x_gpio_chip);
210
-
set_irq_handler(irq, handle_edge_irq);
209
+
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
210
+
handle_edge_irq);
211
211
set_irq_flags(irq, IRQF_VALID );
212
212
}
213
-
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
214
-
set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
215
-
set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
216
-
set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
213
+
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
214
+
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
215
+
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
216
+
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
217
217
218
218
#ifdef CONFIG_CPU_H7202
219
219
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
220
-
set_irq_chip(irq, &h720x_gpio_chip);
221
-
set_irq_handler(irq, handle_edge_irq);
220
+
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
221
+
handle_edge_irq);
222
222
set_irq_flags(irq, IRQF_VALID );
223
223
}
224
-
set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
224
+
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
225
225
#endif
226
226
227
227
/* Enable multiplexed irq's */
+11
-6
arch/arm/mach-h720x/cpu-h7202.c
+11
-6
arch/arm/mach-h720x/cpu-h7202.c
···
141
141
/*
142
142
* mask multiplexed timer IRQs
143
143
*/
144
-
static void inline mask_timerx_irq(struct irq_data *d)
144
+
static void inline __mask_timerx_irq(unsigned int irq)
145
145
{
146
146
unsigned int bit;
147
-
bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
147
+
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
148
148
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
149
+
}
150
+
151
+
static void inline mask_timerx_irq(struct irq_data *d)
152
+
{
153
+
__mask_timerx_irq(d->irq);
149
154
}
150
155
151
156
/*
···
201
196
202
197
for (irq = IRQ_TIMER1;
203
198
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
204
-
mask_timerx_irq(irq);
205
-
set_irq_chip(irq, &h7202_timerx_chip);
206
-
set_irq_handler(irq, handle_edge_irq);
199
+
__mask_timerx_irq(irq);
200
+
irq_set_chip_and_handler(irq, &h7202_timerx_chip,
201
+
handle_edge_irq);
207
202
set_irq_flags(irq, IRQF_VALID );
208
203
}
209
-
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
204
+
irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
210
205
211
206
h720x_init_irq();
212
207
}
+5
-5
arch/arm/mach-iop13xx/irq.c
+5
-5
arch/arm/mach-iop13xx/irq.c
···
224
224
225
225
for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
226
226
if (i < 32)
227
-
set_irq_chip(i, &iop13xx_irqchip1);
227
+
irq_set_chip(i, &iop13xx_irqchip1);
228
228
else if (i < 64)
229
-
set_irq_chip(i, &iop13xx_irqchip2);
229
+
irq_set_chip(i, &iop13xx_irqchip2);
230
230
else if (i < 96)
231
-
set_irq_chip(i, &iop13xx_irqchip3);
231
+
irq_set_chip(i, &iop13xx_irqchip3);
232
232
else
233
-
set_irq_chip(i, &iop13xx_irqchip4);
233
+
irq_set_chip(i, &iop13xx_irqchip4);
234
234
235
-
set_irq_handler(i, handle_level_irq);
235
+
irq_set_handler(i, handle_level_irq);
236
236
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
237
237
}
238
238
+3
-3
arch/arm/mach-iop13xx/msi.c
+3
-3
arch/arm/mach-iop13xx/msi.c
···
118
118
119
119
void __init iop13xx_msi_init(void)
120
120
{
121
-
set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
121
+
irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
122
122
}
123
123
124
124
/*
···
178
178
if (irq < 0)
179
179
return irq;
180
180
181
-
set_irq_msi(irq, desc);
181
+
irq_set_msi_desc(irq, desc);
182
182
183
183
msg.address_hi = 0x0;
184
184
msg.address_lo = IOP13XX_MU_MIMR_PCI;
···
187
187
msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
188
188
189
189
write_msi_msg(irq, &msg);
190
-
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
190
+
irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
191
191
192
192
return 0;
193
193
}
+1
-2
arch/arm/mach-iop32x/irq.c
+1
-2
arch/arm/mach-iop32x/irq.c
+3
-2
arch/arm/mach-iop33x/irq.c
+3
-2
arch/arm/mach-iop33x/irq.c
···
110
110
*IOP3XX_PCIIRSR = 0x0f;
111
111
112
112
for (i = 0; i < NR_IRQS; i++) {
113
-
set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
114
-
set_irq_handler(i, handle_level_irq);
113
+
irq_set_chip_and_handler(i,
114
+
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
115
+
handle_level_irq);
115
116
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
116
117
}
117
118
}
+10
-10
arch/arm/mach-ixp2000/core.c
+10
-10
arch/arm/mach-ixp2000/core.c
···
476
476
*/
477
477
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
478
478
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
479
-
set_irq_chip(irq, &ixp2000_irq_chip);
480
-
set_irq_handler(irq, handle_level_irq);
479
+
irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
480
+
handle_level_irq);
481
481
set_irq_flags(irq, IRQF_VALID);
482
482
} else set_irq_flags(irq, 0);
483
483
}
···
485
485
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
486
486
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
487
487
IXP2000_VALID_ERR_IRQ_MASK) {
488
-
set_irq_chip(irq, &ixp2000_err_irq_chip);
489
-
set_irq_handler(irq, handle_level_irq);
488
+
irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
489
+
handle_level_irq);
490
490
set_irq_flags(irq, IRQF_VALID);
491
491
}
492
492
else
493
493
set_irq_flags(irq, 0);
494
494
}
495
-
set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
495
+
irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
496
496
497
497
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
498
-
set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
499
-
set_irq_handler(irq, handle_level_irq);
498
+
irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
499
+
handle_level_irq);
500
500
set_irq_flags(irq, IRQF_VALID);
501
501
}
502
-
set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
502
+
irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
503
503
504
504
/*
505
505
* Enable PCI irqs. The actual PCI[AB] decoding is done in
···
508
508
*/
509
509
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
510
510
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
511
-
set_irq_chip(irq, &ixp2000_pci_irq_chip);
512
-
set_irq_handler(irq, handle_level_irq);
511
+
irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
512
+
handle_level_irq);
513
513
set_irq_flags(irq, IRQF_VALID);
514
514
}
515
515
}
+3
-3
arch/arm/mach-ixp2000/ixdp2x00.c
+3
-3
arch/arm/mach-ixp2000/ixdp2x00.c
···
158
158
*board_irq_mask = 0xffffffff;
159
159
160
160
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
161
-
set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
162
-
set_irq_handler(irq, handle_level_irq);
161
+
irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
162
+
handle_level_irq);
163
163
set_irq_flags(irq, IRQF_VALID);
164
164
}
165
165
166
166
/* Hook into PCI interrupt */
167
-
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
167
+
irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
168
168
}
169
169
170
170
/*************************************************************************
+3
-3
arch/arm/mach-ixp2000/ixdp2x01.c
+3
-3
arch/arm/mach-ixp2000/ixdp2x01.c
···
115
115
116
116
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
117
117
if (irq & valid_irq_mask) {
118
-
set_irq_chip(irq, &ixdp2x01_irq_chip);
119
-
set_irq_handler(irq, handle_level_irq);
118
+
irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
119
+
handle_level_irq);
120
120
set_irq_flags(irq, IRQF_VALID);
121
121
} else {
122
122
set_irq_flags(irq, 0);
···
124
124
}
125
125
126
126
/* Hook into PCI interrupts */
127
-
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
127
+
irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
128
128
}
129
129
130
130
+7
-7
arch/arm/mach-ixp23xx/core.c
+7
-7
arch/arm/mach-ixp23xx/core.c
···
289
289
{
290
290
switch (type) {
291
291
case IXP23XX_IRQ_LEVEL:
292
-
set_irq_chip(irq, &ixp23xx_irq_level_chip);
293
-
set_irq_handler(irq, handle_level_irq);
292
+
irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
293
+
handle_level_irq);
294
294
break;
295
295
case IXP23XX_IRQ_EDGE:
296
-
set_irq_chip(irq, &ixp23xx_irq_edge_chip);
297
-
set_irq_handler(irq, handle_edge_irq);
296
+
irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
297
+
handle_edge_irq);
298
298
break;
299
299
}
300
300
set_irq_flags(irq, IRQF_VALID);
···
324
324
}
325
325
326
326
for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
327
-
set_irq_chip(irq, &ixp23xx_pci_irq_chip);
328
-
set_irq_handler(irq, handle_level_irq);
327
+
irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
328
+
handle_level_irq);
329
329
set_irq_flags(irq, IRQF_VALID);
330
330
}
331
331
332
-
set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
332
+
irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
333
333
}
334
334
335
335
+6
-6
arch/arm/mach-ixp23xx/ixdp2351.c
+6
-6
arch/arm/mach-ixp23xx/ixdp2351.c
···
136
136
irq++) {
137
137
if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
138
138
set_irq_flags(irq, IRQF_VALID);
139
-
set_irq_handler(irq, handle_level_irq);
140
-
set_irq_chip(irq, &ixdp2351_inta_chip);
139
+
irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
140
+
handle_level_irq);
141
141
}
142
142
}
143
143
···
147
147
irq++) {
148
148
if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
149
149
set_irq_flags(irq, IRQF_VALID);
150
-
set_irq_handler(irq, handle_level_irq);
151
-
set_irq_chip(irq, &ixdp2351_intb_chip);
150
+
irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
151
+
handle_level_irq);
152
152
}
153
153
}
154
154
155
-
set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
156
-
set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
155
+
irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
156
+
irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
157
157
}
158
158
159
159
/*
+2
-2
arch/arm/mach-ixp23xx/roadrunner.c
+2
-2
arch/arm/mach-ixp23xx/roadrunner.c
···
110
110
111
111
static void __init roadrunner_pci_preinit(void)
112
112
{
113
-
set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
114
-
set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
113
+
irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
114
+
irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
115
115
116
116
ixp23xx_pci_preinit();
117
117
}
+4
-4
arch/arm/mach-ixp4xx/avila-pci.c
+4
-4
arch/arm/mach-ixp4xx/avila-pci.c
···
39
39
40
40
void __init avila_pci_preinit(void)
41
41
{
42
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
43
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
44
-
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
45
-
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
42
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
43
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
44
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
45
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
46
46
ixp4xx_pci_preinit();
47
47
}
48
48
+2
-2
arch/arm/mach-ixp4xx/common.c
+2
-2
arch/arm/mach-ixp4xx/common.c
···
252
252
253
253
/* Default to all level triggered */
254
254
for(i = 0; i < NR_IRQS; i++) {
255
-
set_irq_chip(i, &ixp4xx_irq_chip);
256
-
set_irq_handler(i, handle_level_irq);
255
+
irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
256
+
handle_level_irq);
257
257
set_irq_flags(i, IRQF_VALID);
258
258
}
259
259
}
+2
-2
arch/arm/mach-ixp4xx/coyote-pci.c
+2
-2
arch/arm/mach-ixp4xx/coyote-pci.c
···
32
32
33
33
void __init coyote_pci_preinit(void)
34
34
{
35
-
set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
36
-
set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
35
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
36
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
37
37
ixp4xx_pci_preinit();
38
38
}
39
39
+6
-6
arch/arm/mach-ixp4xx/dsmg600-pci.c
+6
-6
arch/arm/mach-ixp4xx/dsmg600-pci.c
···
35
35
36
36
void __init dsmg600_pci_preinit(void)
37
37
{
38
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
39
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
40
-
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
41
-
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
42
-
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
43
-
set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
38
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
39
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
40
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
41
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
42
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
43
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
44
44
ixp4xx_pci_preinit();
45
45
}
46
46
+3
-3
arch/arm/mach-ixp4xx/fsg-pci.c
+3
-3
arch/arm/mach-ixp4xx/fsg-pci.c
···
32
32
33
33
void __init fsg_pci_preinit(void)
34
34
{
35
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37
-
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
35
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
38
38
ixp4xx_pci_preinit();
39
39
}
40
40
+2
-2
arch/arm/mach-ixp4xx/gateway7001-pci.c
+2
-2
arch/arm/mach-ixp4xx/gateway7001-pci.c
···
29
29
30
30
void __init gateway7001_pci_preinit(void)
31
31
{
32
-
set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
33
-
set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
32
+
irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
33
+
irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
34
34
35
35
ixp4xx_pci_preinit();
36
36
}
+6
-6
arch/arm/mach-ixp4xx/goramo_mlr.c
+6
-6
arch/arm/mach-ixp4xx/goramo_mlr.c
···
420
420
gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
421
421
gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
422
422
gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
423
-
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
424
-
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
423
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
424
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
425
425
426
426
set_control(CONTROL_HSS0_DTR_N, 1);
427
427
set_control(CONTROL_HSS1_DTR_N, 1);
···
441
441
#ifdef CONFIG_PCI
442
442
static void __init gmlr_pci_preinit(void)
443
443
{
444
-
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
445
-
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
446
-
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
447
-
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
444
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
445
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
446
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
447
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
448
448
ixp4xx_pci_preinit();
449
449
}
450
450
+2
-2
arch/arm/mach-ixp4xx/gtwx5715-pci.c
+2
-2
arch/arm/mach-ixp4xx/gtwx5715-pci.c
···
43
43
*/
44
44
void __init gtwx5715_pci_preinit(void)
45
45
{
46
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
47
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
46
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
47
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
48
48
ixp4xx_pci_preinit();
49
49
}
50
50
+4
-4
arch/arm/mach-ixp4xx/ixdp425-pci.c
+4
-4
arch/arm/mach-ixp4xx/ixdp425-pci.c
···
36
36
37
37
void __init ixdp425_pci_preinit(void)
38
38
{
39
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
40
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41
-
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
42
-
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
39
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
40
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
42
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
43
43
ixp4xx_pci_preinit();
44
44
}
45
45
+2
-2
arch/arm/mach-ixp4xx/ixdpg425-pci.c
+2
-2
arch/arm/mach-ixp4xx/ixdpg425-pci.c
···
25
25
26
26
void __init ixdpg425_pci_preinit(void)
27
27
{
28
-
set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
29
-
set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
28
+
irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
29
+
irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
30
30
31
31
ixp4xx_pci_preinit();
32
32
}
+5
-5
arch/arm/mach-ixp4xx/nas100d-pci.c
+5
-5
arch/arm/mach-ixp4xx/nas100d-pci.c
···
33
33
34
34
void __init nas100d_pci_preinit(void)
35
35
{
36
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
37
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
38
-
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
39
-
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
40
-
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
36
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
37
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
38
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
39
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
40
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
41
41
ixp4xx_pci_preinit();
42
42
}
43
43
+3
-3
arch/arm/mach-ixp4xx/nslu2-pci.c
+3
-3
arch/arm/mach-ixp4xx/nslu2-pci.c
···
32
32
33
33
void __init nslu2_pci_preinit(void)
34
34
{
35
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37
-
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
35
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
38
38
ixp4xx_pci_preinit();
39
39
}
40
40
+2
-2
arch/arm/mach-ixp4xx/vulcan-pci.c
+2
-2
arch/arm/mach-ixp4xx/vulcan-pci.c
···
38
38
pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
39
39
(int)(pci_cardbus_mem_size >> 20));
40
40
#endif
41
-
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
42
-
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
42
+
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
43
43
ixp4xx_pci_preinit();
44
44
}
45
45
+2
-2
arch/arm/mach-ixp4xx/wg302v2-pci.c
+2
-2
arch/arm/mach-ixp4xx/wg302v2-pci.c
···
29
29
30
30
void __init wg302v2_pci_preinit(void)
31
31
{
32
-
set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
33
-
set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
32
+
irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
33
+
irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
34
34
35
35
ixp4xx_pci_preinit();
36
36
}
+8
-7
arch/arm/mach-kirkwood/irq.c
+8
-7
arch/arm/mach-kirkwood/irq.c
···
35
35
*/
36
36
orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
37
37
IRQ_KIRKWOOD_GPIO_START);
38
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
39
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
40
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
41
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
38
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
39
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
40
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
41
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
42
42
43
43
orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
44
44
IRQ_KIRKWOOD_GPIO_START + 32);
45
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
46
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
47
-
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
45
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
46
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
47
+
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
48
+
gpio_irq_handler);
48
49
}
+1
-1
arch/arm/mach-ks8695/gpio.c
+1
-1
arch/arm/mach-ks8695/gpio.c
+10
-8
arch/arm/mach-ks8695/irq.c
+10
-8
arch/arm/mach-ks8695/irq.c
···
115
115
}
116
116
117
117
if (level_triggered) {
118
-
set_irq_chip(d->irq, &ks8695_irq_level_chip);
119
-
set_irq_handler(d->irq, handle_level_irq);
118
+
irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
119
+
handle_level_irq);
120
120
}
121
121
else {
122
-
set_irq_chip(d->irq, &ks8695_irq_edge_chip);
123
-
set_irq_handler(d->irq, handle_edge_irq);
122
+
irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
123
+
handle_edge_irq);
124
124
}
125
125
126
126
__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
···
158
158
case KS8695_IRQ_UART_RX:
159
159
case KS8695_IRQ_COMM_TX:
160
160
case KS8695_IRQ_COMM_RX:
161
-
set_irq_chip(irq, &ks8695_irq_level_chip);
162
-
set_irq_handler(irq, handle_level_irq);
161
+
irq_set_chip_and_handler(irq,
162
+
&ks8695_irq_level_chip,
163
+
handle_level_irq);
163
164
break;
164
165
165
166
/* Edge-triggered interrupts */
166
167
default:
167
168
/* clear pending bit */
168
169
ks8695_irq_ack(irq_get_irq_data(irq));
169
-
set_irq_chip(irq, &ks8695_irq_edge_chip);
170
-
set_irq_handler(irq, handle_edge_irq);
170
+
irq_set_chip_and_handler(irq,
171
+
&ks8695_irq_edge_chip,
172
+
handle_edge_irq);
171
173
}
172
174
173
175
set_irq_flags(irq, IRQF_VALID);
+5
-5
arch/arm/mach-lpc32xx/irq.c
+5
-5
arch/arm/mach-lpc32xx/irq.c
···
290
290
}
291
291
292
292
/* Ok to use the level handler for all types */
293
-
set_irq_handler(d->irq, handle_level_irq);
293
+
irq_set_handler(d->irq, handle_level_irq);
294
294
295
295
return 0;
296
296
}
···
390
390
391
391
/* Configure supported IRQ's */
392
392
for (i = 0; i < NR_IRQS; i++) {
393
-
set_irq_chip(i, &lpc32xx_irq_chip);
394
-
set_irq_handler(i, handle_level_irq);
393
+
irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
394
+
handle_level_irq);
395
395
set_irq_flags(i, IRQF_VALID);
396
396
}
397
397
···
406
406
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
407
407
408
408
/* MIC SUBIRQx interrupts will route handling to the chain handlers */
409
-
set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
410
-
set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
409
+
irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
410
+
irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
411
411
412
412
/* Initially disable all wake events */
413
413
__raw_writel(0, LPC32XX_CLKPWR_P01_ER);
+9
-9
arch/arm/mach-mmp/irq-mmp2.c
+9
-9
arch/arm/mach-mmp/irq-mmp2.c
···
110
110
if (chip->irq_ack)
111
111
chip->irq_ack(d);
112
112
113
-
set_irq_chip(irq, chip);
113
+
irq_set_chip(irq, chip);
114
114
set_irq_flags(irq, IRQF_VALID);
115
-
set_irq_handler(irq, handle_level_irq);
115
+
irq_set_handler(irq, handle_level_irq);
116
116
}
117
117
}
118
118
···
122
122
123
123
for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
124
124
icu_mask_irq(irq_get_irq_data(irq));
125
-
set_irq_chip(irq, &icu_irq_chip);
125
+
irq_set_chip(irq, &icu_irq_chip);
126
126
set_irq_flags(irq, IRQF_VALID);
127
127
128
128
switch (irq) {
···
133
133
case IRQ_MMP2_SSP_MUX:
134
134
break;
135
135
default:
136
-
set_irq_handler(irq, handle_level_irq);
136
+
irq_set_handler(irq, handle_level_irq);
137
137
break;
138
138
}
139
139
}
···
149
149
init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
150
150
init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
151
151
152
-
set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
153
-
set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
154
-
set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
155
-
set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
156
-
set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
152
+
irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
153
+
irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
154
+
irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
155
+
irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
156
+
irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
157
157
}
+1
-2
arch/arm/mach-mmp/irq-pxa168.c
+1
-2
arch/arm/mach-mmp/irq-pxa168.c
+1
-1
arch/arm/mach-msm/board-msm8960.c
+1
-1
arch/arm/mach-msm/board-msm8960.c
+1
-1
arch/arm/mach-msm/board-msm8x60.c
+1
-1
arch/arm/mach-msm/board-msm8x60.c
+5
-5
arch/arm/mach-msm/board-trout-gpio.c
+5
-5
arch/arm/mach-msm/board-trout-gpio.c
···
214
214
{
215
215
int i;
216
216
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
217
-
set_irq_chip(i, &trout_gpio_irq_chip);
218
-
set_irq_handler(i, handle_edge_irq);
217
+
irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
218
+
handle_edge_irq);
219
219
set_irq_flags(i, IRQF_VALID);
220
220
}
221
221
222
222
for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
223
223
gpiochip_add(&msm_gpio_banks[i].chip);
224
224
225
-
set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
226
-
set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
227
-
set_irq_wake(MSM_GPIO_TO_INT(17), 1);
225
+
irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
226
+
irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
227
+
irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
228
228
229
229
return 0;
230
230
}
+1
-1
arch/arm/mach-msm/board-trout-mmc.c
+1
-1
arch/arm/mach-msm/board-trout-mmc.c
+25
-24
arch/arm/mach-msm/gpio-v2.c
+25
-24
arch/arm/mach-msm/gpio-v2.c
···
230
230
val, val2);
231
231
}
232
232
233
-
static void msm_gpio_irq_ack(unsigned int irq)
233
+
static void msm_gpio_irq_ack(struct irq_data *d)
234
234
{
235
-
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
235
+
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
236
236
237
237
writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
238
238
if (test_bit(gpio, msm_gpio.dual_edge_irqs))
239
239
msm_gpio_update_dual_edge_pos(gpio);
240
240
}
241
241
242
-
static void msm_gpio_irq_mask(unsigned int irq)
242
+
static void msm_gpio_irq_mask(struct irq_data *d)
243
243
{
244
-
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
244
+
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
245
245
unsigned long irq_flags;
246
246
247
247
spin_lock_irqsave(&tlmm_lock, irq_flags);
···
251
251
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
252
252
}
253
253
254
-
static void msm_gpio_irq_unmask(unsigned int irq)
254
+
static void msm_gpio_irq_unmask(struct irq_data *d)
255
255
{
256
-
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
256
+
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
257
257
unsigned long irq_flags;
258
258
259
259
spin_lock_irqsave(&tlmm_lock, irq_flags);
···
263
263
spin_unlock_irqrestore(&tlmm_lock, irq_flags);
264
264
}
265
265
266
-
static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
266
+
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
267
267
{
268
-
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
268
+
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
269
269
unsigned long irq_flags;
270
270
uint32_t bits;
271
271
···
275
275
276
276
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
277
277
bits |= BIT(INTR_DECT_CTL);
278
-
irq_desc[irq].handle_irq = handle_edge_irq;
278
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
279
279
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
280
280
__set_bit(gpio, msm_gpio.dual_edge_irqs);
281
281
else
282
282
__clear_bit(gpio, msm_gpio.dual_edge_irqs);
283
283
} else {
284
284
bits &= ~BIT(INTR_DECT_CTL);
285
-
irq_desc[irq].handle_irq = handle_level_irq;
285
+
__irq_set_handler_locked(d->irq, handle_level_irq);
286
286
__clear_bit(gpio, msm_gpio.dual_edge_irqs);
287
287
}
288
288
···
309
309
*/
310
310
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
311
311
{
312
+
struct irq_data *data = irq_desc_get_irq_data(desc);
312
313
unsigned long i;
313
314
314
315
for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
···
319
318
generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
320
319
i));
321
320
}
322
-
desc->chip->ack(irq);
321
+
data->chip->irq_ack(data);
323
322
}
324
323
325
-
static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
324
+
static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
326
325
{
327
-
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
326
+
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
328
327
329
328
if (on) {
330
329
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
331
-
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
330
+
irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
332
331
set_bit(gpio, msm_gpio.wake_irqs);
333
332
} else {
334
333
clear_bit(gpio, msm_gpio.wake_irqs);
335
334
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
336
-
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
335
+
irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
337
336
}
338
337
339
338
return 0;
···
341
340
342
341
static struct irq_chip msm_gpio_irq_chip = {
343
342
.name = "msmgpio",
344
-
.mask = msm_gpio_irq_mask,
345
-
.unmask = msm_gpio_irq_unmask,
346
-
.ack = msm_gpio_irq_ack,
347
-
.set_type = msm_gpio_irq_set_type,
348
-
.set_wake = msm_gpio_irq_set_wake,
343
+
.irq_mask = msm_gpio_irq_mask,
344
+
.irq_unmask = msm_gpio_irq_unmask,
345
+
.irq_ack = msm_gpio_irq_ack,
346
+
.irq_set_type = msm_gpio_irq_set_type,
347
+
.irq_set_wake = msm_gpio_irq_set_wake,
349
348
};
350
349
351
350
static int __devinit msm_gpio_probe(struct platform_device *dev)
···
362
361
363
362
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
364
363
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
365
-
set_irq_chip(irq, &msm_gpio_irq_chip);
366
-
set_irq_handler(irq, handle_level_irq);
364
+
irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
365
+
handle_level_irq);
367
366
set_irq_flags(irq, IRQF_VALID);
368
367
}
369
368
370
-
set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
369
+
irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
371
370
msm_summary_irq_handler);
372
371
return 0;
373
372
}
···
379
378
if (ret < 0)
380
379
return ret;
381
380
382
-
set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
381
+
irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
383
382
384
383
return 0;
385
384
}
+9
-9
arch/arm/mach-msm/gpio.c
+9
-9
arch/arm/mach-msm/gpio.c
···
293
293
val = readl(msm_chip->regs.int_edge);
294
294
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
295
295
writel(val | mask, msm_chip->regs.int_edge);
296
-
irq_desc[d->irq].handle_irq = handle_edge_irq;
296
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
297
297
} else {
298
298
writel(val & ~mask, msm_chip->regs.int_edge);
299
-
irq_desc[d->irq].handle_irq = handle_level_irq;
299
+
__irq_set_handler_locked(d->irq, handle_level_irq);
300
300
}
301
301
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
302
302
msm_chip->both_edge_detect |= mask;
···
354
354
msm_gpio_chips[j].chip.base +
355
355
msm_gpio_chips[j].chip.ngpio)
356
356
j++;
357
-
set_irq_chip_data(i, &msm_gpio_chips[j]);
358
-
set_irq_chip(i, &msm_gpio_irq_chip);
359
-
set_irq_handler(i, handle_edge_irq);
357
+
irq_set_chip_data(i, &msm_gpio_chips[j]);
358
+
irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
359
+
handle_edge_irq);
360
360
set_irq_flags(i, IRQF_VALID);
361
361
}
362
362
···
366
366
gpiochip_add(&msm_gpio_chips[i].chip);
367
367
}
368
368
369
-
set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
370
-
set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
371
-
set_irq_wake(INT_GPIO_GROUP1, 1);
372
-
set_irq_wake(INT_GPIO_GROUP2, 2);
369
+
irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
370
+
irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
371
+
irq_set_irq_wake(INT_GPIO_GROUP1, 1);
372
+
irq_set_irq_wake(INT_GPIO_GROUP2, 2);
373
373
return 0;
374
374
}
375
375
+3
-4
arch/arm/mach-msm/irq-vic.c
+3
-4
arch/arm/mach-msm/irq-vic.c
···
313
313
type = msm_irq_shadow_reg[index].int_type;
314
314
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
315
315
type |= b;
316
-
irq_desc[d->irq].handle_irq = handle_edge_irq;
316
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
317
317
}
318
318
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
319
319
type &= ~b;
320
-
irq_desc[d->irq].handle_irq = handle_level_irq;
320
+
__irq_set_handler_locked(d->irq, handle_level_irq);
321
321
}
322
322
writel(type, treg);
323
323
msm_irq_shadow_reg[index].int_type = type;
···
357
357
writel(3, VIC_INT_MASTEREN);
358
358
359
359
for (n = 0; n < NR_MSM_IRQS; n++) {
360
-
set_irq_chip(n, &msm_irq_chip);
361
-
set_irq_handler(n, handle_level_irq);
360
+
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
362
361
set_irq_flags(n, IRQF_VALID);
363
362
}
364
363
}
+3
-4
arch/arm/mach-msm/irq.c
+3
-4
arch/arm/mach-msm/irq.c
···
100
100
101
101
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
102
102
writel(readl(treg) | b, treg);
103
-
irq_desc[d->irq].handle_irq = handle_edge_irq;
103
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
104
104
}
105
105
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
106
106
writel(readl(treg) & (~b), treg);
107
-
irq_desc[d->irq].handle_irq = handle_level_irq;
107
+
__irq_set_handler_locked(d->irq, handle_level_irq);
108
108
}
109
109
return 0;
110
110
}
···
145
145
writel(1, VIC_INT_MASTEREN);
146
146
147
147
for (n = 0; n < NR_MSM_IRQS; n++) {
148
-
set_irq_chip(n, &msm_irq_chip);
149
-
set_irq_handler(n, handle_level_irq);
148
+
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
150
149
set_irq_flags(n, IRQF_VALID);
151
150
}
152
151
}
+5
-6
arch/arm/mach-msm/sirc.c
+5
-6
arch/arm/mach-msm/sirc.c
···
105
105
val = readl(sirc_regs.int_type);
106
106
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
107
107
val |= mask;
108
-
irq_desc[d->irq].handle_irq = handle_edge_irq;
108
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
109
109
} else {
110
110
val &= ~mask;
111
-
irq_desc[d->irq].handle_irq = handle_level_irq;
111
+
__irq_set_handler_locked(d->irq, handle_level_irq);
112
112
}
113
113
114
114
writel(val, sirc_regs.int_type);
···
158
158
wake_enable = 0;
159
159
160
160
for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
161
-
set_irq_chip(i, &sirc_irq_chip);
162
-
set_irq_handler(i, handle_edge_irq);
161
+
irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
163
162
set_irq_flags(i, IRQF_VALID);
164
163
}
165
164
166
165
for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
167
-
set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
166
+
irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
168
167
sirc_irq_handler);
169
-
set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
168
+
irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
170
169
}
171
170
return;
172
171
}
+4
-4
arch/arm/mach-mv78xx0/irq.c
+4
-4
arch/arm/mach-mv78xx0/irq.c
···
38
38
orion_gpio_init(0, 32, GPIO_VIRT_BASE,
39
39
mv78xx0_core_index() ? 0x18 : 0,
40
40
IRQ_MV78XX0_GPIO_START);
41
-
set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
42
-
set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
43
-
set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
44
-
set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
41
+
irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
42
+
irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
43
+
irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
44
+
irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
45
45
}
+3
-4
arch/arm/mach-mx3/mach-mx31ads.c
+3
-4
arch/arm/mach-mx3/mach-mx31ads.c
···
199
199
__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
200
200
for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
201
201
i++) {
202
-
set_irq_chip(i, &expio_irq_chip);
203
-
set_irq_handler(i, handle_level_irq);
202
+
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
204
203
set_irq_flags(i, IRQF_VALID);
205
204
}
206
-
set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
207
-
set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
205
+
irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
206
+
irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
208
207
}
209
208
210
209
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+1
-1
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+1
-1
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
···
212
212
213
213
gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
214
214
gpio_direction_input(MBIMX51_TSC2007_GPIO);
215
-
set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
215
+
irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
216
216
i2c_register_board_info(1, mbimx51_i2c_devices,
217
217
ARRAY_SIZE(mbimx51_i2c_devices));
218
218
+5
-5
arch/arm/mach-mxs/gpio.c
+5
-5
arch/arm/mach-mxs/gpio.c
···
136
136
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
137
137
{
138
138
u32 irq_stat;
139
-
struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
139
+
struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
140
140
u32 gpio_irq_no_base = port->virtual_irq_start;
141
141
142
142
desc->irq_data.chip->irq_ack(&desc->irq_data);
···
265
265
266
266
for (j = port[i].virtual_irq_start;
267
267
j < port[i].virtual_irq_start + 32; j++) {
268
-
set_irq_chip(j, &gpio_irq_chip);
269
-
set_irq_handler(j, handle_level_irq);
268
+
irq_set_chip_and_handler(j, &gpio_irq_chip,
269
+
handle_level_irq);
270
270
set_irq_flags(j, IRQF_VALID);
271
271
}
272
272
273
273
/* setup one handler for each entry */
274
-
set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
275
-
set_irq_data(port[i].irq, &port[i]);
274
+
irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
275
+
irq_set_handler_data(port[i].irq, &port[i]);
276
276
277
277
/* register gpio chip */
278
278
port[i].chip.direction_input = mxs_gpio_direction_input;
+1
-2
arch/arm/mach-mxs/icoll.c
+1
-2
arch/arm/mach-mxs/icoll.c
···
74
74
mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
75
75
76
76
for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
77
-
set_irq_chip(i, &mxs_icoll_chip);
78
-
set_irq_handler(i, handle_level_irq);
77
+
irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
79
78
set_irq_flags(i, IRQF_VALID);
80
79
}
81
80
}
+3
-3
arch/arm/mach-netx/generic.c
+3
-3
arch/arm/mach-netx/generic.c
···
171
171
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
172
172
173
173
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
174
-
set_irq_chip(irq, &netx_hif_chip);
175
-
set_irq_handler(irq, handle_level_irq);
174
+
irq_set_chip_and_handler(irq, &netx_hif_chip,
175
+
handle_level_irq);
176
176
set_irq_flags(irq, IRQF_VALID);
177
177
}
178
178
179
179
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
180
-
set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
180
+
irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
181
181
}
182
182
183
183
static int __init netx_init(void)
+4
-4
arch/arm/mach-ns9xxx/board-a9m9750dev.c
+4
-4
arch/arm/mach-ns9xxx/board-a9m9750dev.c
···
107
107
__func__);
108
108
109
109
for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
110
-
set_irq_chip(i, &a9m9750dev_fpga_chip);
111
-
set_irq_handler(i, handle_level_irq);
110
+
irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
111
+
handle_level_irq);
112
112
set_irq_flags(i, IRQF_VALID);
113
113
}
114
114
···
118
118
REGSET(eic, SYS_EIC, LVEDG, LEVEL);
119
119
__raw_writel(eic, SYS_EIC(2));
120
120
121
-
set_irq_chained_handler(IRQ_NS9XXX_EXT2,
122
-
a9m9750dev_fpga_demux_handler);
121
+
irq_set_chained_handler(IRQ_NS9XXX_EXT2,
122
+
a9m9750dev_fpga_demux_handler);
123
123
}
124
124
125
125
void __init board_a9m9750dev_init_machine(void)
-2
arch/arm/mach-ns9xxx/include/mach/board.h
-2
arch/arm/mach-ns9xxx/include/mach/board.h
-5
arch/arm/mach-ns9xxx/include/mach/module.h
-5
arch/arm/mach-ns9xxx/include/mach/module.h
···
18
18
)
19
19
20
20
#define module_is_cc9c() (0 \
21
-
|| machine_is_cc9c() \
22
21
)
23
22
24
23
#define module_is_cc9p9210() (0 \
···
31
32
)
32
33
33
34
#define module_is_cc9p9360() (0 \
34
-
|| machine_is_a9m9360() \
35
35
|| machine_is_cc9p9360dev() \
36
36
|| machine_is_cc9p9360js() \
37
-
|| machine_is_cc9p9360val() \
38
37
)
39
38
40
39
#define module_is_cc9p9750() (0 \
41
40
|| machine_is_a9m9750() \
42
-
|| machine_is_cc9p9750dev() \
43
41
|| machine_is_cc9p9750js() \
44
42
|| machine_is_cc9p9750val() \
45
43
)
46
44
47
45
#define module_is_ccw9c() (0 \
48
-
|| machine_is_ccw9c() \
49
46
)
50
47
51
48
#define module_is_inc20otter() (0 \
+1
-2
arch/arm/mach-ns9xxx/irq.c
+1
-2
arch/arm/mach-ns9xxx/irq.c
···
67
67
__raw_writel(prio2irq(i), SYS_IVA(i));
68
68
69
69
for (i = 0; i <= 31; ++i) {
70
-
set_irq_chip(i, &ns9xxx_chip);
71
-
set_irq_handler(i, handle_fasteoi_irq);
70
+
irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
72
71
set_irq_flags(i, IRQF_VALID);
73
72
irq_set_status_flags(i, IRQ_LEVEL);
74
73
}
+2
-2
arch/arm/mach-nuc93x/irq.c
+2
-2
arch/arm/mach-nuc93x/irq.c
···
59
59
__raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
60
60
61
61
for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
62
-
set_irq_chip(irqno, &nuc93x_irq_chip);
63
-
set_irq_handler(irqno, handle_level_irq);
62
+
irq_set_chip_and_handler(irqno, &nuc93x_irq_chip,
63
+
handle_level_irq);
64
64
set_irq_flags(irqno, IRQF_VALID);
65
65
}
66
66
}
+3
-3
arch/arm/mach-omap1/board-osk.c
+3
-3
arch/arm/mach-omap1/board-osk.c
···
276
276
return;
277
277
}
278
278
/* the CF I/O IRQ is really active-low */
279
-
set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
279
+
irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
280
280
}
281
281
282
282
static void __init osk_init_irq(void)
···
482
482
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
483
483
gpio_request(4, "ts_int");
484
484
gpio_direction_input(4);
485
-
set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
485
+
irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
486
486
487
487
spi_register_board_info(mistral_boardinfo,
488
488
ARRAY_SIZE(mistral_boardinfo));
···
500
500
int irq = gpio_to_irq(OMAP_MPUIO(2));
501
501
502
502
gpio_direction_input(OMAP_MPUIO(2));
503
-
set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
503
+
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
504
504
#ifdef CONFIG_PM
505
505
/* share the IRQ in case someone wants to use the
506
506
* button for more than wakeup from system sleep.
+4
-4
arch/arm/mach-omap1/board-palmz71.c
+4
-4
arch/arm/mach-omap1/board-palmz71.c
···
256
256
{
257
257
if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) {
258
258
printk(KERN_INFO "PM: Power cable connected\n");
259
-
set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
260
-
IRQ_TYPE_EDGE_FALLING);
259
+
irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
260
+
IRQ_TYPE_EDGE_FALLING);
261
261
} else {
262
262
printk(KERN_INFO "PM: Power cable disconnected\n");
263
-
set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
264
-
IRQ_TYPE_EDGE_RISING);
263
+
irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
264
+
IRQ_TYPE_EDGE_RISING);
265
265
}
266
266
return IRQ_HANDLED;
267
267
}
+4
-4
arch/arm/mach-omap1/board-voiceblue.c
+4
-4
arch/arm/mach-omap1/board-voiceblue.c
···
279
279
gpio_request(13, "16C554 irq");
280
280
gpio_request(14, "16C554 irq");
281
281
gpio_request(15, "16C554 irq");
282
-
set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
283
-
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
284
-
set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
285
-
set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
282
+
irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
283
+
irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
284
+
irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
285
+
irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
286
286
287
287
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
288
288
omap_board_config = voiceblue_config;
+5
-5
arch/arm/mach-omap1/fpga.c
+5
-5
arch/arm/mach-omap1/fpga.c
···
156
156
* The touchscreen interrupt is level-sensitive, so
157
157
* we'll use the regular mask_ack routine for it.
158
158
*/
159
-
set_irq_chip(i, &omap_fpga_irq_ack);
159
+
irq_set_chip(i, &omap_fpga_irq_ack);
160
160
}
161
161
else {
162
162
/*
163
163
* All FPGA interrupts except the touchscreen are
164
164
* edge-sensitive, so we won't mask them.
165
165
*/
166
-
set_irq_chip(i, &omap_fpga_irq);
166
+
irq_set_chip(i, &omap_fpga_irq);
167
167
}
168
168
169
-
set_irq_handler(i, handle_edge_irq);
169
+
irq_set_handler(i, handle_edge_irq);
170
170
set_irq_flags(i, IRQF_VALID);
171
171
}
172
172
···
183
183
return;
184
184
}
185
185
gpio_direction_input(13);
186
-
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
187
-
set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
186
+
irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
187
+
irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
188
188
}
+2
-2
arch/arm/mach-omap1/irq.c
+2
-2
arch/arm/mach-omap1/irq.c
···
230
230
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
231
231
omap_irq_set_cfg(j, 0, 0, irq_trigger);
232
232
233
-
set_irq_chip(j, &omap_irq_chip);
234
-
set_irq_handler(j, handle_level_irq);
233
+
irq_set_chip_and_handler(j, &omap_irq_chip,
234
+
handle_level_irq);
235
235
set_irq_flags(j, IRQF_VALID);
236
236
}
237
237
}
+1
-1
arch/arm/mach-omap2/gpmc.c
+1
-1
arch/arm/mach-omap2/gpmc.c
···
743
743
/* initalize the irq_chained */
744
744
irq = OMAP_GPMC_IRQ_BASE;
745
745
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
746
-
set_irq_chip_and_handler(irq, &dummy_irq_chip,
746
+
irq_set_chip_and_handler(irq, &dummy_irq_chip,
747
747
handle_simple_irq);
748
748
set_irq_flags(irq, IRQF_VALID);
749
749
irq++;
+1
-2
arch/arm/mach-omap2/irq.c
+1
-2
arch/arm/mach-omap2/irq.c
···
223
223
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
224
224
225
225
for (i = 0; i < nr_of_irqs; i++) {
226
-
set_irq_chip(i, &omap_irq_chip);
227
-
set_irq_handler(i, handle_level_irq);
226
+
irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
228
227
set_irq_flags(i, IRQF_VALID);
229
228
}
230
229
}
+2
-2
arch/arm/mach-orion5x/db88f5281-setup.c
+2
-2
arch/arm/mach-orion5x/db88f5281-setup.c
···
213
213
pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
214
214
if (gpio_request(pin, "PCI Int1") == 0) {
215
215
if (gpio_direction_input(pin) == 0) {
216
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
216
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
217
217
} else {
218
218
printk(KERN_ERR "db88f5281_pci_preinit faield to "
219
219
"set_irq_type pin %d\n", pin);
···
226
226
pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
227
227
if (gpio_request(pin, "PCI Int2") == 0) {
228
228
if (gpio_direction_input(pin) == 0) {
229
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
229
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
230
230
} else {
231
231
printk(KERN_ERR "db88f5281_pci_preinit faield "
232
232
"to set_irq_type pin %d\n", pin);
+4
-4
arch/arm/mach-orion5x/irq.c
+4
-4
arch/arm/mach-orion5x/irq.c
···
34
34
* Initialize gpiolib for GPIOs 0-31.
35
35
*/
36
36
orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
37
-
set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
38
-
set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
39
-
set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
40
-
set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
37
+
irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
38
+
irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
39
+
irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
40
+
irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
41
41
}
+2
-2
arch/arm/mach-orion5x/rd88f5182-setup.c
+2
-2
arch/arm/mach-orion5x/rd88f5182-setup.c
···
148
148
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
149
149
if (gpio_request(pin, "PCI IntA") == 0) {
150
150
if (gpio_direction_input(pin) == 0) {
151
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
151
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
152
152
} else {
153
153
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
154
154
"set_irq_type pin %d\n", pin);
···
161
161
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
162
162
if (gpio_request(pin, "PCI IntB") == 0) {
163
163
if (gpio_direction_input(pin) == 0) {
164
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
164
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
165
165
} else {
166
166
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
167
167
"set_irq_type pin %d\n", pin);
+1
-1
arch/arm/mach-orion5x/terastation_pro2-setup.c
+1
-1
arch/arm/mach-orion5x/terastation_pro2-setup.c
···
88
88
pin = TSP2_PCI_SLOT0_IRQ_PIN;
89
89
if (gpio_request(pin, "PCI Int1") == 0) {
90
90
if (gpio_direction_input(pin) == 0) {
91
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
91
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
92
92
} else {
93
93
printk(KERN_ERR "tsp2_pci_preinit failed "
94
94
"to set_irq_type pin %d\n", pin);
+2
-2
arch/arm/mach-orion5x/ts209-setup.c
+2
-2
arch/arm/mach-orion5x/ts209-setup.c
···
117
117
pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
118
118
if (gpio_request(pin, "PCI Int1") == 0) {
119
119
if (gpio_direction_input(pin) == 0) {
120
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
120
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
121
121
} else {
122
122
printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
123
123
"set_irq_type pin %d\n", pin);
···
131
131
pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
132
132
if (gpio_request(pin, "PCI Int2") == 0) {
133
133
if (gpio_direction_input(pin) == 0) {
134
-
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
134
+
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
135
135
} else {
136
136
printk(KERN_ERR "qnap_ts209_pci_preinit failed "
137
137
"to set_irq_type pin %d\n", pin);
+5
-5
arch/arm/mach-pnx4008/irq.c
+5
-5
arch/arm/mach-pnx4008/irq.c
···
58
58
case IRQ_TYPE_EDGE_RISING:
59
59
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
60
60
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
61
-
set_irq_handler(d->irq, handle_edge_irq);
61
+
irq_set_handler(d->irq, handle_edge_irq);
62
62
break;
63
63
case IRQ_TYPE_EDGE_FALLING:
64
64
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
65
65
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
66
-
set_irq_handler(d->irq, handle_edge_irq);
66
+
irq_set_handler(d->irq, handle_edge_irq);
67
67
break;
68
68
case IRQ_TYPE_LEVEL_LOW:
69
69
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
70
70
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
71
-
set_irq_handler(d->irq, handle_level_irq);
71
+
irq_set_handler(d->irq, handle_level_irq);
72
72
break;
73
73
case IRQ_TYPE_LEVEL_HIGH:
74
74
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
75
75
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
76
-
set_irq_handler(d->irq, handle_level_irq);
76
+
irq_set_handler(d->irq, handle_level_irq);
77
77
break;
78
78
79
79
/* IRQ_TYPE_EDGE_BOTH is not supported */
···
98
98
/* configure IRQ's */
99
99
for (i = 0; i < NR_IRQS; i++) {
100
100
set_irq_flags(i, IRQF_VALID);
101
-
set_irq_chip(i, &pnx4008_irq_chip);
101
+
irq_set_chip(i, &pnx4008_irq_chip);
102
102
pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
103
103
}
104
104
+4
-4
arch/arm/mach-pxa/balloon3.c
+4
-4
arch/arm/mach-pxa/balloon3.c
···
527
527
pxa27x_init_irq();
528
528
/* setup extra Balloon3 irqs */
529
529
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
530
-
set_irq_chip(irq, &balloon3_irq_chip);
531
-
set_irq_handler(irq, handle_level_irq);
530
+
irq_set_chip_and_handler(irq, &balloon3_irq_chip,
531
+
handle_level_irq);
532
532
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
533
533
}
534
534
535
-
set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
536
-
set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
535
+
irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
536
+
irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
537
537
538
538
pr_debug("%s: chained handler installed - irq %d automatically "
539
539
"enabled\n", __func__, BALLOON3_AUX_NIRQ);
+3
-2
arch/arm/mach-pxa/cm-x2xx-pci.c
+3
-2
arch/arm/mach-pxa/cm-x2xx-pci.c
···
70
70
71
71
cmx2xx_it8152_irq_gpio = irq_gpio;
72
72
73
-
set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
73
+
irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
74
74
75
-
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux);
75
+
irq_set_chained_handler(gpio_to_irq(irq_gpio),
76
+
cmx2xx_it8152_irq_demux);
76
77
}
77
78
78
79
#ifdef CONFIG_PM
+1
-1
arch/arm/mach-pxa/cm-x300.c
+1
-1
arch/arm/mach-pxa/cm-x300.c
+6
-6
arch/arm/mach-pxa/irq.c
+6
-6
arch/arm/mach-pxa/irq.c
···
137
137
GEDR0 = 0x3;
138
138
139
139
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
140
-
set_irq_chip(irq, &pxa_low_gpio_chip);
141
-
set_irq_chip_data(irq, irq_base(0));
142
-
set_irq_handler(irq, handle_edge_irq);
140
+
irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
141
+
handle_edge_irq);
142
+
irq_set_chip_data(irq, irq_base(0));
143
143
set_irq_flags(irq, IRQF_VALID);
144
144
}
145
145
···
165
165
__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
166
166
167
167
irq = PXA_IRQ(i);
168
-
set_irq_chip(irq, &pxa_internal_irq_chip);
169
-
set_irq_chip_data(irq, base);
170
-
set_irq_handler(irq, handle_level_irq);
168
+
irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
169
+
handle_level_irq);
170
+
irq_set_chip_data(irq, base);
171
171
set_irq_flags(irq, IRQF_VALID);
172
172
}
173
173
}
+4
-4
arch/arm/mach-pxa/lpd270.c
+4
-4
arch/arm/mach-pxa/lpd270.c
···
149
149
150
150
/* setup extra LogicPD PXA270 irqs */
151
151
for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
152
-
set_irq_chip(irq, &lpd270_irq_chip);
153
-
set_irq_handler(irq, handle_level_irq);
152
+
irq_set_chip_and_handler(irq, &lpd270_irq_chip,
153
+
handle_level_irq);
154
154
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
155
155
}
156
-
set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
157
-
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
156
+
irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
157
+
irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
158
158
}
159
159
160
160
+4
-4
arch/arm/mach-pxa/lubbock.c
+4
-4
arch/arm/mach-pxa/lubbock.c
···
165
165
166
166
/* setup extra lubbock irqs */
167
167
for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
168
-
set_irq_chip(irq, &lubbock_irq_chip);
169
-
set_irq_handler(irq, handle_level_irq);
168
+
irq_set_chip_and_handler(irq, &lubbock_irq_chip,
169
+
handle_level_irq);
170
170
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
171
171
}
172
172
173
-
set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
174
-
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
173
+
irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
174
+
irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
175
175
}
176
176
177
177
#ifdef CONFIG_PM
+4
-4
arch/arm/mach-pxa/mainstone.c
+4
-4
arch/arm/mach-pxa/mainstone.c
···
166
166
167
167
/* setup extra Mainstone irqs */
168
168
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
169
-
set_irq_chip(irq, &mainstone_irq_chip);
170
-
set_irq_handler(irq, handle_level_irq);
169
+
irq_set_chip_and_handler(irq, &mainstone_irq_chip,
170
+
handle_level_irq);
171
171
if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
172
172
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
173
173
else
···
179
179
MST_INTMSKENA = 0;
180
180
MST_INTSETCLR = 0;
181
181
182
-
set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
183
-
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
182
+
irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
183
+
irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
184
184
}
185
185
186
186
#ifdef CONFIG_PM
+4
-4
arch/arm/mach-pxa/pcm990-baseboard.c
+4
-4
arch/arm/mach-pxa/pcm990-baseboard.c
···
281
281
282
282
/* setup extra PCM990 irqs */
283
283
for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
284
-
set_irq_chip(irq, &pcm990_irq_chip);
285
-
set_irq_handler(irq, handle_level_irq);
284
+
irq_set_chip_and_handler(irq, &pcm990_irq_chip,
285
+
handle_level_irq);
286
286
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
287
287
}
288
288
289
289
PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
290
290
PCM990_INTSETCLR = 0xFF;
291
291
292
-
set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
293
-
set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
292
+
irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
293
+
irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
294
294
}
295
295
296
296
static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
+2
-2
arch/arm/mach-pxa/pxa3xx.c
+2
-2
arch/arm/mach-pxa/pxa3xx.c
···
362
362
int irq;
363
363
364
364
for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
365
-
set_irq_chip(irq, &pxa_ext_wakeup_chip);
366
-
set_irq_handler(irq, handle_edge_irq);
365
+
irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
366
+
handle_edge_irq);
367
367
set_irq_flags(irq, IRQF_VALID);
368
368
}
369
369
+4
-4
arch/arm/mach-pxa/viper.c
+4
-4
arch/arm/mach-pxa/viper.c
···
310
310
/* setup ISA IRQs */
311
311
for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
312
312
isa_irq = viper_bit_to_irq(level);
313
-
set_irq_chip(isa_irq, &viper_irq_chip);
314
-
set_irq_handler(isa_irq, handle_edge_irq);
313
+
irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
314
+
handle_edge_irq);
315
315
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
316
316
}
317
317
318
-
set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
318
+
irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
319
319
viper_irq_handler);
320
-
set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
320
+
irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
321
321
}
322
322
323
323
/* Flat Panel */
+10
-9
arch/arm/mach-pxa/zeus.c
+10
-9
arch/arm/mach-pxa/zeus.c
···
136
136
137
137
/* Peripheral IRQs. It would be nice to move those inside driver
138
138
configuration, but it is not supported at the moment. */
139
-
set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
140
-
set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
141
-
set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
142
-
set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING);
143
-
set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
139
+
irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
140
+
irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
141
+
irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
142
+
irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
143
+
IRQ_TYPE_EDGE_FALLING);
144
+
irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
144
145
145
146
/* Setup ISA IRQs */
146
147
for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
147
148
isa_irq = zeus_bit_to_irq(level);
148
-
set_irq_chip(isa_irq, &zeus_irq_chip);
149
-
set_irq_handler(isa_irq, handle_edge_irq);
149
+
irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
150
+
handle_edge_irq);
150
151
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
151
152
}
152
153
153
-
set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
154
-
set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
154
+
irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
155
+
irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
155
156
}
156
157
157
158
+7
-7
arch/arm/mach-rpc/irq.c
+7
-7
arch/arm/mach-rpc/irq.c
···
133
133
134
134
switch (irq) {
135
135
case 0 ... 7:
136
-
set_irq_chip(irq, &iomd_a_chip);
137
-
set_irq_handler(irq, handle_level_irq);
136
+
irq_set_chip_and_handler(irq, &iomd_a_chip,
137
+
handle_level_irq);
138
138
set_irq_flags(irq, flags);
139
139
break;
140
140
141
141
case 8 ... 15:
142
-
set_irq_chip(irq, &iomd_b_chip);
143
-
set_irq_handler(irq, handle_level_irq);
142
+
irq_set_chip_and_handler(irq, &iomd_b_chip,
143
+
handle_level_irq);
144
144
set_irq_flags(irq, flags);
145
145
break;
146
146
147
147
case 16 ... 21:
148
-
set_irq_chip(irq, &iomd_dma_chip);
149
-
set_irq_handler(irq, handle_level_irq);
148
+
irq_set_chip_and_handler(irq, &iomd_dma_chip,
149
+
handle_level_irq);
150
150
set_irq_flags(irq, flags);
151
151
break;
152
152
153
153
case 64 ... 71:
154
-
set_irq_chip(irq, &iomd_fiq_chip);
154
+
irq_set_chip(irq, &iomd_fiq_chip);
155
155
set_irq_flags(irq, IRQF_VALID);
156
156
break;
157
157
}
+3
-3
arch/arm/mach-s3c2410/bast-irq.c
+3
-3
arch/arm/mach-s3c2410/bast-irq.c
···
147
147
148
148
__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
149
149
150
-
set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
150
+
irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
151
151
152
152
/* register our IRQs */
153
153
154
154
for (i = 0; i < 4; i++) {
155
155
unsigned int irqno = bast_pc104_irqs[i];
156
156
157
-
set_irq_chip(irqno, &bast_pc104_chip);
158
-
set_irq_handler(irqno, handle_level_irq);
157
+
irq_set_chip_and_handler(irqno, &bast_pc104_chip,
158
+
handle_level_irq);
159
159
set_irq_flags(irqno, IRQF_VALID);
160
160
}
161
161
}
+6
-6
arch/arm/mach-s3c2412/irq.c
+6
-6
arch/arm/mach-s3c2412/irq.c
···
175
175
unsigned int irqno;
176
176
177
177
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
178
-
set_irq_chip(irqno, &s3c2412_irq_eint0t4);
179
-
set_irq_handler(irqno, handle_edge_irq);
178
+
irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
179
+
handle_edge_irq);
180
180
set_irq_flags(irqno, IRQF_VALID);
181
181
}
182
182
183
183
/* add demux support for CF/SDI */
184
184
185
-
set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
185
+
irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
186
186
187
187
for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
188
-
set_irq_chip(irqno, &s3c2412_irq_cfsdi);
189
-
set_irq_handler(irqno, handle_level_irq);
188
+
irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
189
+
handle_level_irq);
190
190
set_irq_flags(irqno, IRQF_VALID);
191
191
}
192
192
···
195
195
s3c2412_irq_rtc_chip = s3c_irq_chip;
196
196
s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
197
197
198
-
set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
198
+
irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
199
199
200
200
return 0;
201
201
}
+3
-5
arch/arm/mach-s3c2416/irq.c
+3
-5
arch/arm/mach-s3c2416/irq.c
···
202
202
{
203
203
unsigned int irqno;
204
204
205
-
set_irq_chip(base, &s3c_irq_level_chip);
206
-
set_irq_handler(base, handle_level_irq);
207
-
set_irq_chained_handler(base, demux);
205
+
irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
206
+
irq_set_chained_handler(base, demux);
208
207
209
208
for (irqno = start; irqno <= end; irqno++) {
210
-
set_irq_chip(irqno, chip);
211
-
set_irq_handler(irqno, handle_level_irq);
209
+
irq_set_chip_and_handler(irqno, chip, handle_level_irq);
212
210
set_irq_flags(irqno, IRQF_VALID);
213
211
}
214
212
+5
-5
arch/arm/mach-s3c2440/irq.c
+5
-5
arch/arm/mach-s3c2440/irq.c
···
100
100
101
101
/* add new chained handler for wdt, ac7 */
102
102
103
-
set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
104
-
set_irq_handler(IRQ_WDT, handle_level_irq);
105
-
set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
103
+
irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
104
+
handle_level_irq);
105
+
irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
106
106
107
107
for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
108
-
set_irq_chip(irqno, &s3c_irq_wdtac97);
109
-
set_irq_handler(irqno, handle_level_irq);
108
+
irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
109
+
handle_level_irq);
110
110
set_irq_flags(irqno, IRQF_VALID);
111
111
}
112
112
+7
-7
arch/arm/mach-s3c2440/s3c244x-irq.c
+7
-7
arch/arm/mach-s3c2440/s3c244x-irq.c
···
95
95
{
96
96
unsigned int irqno;
97
97
98
-
set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
99
-
set_irq_handler(IRQ_NFCON, handle_level_irq);
98
+
irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99
+
handle_level_irq);
100
100
set_irq_flags(IRQ_NFCON, IRQF_VALID);
101
101
102
102
/* add chained handler for camera */
103
103
104
-
set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
105
-
set_irq_handler(IRQ_CAM, handle_level_irq);
106
-
set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
104
+
irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105
+
handle_level_irq);
106
+
irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107
107
108
108
for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109
-
set_irq_chip(irqno, &s3c_irq_cam);
110
-
set_irq_handler(irqno, handle_level_irq);
109
+
irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110
+
handle_level_irq);
111
111
set_irq_flags(irqno, IRQF_VALID);
112
112
}
113
113
+3
-5
arch/arm/mach-s3c2443/irq.c
+3
-5
arch/arm/mach-s3c2443/irq.c
···
230
230
{
231
231
unsigned int irqno;
232
232
233
-
set_irq_chip(base, &s3c_irq_level_chip);
234
-
set_irq_handler(base, handle_level_irq);
235
-
set_irq_chained_handler(base, demux);
233
+
irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
234
+
irq_set_chained_handler(base, demux);
236
235
237
236
for (irqno = start; irqno <= end; irqno++) {
238
-
set_irq_chip(irqno, chip);
239
-
set_irq_handler(irqno, handle_level_irq);
237
+
irq_set_chip_and_handler(irqno, chip, handle_level_irq);
240
238
set_irq_flags(irqno, IRQF_VALID);
241
239
}
242
240
+6
-7
arch/arm/mach-s3c64xx/irq-eint.c
+6
-7
arch/arm/mach-s3c64xx/irq-eint.c
···
197
197
int irq;
198
198
199
199
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
200
-
set_irq_chip(irq, &s3c_irq_eint);
201
-
set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq));
202
-
set_irq_handler(irq, handle_level_irq);
200
+
irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
201
+
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
203
202
set_irq_flags(irq, IRQF_VALID);
204
203
}
205
204
206
-
set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
207
-
set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
208
-
set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
209
-
set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
205
+
irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
206
+
irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
207
+
irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
208
+
irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
210
209
211
210
return 0;
212
211
}
+1
-1
arch/arm/mach-sa1100/cerf.c
+1
-1
arch/arm/mach-sa1100/cerf.c
+8
-8
arch/arm/mach-sa1100/irq.c
+8
-8
arch/arm/mach-sa1100/irq.c
···
323
323
ICCR = 1;
324
324
325
325
for (irq = 0; irq <= 10; irq++) {
326
-
set_irq_chip(irq, &sa1100_low_gpio_chip);
327
-
set_irq_handler(irq, handle_edge_irq);
326
+
irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
327
+
handle_edge_irq);
328
328
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
329
329
}
330
330
331
331
for (irq = 12; irq <= 31; irq++) {
332
-
set_irq_chip(irq, &sa1100_normal_chip);
333
-
set_irq_handler(irq, handle_level_irq);
332
+
irq_set_chip_and_handler(irq, &sa1100_normal_chip,
333
+
handle_level_irq);
334
334
set_irq_flags(irq, IRQF_VALID);
335
335
}
336
336
337
337
for (irq = 32; irq <= 48; irq++) {
338
-
set_irq_chip(irq, &sa1100_high_gpio_chip);
339
-
set_irq_handler(irq, handle_edge_irq);
338
+
irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
339
+
handle_edge_irq);
340
340
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
341
341
}
342
342
343
343
/*
344
344
* Install handler for GPIO 11-27 edge detect interrupts
345
345
*/
346
-
set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
347
-
set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
346
+
irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
347
+
irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
348
348
349
349
sa1100_init_gpio();
350
350
}
+4
-4
arch/arm/mach-sa1100/neponset.c
+4
-4
arch/arm/mach-sa1100/neponset.c
···
145
145
/*
146
146
* Install handler for GPIO25.
147
147
*/
148
-
set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
149
-
set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler);
148
+
irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
149
+
irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler);
150
150
151
151
/*
152
152
* We would set IRQ_GPIO25 to be a wake-up IRQ, but
···
161
161
* Setup other Neponset IRQs. SA1111 will be done by the
162
162
* generic SA1111 code.
163
163
*/
164
-
set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
164
+
irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
165
165
set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
166
-
set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
166
+
irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
167
167
set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
168
168
169
169
/*
+1
-1
arch/arm/mach-sa1100/pleb.c
+1
-1
arch/arm/mach-sa1100/pleb.c
+1
-2
arch/arm/mach-shark/irq.c
+1
-2
arch/arm/mach-shark/irq.c
+2
-2
arch/arm/mach-shmobile/board-ap4evb.c
+2
-2
arch/arm/mach-shmobile/board-ap4evb.c
···
1255
1255
gpio_request(GPIO_FN_KEYIN4, NULL);
1256
1256
1257
1257
/* enable TouchScreen */
1258
-
set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
1258
+
irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
1259
1259
1260
1260
tsc_device.irq = IRQ28;
1261
1261
i2c_register_board_info(1, &tsc_device, 1);
···
1311
1311
lcdc_info.ch[0].lcd_size_cfg.height = 91;
1312
1312
1313
1313
/* enable TouchScreen */
1314
-
set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1314
+
irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1315
1315
1316
1316
tsc_device.irq = IRQ7;
1317
1317
i2c_register_board_info(0, &tsc_device, 1);
+3
-3
arch/arm/mach-shmobile/board-mackerel.c
+3
-3
arch/arm/mach-shmobile/board-mackerel.c
···
1124
1124
1125
1125
/* enable Keypad */
1126
1126
gpio_request(GPIO_FN_IRQ9_42, NULL);
1127
-
set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
1127
+
irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
1128
1128
1129
1129
/* enable Touchscreen */
1130
1130
gpio_request(GPIO_FN_IRQ7_40, NULL);
1131
-
set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1131
+
irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1132
1132
1133
1133
/* enable Accelerometer */
1134
1134
gpio_request(GPIO_FN_IRQ21, NULL);
1135
-
set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1135
+
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1136
1136
1137
1137
/* enable SDHI0 */
1138
1138
gpio_request(GPIO_FN_SDHICD0, NULL);
+3
-3
arch/arm/mach-shmobile/intc-sh7367.c
+3
-3
arch/arm/mach-shmobile/intc-sh7367.c
···
421
421
422
422
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
423
423
{
424
-
void __iomem *reg = (void *)get_irq_data(irq);
424
+
void __iomem *reg = (void *)irq_get_handler_data(irq);
425
425
unsigned int evtcodeas = ioread32(reg);
426
426
427
427
generic_handle_irq(intcs_evt2irq(evtcodeas));
···
435
435
register_intc_controller(&intcs_desc);
436
436
437
437
/* demux using INTEVTSA */
438
-
set_irq_data(evt2irq(0xf80), (void *)intevtsa);
439
-
set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
438
+
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
439
+
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
440
440
}
+3
-3
arch/arm/mach-shmobile/intc-sh7372.c
+3
-3
arch/arm/mach-shmobile/intc-sh7372.c
···
601
601
602
602
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
603
603
{
604
-
void __iomem *reg = (void *)get_irq_data(irq);
604
+
void __iomem *reg = (void *)irq_get_handler_data(irq);
605
605
unsigned int evtcodeas = ioread32(reg);
606
606
607
607
generic_handle_irq(intcs_evt2irq(evtcodeas));
···
615
615
register_intc_controller(&intcs_desc);
616
616
617
617
/* demux using INTEVTSA */
618
-
set_irq_data(evt2irq(0xf80), (void *)intevtsa);
619
-
set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
618
+
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
619
+
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
620
620
}
+3
-3
arch/arm/mach-shmobile/intc-sh7377.c
+3
-3
arch/arm/mach-shmobile/intc-sh7377.c
···
626
626
627
627
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
628
628
{
629
-
void __iomem *reg = (void *)get_irq_data(irq);
629
+
void __iomem *reg = (void *)irq_get_handler_data(irq);
630
630
unsigned int evtcodeas = ioread32(reg);
631
631
632
632
generic_handle_irq(intcs_evt2irq(evtcodeas));
···
641
641
register_intc_controller(&intcs_desc);
642
642
643
643
/* demux using INTEVTSA */
644
-
set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645
-
set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
644
+
irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645
+
irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
646
646
}
+3
-3
arch/arm/mach-tcc8k/irq.c
+3
-3
arch/arm/mach-tcc8k/irq.c
···
102
102
103
103
for (irqno = 0; irqno < NR_IRQS; irqno++) {
104
104
if (irqno < 32)
105
-
set_irq_chip(irqno, &tcc8000_irq_chip0);
105
+
irq_set_chip(irqno, &tcc8000_irq_chip0);
106
106
else
107
-
set_irq_chip(irqno, &tcc8000_irq_chip1);
108
-
set_irq_handler(irqno, handle_level_irq);
107
+
irq_set_chip(irqno, &tcc8000_irq_chip1);
108
+
irq_set_handler(irqno, handle_level_irq);
109
109
set_irq_flags(irqno, IRQF_VALID);
110
110
}
111
111
}
+10
-29
arch/arm/mach-tegra/gpio.c
+10
-29
arch/arm/mach-tegra/gpio.c
···
208
208
spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
209
209
210
210
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
211
-
__set_irq_handler_unlocked(d->irq, handle_level_irq);
211
+
__irq_set_handler_locked(d->irq, handle_level_irq);
212
212
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
213
-
__set_irq_handler_unlocked(d->irq, handle_edge_irq);
213
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
214
214
215
215
return 0;
216
216
}
···
224
224
225
225
desc->irq_data.chip->irq_ack(&desc->irq_data);
226
226
227
-
bank = get_irq_data(irq);
227
+
bank = irq_get_handler_data(irq);
228
228
229
229
for (port = 0; port < 4; port++) {
230
230
int gpio = tegra_gpio_compose(bank->bank, port, 0);
···
275
275
}
276
276
277
277
local_irq_restore(flags);
278
-
279
-
for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
280
-
struct irq_desc *desc = irq_to_desc(i);
281
-
if (!desc || (desc->status & IRQ_WAKEUP))
282
-
continue;
283
-
enable_irq(i);
284
-
}
285
278
}
286
279
287
280
void tegra_gpio_suspend(void)
288
281
{
289
282
unsigned long flags;
290
283
int b, p, i;
291
-
292
-
for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
293
-
struct irq_desc *desc = irq_to_desc(i);
294
-
if (!desc)
295
-
continue;
296
-
if (desc->status & IRQ_WAKEUP) {
297
-
int gpio = i - INT_GPIO_BASE;
298
-
pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7);
299
-
continue;
300
-
}
301
-
disable_irq(i);
302
-
}
303
284
304
285
local_irq_save(flags);
305
286
for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
···
301
320
static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
302
321
{
303
322
struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
304
-
return set_irq_wake(bank->irq, enable);
323
+
return irq_set_irq_wake(bank->irq, enable);
305
324
}
306
325
#endif
307
326
···
340
359
for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
341
360
bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
342
361
343
-
lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class);
344
-
set_irq_chip_data(i, bank);
345
-
set_irq_chip(i, &tegra_gpio_irq_chip);
346
-
set_irq_handler(i, handle_simple_irq);
362
+
irq_set_lockdep_class(i, &gpio_lock_class);
363
+
irq_set_chip_data(i, bank);
364
+
irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
365
+
handle_simple_irq);
347
366
set_irq_flags(i, IRQF_VALID);
348
367
}
349
368
350
369
for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
351
370
bank = &tegra_gpio_banks[i];
352
371
353
-
set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler);
354
-
set_irq_data(bank->irq, bank);
372
+
irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
373
+
irq_set_handler_data(bank->irq, bank);
355
374
356
375
for (j = 0; j < 4; j++)
357
376
spin_lock_init(&bank->lvl_lock[j]);
+2
-3
arch/arm/mach-tegra/irq.c
+2
-3
arch/arm/mach-tegra/irq.c
···
144
144
gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145
145
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146
146
147
-
gic = get_irq_chip(29);
147
+
gic = irq_get_chip(29);
148
148
tegra_gic_unmask_irq = gic->irq_unmask;
149
149
tegra_gic_mask_irq = gic->irq_mask;
150
150
tegra_gic_ack_irq = gic->irq_ack;
···
154
154
155
155
for (i = 0; i < INT_MAIN_NR; i++) {
156
156
irq = INT_PRI_BASE + i;
157
-
set_irq_chip(irq, &tegra_irq);
158
-
set_irq_handler(irq, handle_level_irq);
157
+
irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
159
158
set_irq_flags(irq, IRQF_VALID);
160
159
}
161
160
}
+1
-2
arch/arm/mach-ux500/modem-irq-db5500.c
+1
-2
arch/arm/mach-ux500/modem-irq-db5500.c
···
90
90
91
91
static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
92
92
{
93
-
set_irq_chip(irq, modem_irq_chip);
94
-
set_irq_handler(irq, handle_simple_irq);
93
+
irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
95
94
set_irq_flags(irq, IRQF_VALID);
96
95
97
96
pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
+1
-1
arch/arm/mach-versatile/core.c
+1
-1
arch/arm/mach-versatile/core.c
+7
-7
arch/arm/mach-vt8500/irq.c
+7
-7
arch/arm/mach-vt8500/irq.c
···
97
97
return -EINVAL;
98
98
case IRQF_TRIGGER_HIGH:
99
99
dctr |= VT8500_TRIGGER_HIGH;
100
-
irq_desc[orig_irq].handle_irq = handle_level_irq;
100
+
__irq_set_handler_locked(orig_irq, handle_level_irq);
101
101
break;
102
102
case IRQF_TRIGGER_FALLING:
103
103
dctr |= VT8500_TRIGGER_FALLING;
104
-
irq_desc[orig_irq].handle_irq = handle_edge_irq;
104
+
__irq_set_handler_locked(orig_irq, handle_edge_irq);
105
105
break;
106
106
case IRQF_TRIGGER_RISING:
107
107
dctr |= VT8500_TRIGGER_RISING;
108
-
irq_desc[orig_irq].handle_irq = handle_edge_irq;
108
+
__irq_set_handler_locked(orig_irq, handle_edge_irq);
109
109
break;
110
110
}
111
111
writeb(dctr, base + VT8500_IC_DCTR + irq);
···
136
136
/* Disable all interrupts and route them to IRQ */
137
137
writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
138
138
139
-
set_irq_chip(i, &vt8500_irq_chip);
140
-
set_irq_handler(i, handle_level_irq);
139
+
irq_set_chip_and_handler(i, &vt8500_irq_chip,
140
+
handle_level_irq);
141
141
set_irq_flags(i, IRQF_VALID);
142
142
}
143
143
} else {
···
167
167
writeb(0x00, sic_regbase + VT8500_IC_DCTR
168
168
+ i - 64);
169
169
170
-
set_irq_chip(i, &vt8500_irq_chip);
171
-
set_irq_handler(i, handle_level_irq);
170
+
irq_set_chip_and_handler(i, &vt8500_irq_chip,
171
+
handle_level_irq);
172
172
set_irq_flags(i, IRQF_VALID);
173
173
}
174
174
} else {
+2
-2
arch/arm/mach-w90x900/irq.c
+2
-2
arch/arm/mach-w90x900/irq.c
···
207
207
__raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
208
208
209
209
for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
210
-
set_irq_chip(irqno, &nuc900_irq_chip);
211
-
set_irq_handler(irqno, handle_level_irq);
210
+
irq_set_chip_and_handler(irqno, &nuc900_irq_chip,
211
+
handle_level_irq);
212
212
set_irq_flags(irqno, IRQF_VALID);
213
213
}
214
214
}
+4
-10
arch/arm/plat-mxc/3ds_debugboard.c
+4
-10
arch/arm/plat-mxc/3ds_debugboard.c
···
100
100
101
101
expio_irq = MXC_BOARD_IRQ_START;
102
102
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
103
-
struct irq_desc *d;
104
103
if ((int_valid & 1) == 0)
105
104
continue;
106
-
d = irq_desc + expio_irq;
107
-
if (unlikely(!(d->handle_irq)))
108
-
pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
109
-
else
110
-
d->handle_irq(expio_irq, d);
105
+
generic_handle_irq(expio_irq);
111
106
}
112
107
113
108
desc->irq_data.chip->irq_ack(&desc->irq_data);
···
181
186
__raw_writew(0x1F, brd_io + INTR_MASK_REG);
182
187
for (i = MXC_EXP_IO_BASE;
183
188
i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
184
-
set_irq_chip(i, &expio_irq_chip);
185
-
set_irq_handler(i, handle_level_irq);
189
+
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
186
190
set_irq_flags(i, IRQF_VALID);
187
191
}
188
-
set_irq_type(p_irq, IRQF_TRIGGER_LOW);
189
-
set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
192
+
irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
193
+
irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
190
194
191
195
/* Register Lan device on the debugboard */
192
196
smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+2
-2
arch/arm/plat-mxc/avic.c
+2
-2
arch/arm/plat-mxc/avic.c
···
139
139
__raw_writel(0, avic_base + AVIC_INTTYPEH);
140
140
__raw_writel(0, avic_base + AVIC_INTTYPEL);
141
141
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
142
-
set_irq_chip(i, &mxc_avic_chip.base);
143
-
set_irq_handler(i, handle_level_irq);
142
+
irq_set_chip_and_handler(i, &mxc_avic_chip.base,
143
+
handle_level_irq);
144
144
set_irq_flags(i, IRQF_VALID);
145
145
}
146
146
+13
-11
arch/arm/plat-mxc/gpio.c
+13
-11
arch/arm/plat-mxc/gpio.c
···
175
175
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
176
176
{
177
177
u32 irq_stat;
178
-
struct mxc_gpio_port *port = get_irq_data(irq);
178
+
struct mxc_gpio_port *port = irq_get_handler_data(irq);
179
179
180
180
irq_stat = __raw_readl(port->base + GPIO_ISR) &
181
181
__raw_readl(port->base + GPIO_IMR);
···
188
188
{
189
189
int i;
190
190
u32 irq_msk, irq_stat;
191
-
struct mxc_gpio_port *port = get_irq_data(irq);
191
+
struct mxc_gpio_port *port = irq_get_handler_data(irq);
192
192
193
193
/* walk through all interrupt status registers */
194
194
for (i = 0; i < gpio_table_size; i++) {
···
311
311
__raw_writel(~0, port[i].base + GPIO_ISR);
312
312
for (j = port[i].virtual_irq_start;
313
313
j < port[i].virtual_irq_start + 32; j++) {
314
-
set_irq_chip(j, &gpio_irq_chip);
315
-
set_irq_handler(j, handle_level_irq);
314
+
irq_set_chip_and_handler(j, &gpio_irq_chip,
315
+
handle_level_irq);
316
316
set_irq_flags(j, IRQF_VALID);
317
317
}
318
318
···
331
331
332
332
if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
333
333
/* setup one handler for each entry */
334
-
set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
335
-
set_irq_data(port[i].irq, &port[i]);
334
+
irq_set_chained_handler(port[i].irq,
335
+
mx3_gpio_irq_handler);
336
+
irq_set_handler_data(port[i].irq, &port[i]);
336
337
if (port[i].irq_high) {
337
338
/* setup handler for GPIO 16 to 31 */
338
-
set_irq_chained_handler(port[i].irq_high,
339
-
mx3_gpio_irq_handler);
340
-
set_irq_data(port[i].irq_high, &port[i]);
339
+
irq_set_chained_handler(port[i].irq_high,
340
+
mx3_gpio_irq_handler);
341
+
irq_set_handler_data(port[i].irq_high,
342
+
&port[i]);
341
343
}
342
344
}
343
345
}
344
346
345
347
if (cpu_is_mx2()) {
346
348
/* setup one handler for all GPIO interrupts */
347
-
set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
348
-
set_irq_data(port[0].irq, port);
349
+
irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
350
+
irq_set_handler_data(port[0].irq, port);
349
351
}
350
352
351
353
return 0;
+2
-2
arch/arm/plat-mxc/irq-common.c
+2
-2
arch/arm/plat-mxc/irq-common.c
···
29
29
30
30
ret = -ENOSYS;
31
31
32
-
base = get_irq_chip(irq);
32
+
base = irq_get_chip(irq);
33
33
if (base) {
34
34
chip = container_of(base, struct mxc_irq_chip, base);
35
35
if (chip->set_priority)
···
48
48
49
49
ret = -ENOSYS;
50
50
51
-
base = get_irq_chip(irq);
51
+
base = irq_get_chip(irq);
52
52
if (base) {
53
53
chip = container_of(base, struct mxc_irq_chip, base);
54
54
if (chip->set_irq_fiq)
+2
-2
arch/arm/plat-mxc/tzic.c
+2
-2
arch/arm/plat-mxc/tzic.c
···
167
167
/* all IRQ no FIQ Warning :: No selection */
168
168
169
169
for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
170
-
set_irq_chip(i, &mxc_tzic_chip.base);
171
-
set_irq_handler(i, handle_level_irq);
170
+
irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
171
+
handle_level_irq);
172
172
set_irq_flags(i, IRQF_VALID);
173
173
}
174
174
+27
-30
arch/arm/plat-nomadik/gpio.c
+27
-30
arch/arm/plat-nomadik/gpio.c
···
54
54
u32 rwimsc;
55
55
u32 fwimsc;
56
56
u32 slpm;
57
+
u32 enabled;
57
58
};
58
59
59
60
static struct nmk_gpio_chip *
···
319
318
struct nmk_gpio_chip *nmk_chip;
320
319
int pin = PIN_NUM(cfgs[i]);
321
320
322
-
nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
321
+
nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
323
322
if (!nmk_chip) {
324
323
ret = -EINVAL;
325
324
break;
···
398
397
struct nmk_gpio_chip *nmk_chip;
399
398
unsigned long flags;
400
399
401
-
nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
400
+
nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
402
401
if (!nmk_chip)
403
402
return -EINVAL;
404
403
···
431
430
struct nmk_gpio_chip *nmk_chip;
432
431
unsigned long flags;
433
432
434
-
nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
433
+
nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
435
434
if (!nmk_chip)
436
435
return -EINVAL;
437
436
···
457
456
struct nmk_gpio_chip *nmk_chip;
458
457
unsigned long flags;
459
458
460
-
nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
459
+
nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
461
460
if (!nmk_chip)
462
461
return -EINVAL;
463
462
···
474
473
struct nmk_gpio_chip *nmk_chip;
475
474
u32 afunc, bfunc, bit;
476
475
477
-
nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
476
+
nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
478
477
if (!nmk_chip)
479
478
return -EINVAL;
480
479
···
542
541
static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
543
542
int gpio, bool on)
544
543
{
545
-
#ifdef CONFIG_ARCH_U8500
546
-
if (cpu_is_u8500v2()) {
547
-
__nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
548
-
on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
549
-
: NMK_GPIO_SLPM_WAKEUP_DISABLE);
550
-
}
551
-
#endif
552
544
__nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
553
545
}
554
546
···
557
563
bitmask = nmk_gpio_get_bitmask(gpio);
558
564
if (!nmk_chip)
559
565
return -EINVAL;
566
+
567
+
if (enable)
568
+
nmk_chip->enabled |= bitmask;
569
+
else
570
+
nmk_chip->enabled &= ~bitmask;
560
571
561
572
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
562
573
spin_lock(&nmk_chip->lock);
···
589
590
590
591
static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
591
592
{
592
-
struct irq_desc *desc = irq_to_desc(d->irq);
593
-
bool enabled = !(desc->status & IRQ_DISABLED);
594
593
struct nmk_gpio_chip *nmk_chip;
595
594
unsigned long flags;
596
595
u32 bitmask;
···
603
606
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
604
607
spin_lock(&nmk_chip->lock);
605
608
606
-
if (!enabled)
609
+
if (!(nmk_chip->enabled & bitmask))
607
610
__nmk_gpio_set_wake(nmk_chip, gpio, on);
608
611
609
612
if (on)
···
619
622
620
623
static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
621
624
{
622
-
struct irq_desc *desc = irq_to_desc(d->irq);
623
-
bool enabled = !(desc->status & IRQ_DISABLED);
624
-
bool wake = desc->wake_depth;
625
+
bool enabled, wake = irqd_is_wakeup_set(d);
625
626
int gpio;
626
627
struct nmk_gpio_chip *nmk_chip;
627
628
unsigned long flags;
···
635
640
return -EINVAL;
636
641
if (type & IRQ_TYPE_LEVEL_LOW)
637
642
return -EINVAL;
643
+
644
+
enabled = nmk_chip->enabled & bitmask;
638
645
639
646
spin_lock_irqsave(&nmk_chip->lock, flags);
640
647
···
678
681
u32 status)
679
682
{
680
683
struct nmk_gpio_chip *nmk_chip;
681
-
struct irq_chip *host_chip = get_irq_chip(irq);
684
+
struct irq_chip *host_chip = irq_get_chip(irq);
682
685
unsigned int first_irq;
683
686
684
687
if (host_chip->irq_mask_ack)
···
689
692
host_chip->irq_ack(&desc->irq_data);
690
693
}
691
694
692
-
nmk_chip = get_irq_data(irq);
695
+
nmk_chip = irq_get_handler_data(irq);
693
696
first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
694
697
while (status) {
695
698
int bit = __ffs(status);
···
703
706
704
707
static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
705
708
{
706
-
struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
709
+
struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
707
710
u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
708
711
709
712
__nmk_gpio_irq_handler(irq, desc, status);
···
712
715
static void nmk_gpio_secondary_irq_handler(unsigned int irq,
713
716
struct irq_desc *desc)
714
717
{
715
-
struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
718
+
struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
716
719
u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
717
720
718
721
__nmk_gpio_irq_handler(irq, desc, status);
···
725
728
726
729
first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
727
730
for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
728
-
set_irq_chip(i, &nmk_gpio_irq_chip);
729
-
set_irq_handler(i, handle_edge_irq);
731
+
irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
732
+
handle_edge_irq);
730
733
set_irq_flags(i, IRQF_VALID);
731
-
set_irq_chip_data(i, nmk_chip);
732
-
set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
734
+
irq_set_chip_data(i, nmk_chip);
735
+
irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
733
736
}
734
737
735
-
set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
736
-
set_irq_data(nmk_chip->parent_irq, nmk_chip);
738
+
irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
739
+
irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
737
740
738
741
if (nmk_chip->secondary_parent_irq >= 0) {
739
-
set_irq_chained_handler(nmk_chip->secondary_parent_irq,
742
+
irq_set_chained_handler(nmk_chip->secondary_parent_irq,
740
743
nmk_gpio_secondary_irq_handler);
741
-
set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
744
+
irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
742
745
}
743
746
744
747
return 0;
+11
-20
arch/arm/plat-omap/gpio.c
+11
-20
arch/arm/plat-omap/gpio.c
···
755
755
bank = irq_data_get_irq_chip_data(d);
756
756
spin_lock_irqsave(&bank->lock, flags);
757
757
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758
-
if (retval == 0) {
759
-
struct irq_desc *desc = irq_to_desc(d->irq);
760
-
761
-
desc->status &= ~IRQ_TYPE_SENSE_MASK;
762
-
desc->status |= type;
763
-
}
764
758
spin_unlock_irqrestore(&bank->lock, flags);
765
759
766
760
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
767
-
__set_irq_handler_unlocked(d->irq, handle_level_irq);
761
+
__irq_set_handler_locked(d->irq, handle_level_irq);
768
762
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
769
-
__set_irq_handler_unlocked(d->irq, handle_edge_irq);
763
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
770
764
771
765
return retval;
772
766
}
···
1140
1146
1141
1147
desc->irq_data.chip->irq_ack(&desc->irq_data);
1142
1148
1143
-
bank = get_irq_data(irq);
1149
+
bank = irq_get_handler_data(irq);
1144
1150
#ifdef CONFIG_ARCH_OMAP1
1145
1151
if (bank->method == METHOD_MPUIO)
1146
1152
isr_reg = bank->base +
···
1264
1270
unsigned int gpio = d->irq - IH_GPIO_BASE;
1265
1271
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1266
1272
unsigned int irq_mask = 1 << get_gpio_index(gpio);
1267
-
struct irq_desc *desc = irq_to_desc(d->irq);
1268
-
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1273
+
u32 trigger = irqd_get_trigger_type(d);
1269
1274
1270
1275
if (trigger)
1271
1276
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
···
1665
1672
1666
1673
for (j = bank->virtual_irq_start;
1667
1674
j < bank->virtual_irq_start + bank_width; j++) {
1668
-
struct irq_desc *d = irq_to_desc(j);
1669
-
1670
-
lockdep_set_class(&d->lock, &gpio_lock_class);
1671
-
set_irq_chip_data(j, bank);
1675
+
irq_set_lockdep_class(j, &gpio_lock_class);
1676
+
irq_set_chip_data(j, bank);
1672
1677
if (bank_is_mpuio(bank))
1673
-
set_irq_chip(j, &mpuio_irq_chip);
1678
+
irq_set_chip(j, &mpuio_irq_chip);
1674
1679
else
1675
-
set_irq_chip(j, &gpio_irq_chip);
1676
-
set_irq_handler(j, handle_simple_irq);
1680
+
irq_set_chip(j, &gpio_irq_chip);
1681
+
irq_set_handler(j, handle_simple_irq);
1677
1682
set_irq_flags(j, IRQF_VALID);
1678
1683
}
1679
-
set_irq_chained_handler(bank->irq, gpio_irq_handler);
1680
-
set_irq_data(bank->irq, bank);
1684
+
irq_set_chained_handler(bank->irq, gpio_irq_handler);
1685
+
irq_set_handler_data(bank->irq, bank);
1681
1686
}
1682
1687
1683
1688
static int __devinit omap_gpio_probe(struct platform_device *pdev)
+13
-18
arch/arm/plat-orion/gpio.c
+13
-18
arch/arm/plat-orion/gpio.c
···
324
324
static void gpio_irq_ack(struct irq_data *d)
325
325
{
326
326
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
327
-
int type;
327
+
int type = irqd_get_trigger_type(d);
328
328
329
-
type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
330
329
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
331
330
int pin = d->irq - ochip->secondary_irq_base;
332
331
···
336
337
static void gpio_irq_mask(struct irq_data *d)
337
338
{
338
339
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
339
-
int type;
340
+
int type = irqd_get_trigger_type(d);
340
341
void __iomem *reg;
341
342
int pin;
342
343
343
-
type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
344
344
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
345
345
reg = GPIO_EDGE_MASK(ochip);
346
346
else
···
353
355
static void gpio_irq_unmask(struct irq_data *d)
354
356
{
355
357
struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
356
-
int type;
358
+
int type = irqd_get_trigger_type(d);
357
359
void __iomem *reg;
358
360
int pin;
359
361
360
-
type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
361
362
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
362
363
reg = GPIO_EDGE_MASK(ochip);
363
364
else
···
386
389
* Set edge/level type.
387
390
*/
388
391
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
389
-
set_irq_handler(d->irq, handle_edge_irq);
392
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
390
393
} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
391
-
set_irq_handler(d->irq, handle_level_irq);
394
+
__irq_set_handler_locked(d->irq, handle_level_irq);
392
395
} else {
393
396
printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
394
397
d->irq, type);
···
474
477
for (i = 0; i < ngpio; i++) {
475
478
unsigned int irq = secondary_irq_base + i;
476
479
477
-
set_irq_chip(irq, &orion_gpio_irq_chip);
478
-
set_irq_handler(irq, handle_level_irq);
479
-
set_irq_chip_data(irq, ochip);
480
-
irq_desc[irq].status |= IRQ_LEVEL;
480
+
irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
481
+
handle_level_irq);
482
+
irq_set_chip_data(irq, ochip);
483
+
irq_set_status_flags(irq, IRQ_LEVEL);
481
484
set_irq_flags(irq, IRQF_VALID);
482
485
}
483
486
}
···
485
488
void orion_gpio_irq_handler(int pinoff)
486
489
{
487
490
struct orion_gpio_chip *ochip;
488
-
u32 cause;
491
+
u32 cause, type;
489
492
int i;
490
493
491
494
ochip = orion_gpio_chip_find(pinoff);
···
497
500
498
501
for (i = 0; i < ochip->chip.ngpio; i++) {
499
502
int irq;
500
-
struct irq_desc *desc;
501
503
502
504
irq = ochip->secondary_irq_base + i;
503
505
504
506
if (!(cause & (1 << i)))
505
507
continue;
506
508
507
-
desc = irq_desc + irq;
508
-
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
509
+
type = irqd_get_trigger_type(irq_get_irq_data(irq));
510
+
if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
509
511
/* Swap polarity (race with GPIO line) */
510
512
u32 polarity;
511
513
···
512
516
polarity ^= 1 << i;
513
517
writel(polarity, GPIO_IN_POL(ochip));
514
518
}
515
-
516
-
desc_handle_irq(irq, desc);
519
+
generic_handle_irq(irq);
517
520
}
518
521
}
+4
-4
arch/arm/plat-orion/irq.c
+4
-4
arch/arm/plat-orion/irq.c
···
56
56
for (i = 0; i < 32; i++) {
57
57
unsigned int irq = irq_start + i;
58
58
59
-
set_irq_chip(irq, &orion_irq_chip);
60
-
set_irq_chip_data(irq, maskaddr);
61
-
set_irq_handler(irq, handle_level_irq);
62
-
irq_desc[irq].status |= IRQ_LEVEL;
59
+
irq_set_chip_and_handler(irq, &orion_irq_chip,
60
+
handle_level_irq);
61
+
irq_set_chip_data(irq, maskaddr);
62
+
irq_set_status_flags(irq, IRQ_LEVEL);
63
63
set_irq_flags(irq, IRQF_VALID);
64
64
}
65
65
}
+3
-3
arch/arm/plat-pxa/gpio.c
+3
-3
arch/arm/plat-pxa/gpio.c
···
284
284
}
285
285
286
286
for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
287
-
set_irq_chip(irq, &pxa_muxed_gpio_chip);
288
-
set_irq_handler(irq, handle_edge_irq);
287
+
irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288
+
handle_edge_irq);
289
289
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290
290
}
291
291
292
292
/* Install handler for GPIO>=2 edge detect interrupts */
293
-
set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
293
+
irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
294
294
pxa_muxed_gpio_chip.irq_set_wake = fn;
295
295
}
296
296
+21
-22
arch/arm/plat-s3c24xx/irq.c
+21
-22
arch/arm/plat-s3c24xx/irq.c
···
592
592
case IRQ_UART1:
593
593
case IRQ_UART2:
594
594
case IRQ_ADCPARENT:
595
-
set_irq_chip(irqno, &s3c_irq_level_chip);
596
-
set_irq_handler(irqno, handle_level_irq);
595
+
irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
596
+
handle_level_irq);
597
597
break;
598
598
599
599
case IRQ_RESERVED6:
···
603
603
604
604
default:
605
605
//irqdbf("registering irq %d (s3c irq)\n", irqno);
606
-
set_irq_chip(irqno, &s3c_irq_chip);
607
-
set_irq_handler(irqno, handle_edge_irq);
606
+
irq_set_chip_and_handler(irqno, &s3c_irq_chip,
607
+
handle_edge_irq);
608
608
set_irq_flags(irqno, IRQF_VALID);
609
609
}
610
610
}
611
611
612
612
/* setup the cascade irq handlers */
613
613
614
-
set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
615
-
set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
614
+
irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
615
+
irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
616
616
617
-
set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
618
-
set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
619
-
set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
620
-
set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
617
+
irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
618
+
irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
619
+
irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
620
+
irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
621
621
622
622
/* external interrupts */
623
623
624
624
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
625
625
irqdbf("registering irq %d (ext int)\n", irqno);
626
-
set_irq_chip(irqno, &s3c_irq_eint0t4);
627
-
set_irq_handler(irqno, handle_edge_irq);
626
+
irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
627
+
handle_edge_irq);
628
628
set_irq_flags(irqno, IRQF_VALID);
629
629
}
630
630
631
631
for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
632
632
irqdbf("registering irq %d (extended s3c irq)\n", irqno);
633
-
set_irq_chip(irqno, &s3c_irqext_chip);
634
-
set_irq_handler(irqno, handle_edge_irq);
633
+
irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
634
+
handle_edge_irq);
635
635
set_irq_flags(irqno, IRQF_VALID);
636
636
}
637
637
···
641
641
642
642
for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
643
643
irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
644
-
set_irq_chip(irqno, &s3c_irq_uart0);
645
-
set_irq_handler(irqno, handle_level_irq);
644
+
irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
645
+
handle_level_irq);
646
646
set_irq_flags(irqno, IRQF_VALID);
647
647
}
648
648
649
649
for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
650
650
irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
651
-
set_irq_chip(irqno, &s3c_irq_uart1);
652
-
set_irq_handler(irqno, handle_level_irq);
651
+
irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
652
+
handle_level_irq);
653
653
set_irq_flags(irqno, IRQF_VALID);
654
654
}
655
655
656
656
for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
657
657
irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
658
-
set_irq_chip(irqno, &s3c_irq_uart2);
659
-
set_irq_handler(irqno, handle_level_irq);
658
+
irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
659
+
handle_level_irq);
660
660
set_irq_flags(irqno, IRQF_VALID);
661
661
}
662
662
663
663
for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
664
664
irqdbf("registering irq %d (s3c adc irq)\n", irqno);
665
-
set_irq_chip(irqno, &s3c_irq_adc);
666
-
set_irq_handler(irqno, handle_edge_irq);
665
+
irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
667
666
set_irq_flags(irqno, IRQF_VALID);
668
667
}
669
668
+3
-4
arch/arm/plat-s5p/irq-eint.c
+3
-4
arch/arm/plat-s5p/irq-eint.c
···
205
205
int irq;
206
206
207
207
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
208
-
set_irq_chip(irq, &s5p_irq_vic_eint);
208
+
irq_set_chip(irq, &s5p_irq_vic_eint);
209
209
210
210
for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
211
-
set_irq_chip(irq, &s5p_irq_eint);
212
-
set_irq_handler(irq, handle_level_irq);
211
+
irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
213
212
set_irq_flags(irq, IRQF_VALID);
214
213
}
215
214
216
-
set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
215
+
irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
217
216
return 0;
218
217
}
219
218
+11
-11
arch/arm/plat-s5p/irq-gpioint.c
+11
-11
arch/arm/plat-s5p/irq-gpioint.c
···
43
43
44
44
static int s5p_gpioint_get_offset(struct irq_data *data)
45
45
{
46
-
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
46
+
struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
47
47
return data->irq - chip->irq_base;
48
48
}
49
49
50
50
static void s5p_gpioint_ack(struct irq_data *data)
51
51
{
52
-
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
52
+
struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
53
53
int group, offset, pend_offset;
54
54
unsigned int value;
55
55
···
64
64
65
65
static void s5p_gpioint_mask(struct irq_data *data)
66
66
{
67
-
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
67
+
struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
68
68
int group, offset, mask_offset;
69
69
unsigned int value;
70
70
···
79
79
80
80
static void s5p_gpioint_unmask(struct irq_data *data)
81
81
{
82
-
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
82
+
struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
83
83
int group, offset, mask_offset;
84
84
unsigned int value;
85
85
···
100
100
101
101
static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
102
102
{
103
-
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
103
+
struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
104
104
int group, offset, con_offset;
105
105
unsigned int value;
106
106
···
149
149
150
150
static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
151
151
{
152
-
struct s5p_gpioint_bank *bank = get_irq_data(irq);
152
+
struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
153
153
int group, pend_offset, mask_offset;
154
154
unsigned int pend, mask;
155
155
···
200
200
if (!bank->chips)
201
201
return -ENOMEM;
202
202
203
-
set_irq_chained_handler(bank->irq, s5p_gpioint_handler);
204
-
set_irq_data(bank->irq, bank);
203
+
irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
204
+
irq_set_handler_data(bank->irq, bank);
205
205
bank->handler = s5p_gpioint_handler;
206
206
printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
207
207
bank->irq);
···
219
219
bank->chips[group - bank->start] = chip;
220
220
for (i = 0; i < chip->chip.ngpio; i++) {
221
221
irq = chip->irq_base + i;
222
-
set_irq_chip(irq, &s5p_gpioint);
223
-
set_irq_data(irq, chip);
224
-
set_irq_handler(irq, handle_level_irq);
222
+
irq_set_chip(irq, &s5p_gpioint);
223
+
irq_set_handler_data(irq, chip);
224
+
irq_set_handler(irq, handle_level_irq);
225
225
set_irq_flags(irq, IRQF_VALID);
226
226
}
227
227
return 0;
+4
-6
arch/arm/plat-samsung/irq-uart.c
+4
-6
arch/arm/plat-samsung/irq-uart.c
···
107
107
108
108
static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
109
109
{
110
-
struct irq_desc *desc = irq_to_desc(uirq->parent_irq);
111
110
void __iomem *reg_base = uirq->regs;
112
111
unsigned int irq;
113
112
int offs;
···
117
118
for (offs = 0; offs < 3; offs++) {
118
119
irq = uirq->base_irq + offs;
119
120
120
-
set_irq_chip(irq, &s3c_irq_uart);
121
-
set_irq_chip_data(irq, uirq);
122
-
set_irq_handler(irq, handle_level_irq);
121
+
irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
122
+
irq_set_chip_data(irq, uirq);
123
123
set_irq_flags(irq, IRQF_VALID);
124
124
}
125
125
126
-
desc->irq_data.handler_data = uirq;
127
-
set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
126
+
irq_set_handler_data(uirq->parent_irq, uirq);
127
+
irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
128
128
}
129
129
130
130
/**
+4
-7
arch/arm/plat-samsung/irq-vic-timer.c
+4
-7
arch/arm/plat-samsung/irq-vic-timer.c
···
77
77
void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
78
78
unsigned int timer_irq)
79
79
{
80
-
struct irq_desc *desc = irq_to_desc(parent_irq);
81
80
82
-
set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
81
+
irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
82
+
irq_set_handler_data(parent_irq, (void *)timer_irq);
83
83
84
-
set_irq_chip(timer_irq, &s3c_irq_timer);
85
-
set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
86
-
set_irq_handler(timer_irq, handle_level_irq);
84
+
irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
85
+
irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
87
86
set_irq_flags(timer_irq, IRQF_VALID);
88
-
89
-
desc->irq_data.handler_data = (void *)timer_irq;
90
87
}
+4
-4
arch/arm/plat-samsung/wakeup-mask.c
+4
-4
arch/arm/plat-samsung/wakeup-mask.c
···
22
22
void samsung_sync_wakemask(void __iomem *reg,
23
23
struct samsung_wakeup_mask *mask, int nr_mask)
24
24
{
25
-
struct irq_desc *desc;
25
+
struct irq_data *data;
26
26
u32 val;
27
27
28
28
val = __raw_readl(reg);
···
33
33
continue;
34
34
}
35
35
36
-
desc = irq_to_desc(mask->irq);
36
+
data = irq_get_irq_data(mask->irq);
37
37
38
-
/* bit of a liberty to read this directly from irq_desc. */
39
-
if (desc->wake_depth > 0)
38
+
/* bit of a liberty to read this directly from irq_data. */
39
+
if (irqd_is_wakeup_set(data))
40
40
val &= ~mask->bit;
41
41
else
42
42
val |= mask->bit;
+6
-6
arch/arm/plat-spear/shirq.c
+6
-6
arch/arm/plat-spear/shirq.c
···
68
68
static void shirq_handler(unsigned irq, struct irq_desc *desc)
69
69
{
70
70
u32 i, val, mask;
71
-
struct spear_shirq *shirq = get_irq_data(irq);
71
+
struct spear_shirq *shirq = irq_get_handler_data(irq);
72
72
73
73
desc->irq_data.chip->irq_ack(&desc->irq_data);
74
74
while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
···
105
105
if (!shirq->dev_count)
106
106
return -EINVAL;
107
107
108
-
set_irq_chained_handler(shirq->irq, shirq_handler);
108
+
irq_set_chained_handler(shirq->irq, shirq_handler);
109
109
for (i = 0; i < shirq->dev_count; i++) {
110
-
set_irq_chip(shirq->dev_config[i].virq, &shirq_chip);
111
-
set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq);
110
+
irq_set_chip_and_handler(shirq->dev_config[i].virq,
111
+
&shirq_chip, handle_simple_irq);
112
112
set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
113
-
set_irq_chip_data(shirq->dev_config[i].virq, shirq);
113
+
irq_set_chip_data(shirq->dev_config[i].virq, shirq);
114
114
}
115
115
116
-
set_irq_data(shirq->irq, shirq);
116
+
irq_set_handler_data(shirq->irq, shirq);
117
117
return 0;
118
118
}
+1
-2
arch/arm/plat-stmp3xxx/irq.c
+1
-2
arch/arm/plat-stmp3xxx/irq.c
···
35
35
/* Disable all interrupts initially */
36
36
for (i = 0; i < NR_REAL_IRQS; i++) {
37
37
chip->irq_mask(irq_get_irq_data(i));
38
-
set_irq_chip(i, chip);
39
-
set_irq_handler(i, handle_level_irq);
38
+
irq_set_chip_and_handler(i, chip, handle_level_irq);
40
39
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
41
40
}
42
41
+6
-7
arch/arm/plat-stmp3xxx/pinmux.c
+6
-7
arch/arm/plat-stmp3xxx/pinmux.c
···
489
489
490
490
static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
491
491
{
492
-
struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq);
492
+
struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
493
493
int gpio_irq = pm->virq;
494
494
u32 stat = __raw_readl(pm->irqstat);
495
495
496
496
while (stat) {
497
497
if (stat & 1)
498
-
irq_desc[gpio_irq].handle_irq(gpio_irq,
499
-
&irq_desc[gpio_irq]);
498
+
generic_handle_irq(gpio_irq);
500
499
gpio_irq++;
501
500
stat >>= 1;
502
501
}
···
533
534
534
535
for (virq = pm->virq; virq < pm->virq; virq++) {
535
536
gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
536
-
set_irq_chip(virq, &gpio_irq_chip);
537
-
set_irq_handler(virq, handle_level_irq);
537
+
irq_set_chip_and_handler(virq, &gpio_irq_chip,
538
+
handle_level_irq);
538
539
set_irq_flags(virq, IRQF_VALID);
539
540
}
540
541
r = gpiochip_add(&pm->chip);
541
542
if (r < 0)
542
543
break;
543
-
set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq);
544
-
set_irq_data(pm->irq, pm);
544
+
irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
545
+
irq_set_handler_data(pm->irq, pm);
545
546
}
546
547
return r;
547
548
}
+6
-6
arch/arm/plat-versatile/fpga-irq.c
+6
-6
arch/arm/plat-versatile/fpga-irq.c
···
30
30
31
31
static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
32
32
{
33
-
struct fpga_irq_data *f = get_irq_desc_data(desc);
33
+
struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
34
34
u32 status = readl(f->base + IRQ_STATUS);
35
35
36
36
if (status == 0) {
···
55
55
f->chip.irq_unmask = fpga_irq_unmask;
56
56
57
57
if (parent_irq != -1) {
58
-
set_irq_data(parent_irq, f);
59
-
set_irq_chained_handler(parent_irq, fpga_irq_handle);
58
+
irq_set_handler_data(parent_irq, f);
59
+
irq_set_chained_handler(parent_irq, fpga_irq_handle);
60
60
}
61
61
62
62
for (i = 0; i < 32; i++) {
63
63
if (valid & (1 << i)) {
64
64
unsigned int irq = f->irq_start + i;
65
65
66
-
set_irq_chip_data(irq, f);
67
-
set_irq_chip(irq, &f->chip);
68
-
set_irq_handler(irq, handle_level_irq);
66
+
irq_set_chip_data(irq, f);
67
+
irq_set_chip_and_handler(irq, &f->chip,
68
+
handle_level_irq);
69
69
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
70
70
}
71
71
}
+1
-1
arch/blackfin/kernel/irqchip.c
+1
-1
arch/blackfin/kernel/irqchip.c
···
48
48
seq_printf(p, "%3d: ", i);
49
49
for_each_online_cpu(j)
50
50
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
51
-
seq_printf(p, " %8s", get_irq_desc_chip(desc)->name);
51
+
seq_printf(p, " %8s", irq_desc_get_chip(desc)->name);
52
52
seq_printf(p, " %s", action->name);
53
53
for (action = action->next; action; action = action->next)
54
54
seq_printf(p, " %s", action->name);
+4
-3
arch/blackfin/kernel/trace.c
+4
-3
arch/blackfin/kernel/trace.c
···
912
912
/* if no interrupts are going off, don't print this out */
913
913
if (fp->ipend & ~0x3F) {
914
914
for (i = 0; i < (NR_IRQS - 1); i++) {
915
+
struct irq_desc *desc = irq_to_desc(i);
915
916
if (!in_atomic)
916
-
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
917
+
raw_spin_lock_irqsave(&desc->lock, flags);
917
918
918
-
action = irq_desc[i].action;
919
+
action = desc->action;
919
920
if (!action)
920
921
goto unlock;
921
922
···
929
928
pr_cont("\n");
930
929
unlock:
931
930
if (!in_atomic)
932
-
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
931
+
raw_spin_unlock_irqrestore(&desc->lock, flags);
933
932
}
934
933
}
935
934
+3
-3
arch/blackfin/mach-bf561/smp.c
+3
-3
arch/blackfin/mach-bf561/smp.c
···
154
154
void __cpuinit bfin_local_timer_setup(void)
155
155
{
156
156
#if defined(CONFIG_TICKSOURCE_CORETMR)
157
-
struct irq_chip *chip = get_irq_chip(IRQ_CORETMR);
158
-
struct irq_desc *desc = irq_to_desc(IRQ_CORETMR);
157
+
struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
158
+
struct irq_chip *chip = irq_data_get_irq_chip(data);
159
159
160
160
bfin_coretmr_init();
161
161
bfin_coretmr_clockevent_init();
162
162
163
-
chip->irq_unmask(&desc->irq_data);
163
+
chip->irq_unmask(data);
164
164
#else
165
165
/* Power down the core timer, just to play safe. */
166
166
bfin_write_TCNTL(0);
+20
-23
arch/blackfin/mach-common/ints-priority.c
+20
-23
arch/blackfin/mach-common/ints-priority.c
···
559
559
#ifdef CONFIG_IPIPE
560
560
handle = handle_level_irq;
561
561
#endif
562
-
__set_irq_handler_unlocked(irq, handle);
562
+
__irq_set_handler_locked(irq, handle);
563
563
}
564
564
565
565
static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
···
578
578
static void bfin_gpio_mask_ack_irq(struct irq_data *d)
579
579
{
580
580
unsigned int irq = d->irq;
581
-
struct irq_desc *desc = irq_to_desc(irq);
582
581
u32 gpionr = irq_to_gpio(irq);
583
582
584
-
if (desc->handle_irq == handle_edge_irq)
583
+
if (!irqd_is_level_type(d))
585
584
set_gpio_data(gpionr, 0);
586
585
587
586
set_gpio_maska(gpionr, 0);
···
836
837
837
838
static void bfin_gpio_ack_irq(struct irq_data *d)
838
839
{
839
-
struct irq_desc *desc = irq_to_desc(d->irq);
840
840
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
841
841
u32 pintbit = PINT_BIT(pint_val);
842
842
u32 bank = PINT_2_BANK(pint_val);
843
843
844
-
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
844
+
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
845
845
if (pint[bank]->invert_set & pintbit)
846
846
pint[bank]->invert_clear = pintbit;
847
847
else
···
852
854
853
855
static void bfin_gpio_mask_ack_irq(struct irq_data *d)
854
856
{
855
-
struct irq_desc *desc = irq_to_desc(d->irq);
856
857
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
857
858
u32 pintbit = PINT_BIT(pint_val);
858
859
u32 bank = PINT_2_BANK(pint_val);
859
860
860
-
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
861
+
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
861
862
if (pint[bank]->invert_set & pintbit)
862
863
pint[bank]->invert_clear = pintbit;
863
864
else
···
1163
1166
1164
1167
for (irq = 0; irq <= SYS_IRQS; irq++) {
1165
1168
if (irq <= IRQ_CORETMR)
1166
-
set_irq_chip(irq, &bfin_core_irqchip);
1169
+
irq_set_chip(irq, &bfin_core_irqchip);
1167
1170
else
1168
-
set_irq_chip(irq, &bfin_internal_irqchip);
1171
+
irq_set_chip(irq, &bfin_internal_irqchip);
1169
1172
1170
1173
switch (irq) {
1171
1174
#if defined(CONFIG_BF53x)
···
1189
1192
#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1190
1193
case IRQ_PORTF_INTA:
1191
1194
#endif
1192
-
set_irq_chained_handler(irq,
1193
-
bfin_demux_gpio_irq);
1195
+
irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1194
1196
break;
1195
1197
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1196
1198
case IRQ_GENERIC_ERROR:
1197
-
set_irq_chained_handler(irq, bfin_demux_error_irq);
1199
+
irq_set_chained_handler(irq, bfin_demux_error_irq);
1198
1200
break;
1199
1201
#endif
1200
1202
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1201
1203
case IRQ_MAC_ERROR:
1202
-
set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1204
+
irq_set_chained_handler(irq,
1205
+
bfin_demux_mac_status_irq);
1203
1206
break;
1204
1207
#endif
1205
1208
#ifdef CONFIG_SMP
1206
1209
case IRQ_SUPPLE_0:
1207
1210
case IRQ_SUPPLE_1:
1208
-
set_irq_handler(irq, handle_percpu_irq);
1211
+
irq_set_handler(irq, handle_percpu_irq);
1209
1212
break;
1210
1213
#endif
1211
1214
1212
1215
#ifdef CONFIG_TICKSOURCE_CORETMR
1213
1216
case IRQ_CORETMR:
1214
1217
# ifdef CONFIG_SMP
1215
-
set_irq_handler(irq, handle_percpu_irq);
1218
+
irq_set_handler(irq, handle_percpu_irq);
1216
1219
break;
1217
1220
# else
1218
-
set_irq_handler(irq, handle_simple_irq);
1221
+
irq_set_handler(irq, handle_simple_irq);
1219
1222
break;
1220
1223
# endif
1221
1224
#endif
1222
1225
1223
1226
#ifdef CONFIG_TICKSOURCE_GPTMR0
1224
1227
case IRQ_TIMER0:
1225
-
set_irq_handler(irq, handle_simple_irq);
1228
+
irq_set_handler(irq, handle_simple_irq);
1226
1229
break;
1227
1230
#endif
1228
1231
1229
1232
#ifdef CONFIG_IPIPE
1230
1233
default:
1231
-
set_irq_handler(irq, handle_level_irq);
1234
+
irq_set_handler(irq, handle_level_irq);
1232
1235
break;
1233
1236
#else /* !CONFIG_IPIPE */
1234
1237
default:
1235
-
set_irq_handler(irq, handle_simple_irq);
1238
+
irq_set_handler(irq, handle_simple_irq);
1236
1239
break;
1237
1240
#endif /* !CONFIG_IPIPE */
1238
1241
}
···
1240
1243
1241
1244
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1242
1245
for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1243
-
set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1246
+
irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
1244
1247
handle_level_irq);
1245
1248
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1246
-
set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1249
+
irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1247
1250
#endif
1248
1251
#endif
1249
1252
1250
1253
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1251
1254
for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1252
-
set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1255
+
irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1253
1256
handle_level_irq);
1254
1257
#endif
1255
1258
/* if configured as edge, then will be changed to do_edge_IRQ */
1256
1259
for (irq = GPIO_IRQ_BASE;
1257
1260
irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1258
-
set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1261
+
irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1259
1262
handle_level_irq);
1260
1263
1261
1264
bfin_write_IMASK(0);
+2
arch/frv/Kconfig
+2
arch/frv/Kconfig
+14
-14
arch/frv/kernel/irq-mb93091.c
+14
-14
arch/frv/kernel/irq-mb93091.c
···
36
36
/*
37
37
* on-motherboard FPGA PIC operations
38
38
*/
39
-
static void frv_fpga_mask(unsigned int irq)
39
+
static void frv_fpga_mask(struct irq_data *d)
40
40
{
41
41
uint16_t imr = __get_IMR();
42
42
43
-
imr |= 1 << (irq - IRQ_BASE_FPGA);
43
+
imr |= 1 << (d->irq - IRQ_BASE_FPGA);
44
44
45
45
__set_IMR(imr);
46
46
}
47
47
48
-
static void frv_fpga_ack(unsigned int irq)
48
+
static void frv_fpga_ack(struct irq_data *d)
49
49
{
50
50
__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
51
51
}
52
52
53
-
static void frv_fpga_mask_ack(unsigned int irq)
53
+
static void frv_fpga_mask_ack(struct irq_data *d)
54
54
{
55
55
uint16_t imr = __get_IMR();
56
56
57
-
imr |= 1 << (irq - IRQ_BASE_FPGA);
57
+
imr |= 1 << (d->irq - IRQ_BASE_FPGA);
58
58
__set_IMR(imr);
59
59
60
-
__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
60
+
__clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
61
61
}
62
62
63
-
static void frv_fpga_unmask(unsigned int irq)
63
+
static void frv_fpga_unmask(struct irq_data *d)
64
64
{
65
65
uint16_t imr = __get_IMR();
66
66
67
-
imr &= ~(1 << (irq - IRQ_BASE_FPGA));
67
+
imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
68
68
69
69
__set_IMR(imr);
70
70
}
71
71
72
72
static struct irq_chip frv_fpga_pic = {
73
73
.name = "mb93091",
74
-
.ack = frv_fpga_ack,
75
-
.mask = frv_fpga_mask,
76
-
.mask_ack = frv_fpga_mask_ack,
77
-
.unmask = frv_fpga_unmask,
74
+
.irq_ack = frv_fpga_ack,
75
+
.irq_mask = frv_fpga_mask,
76
+
.irq_mask_ack = frv_fpga_mask_ack,
77
+
.irq_unmask = frv_fpga_unmask,
78
78
};
79
79
80
80
/*
···
146
146
__clr_IFR(0x0000);
147
147
148
148
for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
149
-
set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
149
+
irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
150
150
151
-
set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
151
+
irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
152
152
153
153
/* the FPGA drives the first four external IRQ inputs on the CPU PIC */
154
154
setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
+15
-16
arch/frv/kernel/irq-mb93093.c
+15
-16
arch/frv/kernel/irq-mb93093.c
···
35
35
/*
36
36
* off-CPU FPGA PIC operations
37
37
*/
38
-
static void frv_fpga_mask(unsigned int irq)
38
+
static void frv_fpga_mask(struct irq_data *d)
39
39
{
40
40
uint16_t imr = __get_IMR();
41
41
42
-
imr |= 1 << (irq - IRQ_BASE_FPGA);
42
+
imr |= 1 << (d->irq - IRQ_BASE_FPGA);
43
43
__set_IMR(imr);
44
44
}
45
45
46
-
static void frv_fpga_ack(unsigned int irq)
46
+
static void frv_fpga_ack(struct irq_data *d)
47
47
{
48
-
__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
48
+
__clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
49
49
}
50
50
51
-
static void frv_fpga_mask_ack(unsigned int irq)
51
+
static void frv_fpga_mask_ack(struct irq_data *d)
52
52
{
53
53
uint16_t imr = __get_IMR();
54
54
55
-
imr |= 1 << (irq - IRQ_BASE_FPGA);
55
+
imr |= 1 << (d->irq - IRQ_BASE_FPGA);
56
56
__set_IMR(imr);
57
57
58
-
__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
58
+
__clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
59
59
}
60
60
61
-
static void frv_fpga_unmask(unsigned int irq)
61
+
static void frv_fpga_unmask(struct irq_data *d)
62
62
{
63
63
uint16_t imr = __get_IMR();
64
64
65
-
imr &= ~(1 << (irq - IRQ_BASE_FPGA));
65
+
imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
66
66
67
67
__set_IMR(imr);
68
68
}
69
69
70
70
static struct irq_chip frv_fpga_pic = {
71
71
.name = "mb93093",
72
-
.ack = frv_fpga_ack,
73
-
.mask = frv_fpga_mask,
74
-
.mask_ack = frv_fpga_mask_ack,
75
-
.unmask = frv_fpga_unmask,
76
-
.end = frv_fpga_end,
72
+
.irq_ack = frv_fpga_ack,
73
+
.irq_mask = frv_fpga_mask,
74
+
.irq_mask_ack = frv_fpga_mask_ack,
75
+
.irq_unmask = frv_fpga_unmask,
77
76
};
78
77
79
78
/*
···
93
94
irq = 31 - irq;
94
95
mask &= ~(1 << irq);
95
96
96
-
generic_irq_handle(IRQ_BASE_FPGA + irq);
97
+
generic_handle_irq(IRQ_BASE_FPGA + irq);
97
98
}
98
99
99
100
return IRQ_HANDLED;
···
124
125
__clr_IFR(0x0000);
125
126
126
127
for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
127
-
set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
128
+
irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
128
129
129
130
/* the FPGA drives external IRQ input #2 on the CPU PIC */
130
131
setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
+13
-12
arch/frv/kernel/irq-mb93493.c
+13
-12
arch/frv/kernel/irq-mb93493.c
···
45
45
* daughter board PIC operations
46
46
* - there is no way to ACK interrupts in the MB93493 chip
47
47
*/
48
-
static void frv_mb93493_mask(unsigned int irq)
48
+
static void frv_mb93493_mask(struct irq_data *d)
49
49
{
50
50
uint32_t iqsr;
51
51
volatile void *piqsr;
52
52
53
-
if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
53
+
if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
54
54
piqsr = __addr_MB93493_IQSR(1);
55
55
else
56
56
piqsr = __addr_MB93493_IQSR(0);
57
57
58
58
iqsr = readl(piqsr);
59
-
iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16));
59
+
iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16));
60
60
writel(iqsr, piqsr);
61
61
}
62
62
63
-
static void frv_mb93493_ack(unsigned int irq)
63
+
static void frv_mb93493_ack(struct irq_data *d)
64
64
{
65
65
}
66
66
67
-
static void frv_mb93493_unmask(unsigned int irq)
67
+
static void frv_mb93493_unmask(struct irq_data *d)
68
68
{
69
69
uint32_t iqsr;
70
70
volatile void *piqsr;
71
71
72
-
if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
72
+
if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
73
73
piqsr = __addr_MB93493_IQSR(1);
74
74
else
75
75
piqsr = __addr_MB93493_IQSR(0);
76
76
77
77
iqsr = readl(piqsr);
78
-
iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16);
78
+
iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16);
79
79
writel(iqsr, piqsr);
80
80
}
81
81
82
82
static struct irq_chip frv_mb93493_pic = {
83
83
.name = "mb93093",
84
-
.ack = frv_mb93493_ack,
85
-
.mask = frv_mb93493_mask,
86
-
.mask_ack = frv_mb93493_mask,
87
-
.unmask = frv_mb93493_unmask,
84
+
.irq_ack = frv_mb93493_ack,
85
+
.irq_mask = frv_mb93493_mask,
86
+
.irq_mask_ack = frv_mb93493_mask,
87
+
.irq_unmask = frv_mb93493_unmask,
88
88
};
89
89
90
90
/*
···
139
139
int irq;
140
140
141
141
for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
142
-
set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq);
142
+
irq_set_chip_and_handler(irq, &frv_mb93493_pic,
143
+
handle_edge_irq);
143
144
144
145
/* the MB93493 drives external IRQ inputs on the CPU PIC */
145
146
setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
+18
-62
arch/frv/kernel/irq.c
+18
-62
arch/frv/kernel/irq.c
···
47
47
48
48
atomic_t irq_err_count;
49
49
50
-
/*
51
-
* Generic, controller-independent functions:
52
-
*/
53
-
int show_interrupts(struct seq_file *p, void *v)
50
+
int arch_show_interrupts(struct seq_file *p, int prec)
54
51
{
55
-
int i = *(loff_t *) v, cpu;
56
-
struct irqaction * action;
57
-
unsigned long flags;
58
-
59
-
if (i == 0) {
60
-
char cpuname[12];
61
-
62
-
seq_printf(p, " ");
63
-
for_each_present_cpu(cpu) {
64
-
sprintf(cpuname, "CPU%d", cpu);
65
-
seq_printf(p, " %10s", cpuname);
66
-
}
67
-
seq_putc(p, '\n');
68
-
}
69
-
70
-
if (i < NR_IRQS) {
71
-
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
72
-
action = irq_desc[i].action;
73
-
if (action) {
74
-
seq_printf(p, "%3d: ", i);
75
-
for_each_present_cpu(cpu)
76
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
77
-
seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
78
-
seq_printf(p, " %s", action->name);
79
-
for (action = action->next;
80
-
action;
81
-
action = action->next)
82
-
seq_printf(p, ", %s", action->name);
83
-
84
-
seq_putc(p, '\n');
85
-
}
86
-
87
-
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
88
-
} else if (i == NR_IRQS) {
89
-
seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
90
-
}
91
-
52
+
seq_printf(p, "%*s: ", prec, "ERR");
53
+
seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
92
54
return 0;
93
55
}
94
56
95
57
/*
96
58
* on-CPU PIC operations
97
59
*/
98
-
static void frv_cpupic_ack(unsigned int irqlevel)
60
+
static void frv_cpupic_ack(struct irq_data *d)
99
61
{
100
-
__clr_RC(irqlevel);
62
+
__clr_RC(d->irq);
101
63
__clr_IRL();
102
64
}
103
65
104
-
static void frv_cpupic_mask(unsigned int irqlevel)
66
+
static void frv_cpupic_mask(struct irq_data *d)
105
67
{
106
-
__set_MASK(irqlevel);
68
+
__set_MASK(d->irq);
107
69
}
108
70
109
-
static void frv_cpupic_mask_ack(unsigned int irqlevel)
71
+
static void frv_cpupic_mask_ack(struct irq_data *d)
110
72
{
111
-
__set_MASK(irqlevel);
112
-
__clr_RC(irqlevel);
73
+
__set_MASK(d->irq);
74
+
__clr_RC(d->irq);
113
75
__clr_IRL();
114
76
}
115
77
116
-
static void frv_cpupic_unmask(unsigned int irqlevel)
78
+
static void frv_cpupic_unmask(struct irq_data *d)
117
79
{
118
-
__clr_MASK(irqlevel);
119
-
}
120
-
121
-
static void frv_cpupic_end(unsigned int irqlevel)
122
-
{
123
-
__clr_MASK(irqlevel);
80
+
__clr_MASK(d->irq);
124
81
}
125
82
126
83
static struct irq_chip frv_cpu_pic = {
127
84
.name = "cpu",
128
-
.ack = frv_cpupic_ack,
129
-
.mask = frv_cpupic_mask,
130
-
.mask_ack = frv_cpupic_mask_ack,
131
-
.unmask = frv_cpupic_unmask,
132
-
.end = frv_cpupic_end,
85
+
.irq_ack = frv_cpupic_ack,
86
+
.irq_mask = frv_cpupic_mask,
87
+
.irq_mask_ack = frv_cpupic_mask_ack,
88
+
.irq_unmask = frv_cpupic_unmask,
133
89
};
134
90
135
91
/*
···
117
161
int level;
118
162
119
163
for (level = 1; level <= 14; level++)
120
-
set_irq_chip_and_handler(level, &frv_cpu_pic,
164
+
irq_set_chip_and_handler(level, &frv_cpu_pic,
121
165
handle_level_irq);
122
166
123
-
set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq);
167
+
irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
124
168
125
169
/* set the trigger levels for internal interrupt sources
126
170
* - timers all falling-edge
+1
arch/ia64/Kconfig
+1
arch/ia64/Kconfig
+15
-16
arch/ia64/hp/sim/hpsim_irq.c
+15
-16
arch/ia64/hp/sim/hpsim_irq.c
···
11
11
#include <linux/irq.h>
12
12
13
13
static unsigned int
14
-
hpsim_irq_startup (unsigned int irq)
14
+
hpsim_irq_startup(struct irq_data *data)
15
15
{
16
16
return 0;
17
17
}
18
18
19
19
static void
20
-
hpsim_irq_noop (unsigned int irq)
20
+
hpsim_irq_noop(struct irq_data *data)
21
21
{
22
22
}
23
23
24
24
static int
25
-
hpsim_set_affinity_noop(unsigned int a, const struct cpumask *b)
25
+
hpsim_set_affinity_noop(struct irq_data *d, const struct cpumask *b, bool f)
26
26
{
27
27
return 0;
28
28
}
29
29
30
30
static struct irq_chip irq_type_hp_sim = {
31
-
.name = "hpsim",
32
-
.startup = hpsim_irq_startup,
33
-
.shutdown = hpsim_irq_noop,
34
-
.enable = hpsim_irq_noop,
35
-
.disable = hpsim_irq_noop,
36
-
.ack = hpsim_irq_noop,
37
-
.end = hpsim_irq_noop,
38
-
.set_affinity = hpsim_set_affinity_noop,
31
+
.name = "hpsim",
32
+
.irq_startup = hpsim_irq_startup,
33
+
.irq_shutdown = hpsim_irq_noop,
34
+
.irq_enable = hpsim_irq_noop,
35
+
.irq_disable = hpsim_irq_noop,
36
+
.irq_ack = hpsim_irq_noop,
37
+
.irq_set_affinity = hpsim_set_affinity_noop,
39
38
};
40
39
41
40
void __init
42
41
hpsim_irq_init (void)
43
42
{
44
-
struct irq_desc *idesc;
45
43
int i;
46
44
47
-
for (i = 0; i < NR_IRQS; ++i) {
48
-
idesc = irq_desc + i;
49
-
if (idesc->chip == &no_irq_chip)
50
-
idesc->chip = &irq_type_hp_sim;
45
+
for_each_active_irq(i) {
46
+
struct irq_chip *chip = irq_get_chip(i);
47
+
48
+
if (chip == &no_irq_chip)
49
+
irq_set_chip(i, &irq_type_hp_sim);
51
50
}
52
51
}
-3
arch/ia64/include/asm/hw_irq.h
-3
arch/ia64/include/asm/hw_irq.h
+55
-64
arch/ia64/kernel/iosapic.c
+55
-64
arch/ia64/kernel/iosapic.c
···
257
257
}
258
258
259
259
static void
260
-
nop (unsigned int irq)
260
+
nop (struct irq_data *data)
261
261
{
262
262
/* do nothing... */
263
263
}
···
287
287
#endif
288
288
289
289
static void
290
-
mask_irq (unsigned int irq)
290
+
mask_irq (struct irq_data *data)
291
291
{
292
+
unsigned int irq = data->irq;
292
293
u32 low32;
293
294
int rte_index;
294
295
struct iosapic_rte_info *rte;
···
306
305
}
307
306
308
307
static void
309
-
unmask_irq (unsigned int irq)
308
+
unmask_irq (struct irq_data *data)
310
309
{
310
+
unsigned int irq = data->irq;
311
311
u32 low32;
312
312
int rte_index;
313
313
struct iosapic_rte_info *rte;
···
325
323
326
324
327
325
static int
328
-
iosapic_set_affinity(unsigned int irq, const struct cpumask *mask)
326
+
iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
327
+
bool force)
329
328
{
330
329
#ifdef CONFIG_SMP
330
+
unsigned int irq = data->irq;
331
331
u32 high32, low32;
332
332
int cpu, dest, rte_index;
333
333
int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
···
383
379
*/
384
380
385
381
static unsigned int
386
-
iosapic_startup_level_irq (unsigned int irq)
382
+
iosapic_startup_level_irq (struct irq_data *data)
387
383
{
388
-
unmask_irq(irq);
384
+
unmask_irq(data);
389
385
return 0;
390
386
}
391
387
392
388
static void
393
-
iosapic_unmask_level_irq (unsigned int irq)
389
+
iosapic_unmask_level_irq (struct irq_data *data)
394
390
{
391
+
unsigned int irq = data->irq;
395
392
ia64_vector vec = irq_to_vector(irq);
396
393
struct iosapic_rte_info *rte;
397
394
int do_unmask_irq = 0;
398
395
399
396
irq_complete_move(irq);
400
-
if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
397
+
if (unlikely(irqd_is_setaffinity_pending(data))) {
401
398
do_unmask_irq = 1;
402
-
mask_irq(irq);
399
+
mask_irq(data);
403
400
} else
404
-
unmask_irq(irq);
401
+
unmask_irq(data);
405
402
406
403
list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
407
404
iosapic_eoi(rte->iosapic->addr, vec);
408
405
409
406
if (unlikely(do_unmask_irq)) {
410
-
move_masked_irq(irq);
411
-
unmask_irq(irq);
407
+
irq_move_masked_irq(data);
408
+
unmask_irq(data);
412
409
}
413
410
}
414
411
···
419
414
#define iosapic_ack_level_irq nop
420
415
421
416
static struct irq_chip irq_type_iosapic_level = {
422
-
.name = "IO-SAPIC-level",
423
-
.startup = iosapic_startup_level_irq,
424
-
.shutdown = iosapic_shutdown_level_irq,
425
-
.enable = iosapic_enable_level_irq,
426
-
.disable = iosapic_disable_level_irq,
427
-
.ack = iosapic_ack_level_irq,
428
-
.mask = mask_irq,
429
-
.unmask = iosapic_unmask_level_irq,
430
-
.set_affinity = iosapic_set_affinity
417
+
.name = "IO-SAPIC-level",
418
+
.irq_startup = iosapic_startup_level_irq,
419
+
.irq_shutdown = iosapic_shutdown_level_irq,
420
+
.irq_enable = iosapic_enable_level_irq,
421
+
.irq_disable = iosapic_disable_level_irq,
422
+
.irq_ack = iosapic_ack_level_irq,
423
+
.irq_mask = mask_irq,
424
+
.irq_unmask = iosapic_unmask_level_irq,
425
+
.irq_set_affinity = iosapic_set_affinity
431
426
};
432
427
433
428
/*
···
435
430
*/
436
431
437
432
static unsigned int
438
-
iosapic_startup_edge_irq (unsigned int irq)
433
+
iosapic_startup_edge_irq (struct irq_data *data)
439
434
{
440
-
unmask_irq(irq);
435
+
unmask_irq(data);
441
436
/*
442
437
* IOSAPIC simply drops interrupts pended while the
443
438
* corresponding pin was masked, so we can't know if an
···
447
442
}
448
443
449
444
static void
450
-
iosapic_ack_edge_irq (unsigned int irq)
445
+
iosapic_ack_edge_irq (struct irq_data *data)
451
446
{
452
-
struct irq_desc *idesc = irq_desc + irq;
453
-
454
-
irq_complete_move(irq);
455
-
move_native_irq(irq);
456
-
/*
457
-
* Once we have recorded IRQ_PENDING already, we can mask the
458
-
* interrupt for real. This prevents IRQ storms from unhandled
459
-
* devices.
460
-
*/
461
-
if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
462
-
(IRQ_PENDING|IRQ_DISABLED))
463
-
mask_irq(irq);
447
+
irq_complete_move(data->irq);
448
+
irq_move_irq(data);
464
449
}
465
450
466
451
#define iosapic_enable_edge_irq unmask_irq
467
452
#define iosapic_disable_edge_irq nop
468
-
#define iosapic_end_edge_irq nop
469
453
470
454
static struct irq_chip irq_type_iosapic_edge = {
471
-
.name = "IO-SAPIC-edge",
472
-
.startup = iosapic_startup_edge_irq,
473
-
.shutdown = iosapic_disable_edge_irq,
474
-
.enable = iosapic_enable_edge_irq,
475
-
.disable = iosapic_disable_edge_irq,
476
-
.ack = iosapic_ack_edge_irq,
477
-
.end = iosapic_end_edge_irq,
478
-
.mask = mask_irq,
479
-
.unmask = unmask_irq,
480
-
.set_affinity = iosapic_set_affinity
455
+
.name = "IO-SAPIC-edge",
456
+
.irq_startup = iosapic_startup_edge_irq,
457
+
.irq_shutdown = iosapic_disable_edge_irq,
458
+
.irq_enable = iosapic_enable_edge_irq,
459
+
.irq_disable = iosapic_disable_edge_irq,
460
+
.irq_ack = iosapic_ack_edge_irq,
461
+
.irq_mask = mask_irq,
462
+
.irq_unmask = unmask_irq,
463
+
.irq_set_affinity = iosapic_set_affinity
481
464
};
482
465
483
466
static unsigned int
···
555
562
register_intr (unsigned int gsi, int irq, unsigned char delivery,
556
563
unsigned long polarity, unsigned long trigger)
557
564
{
558
-
struct irq_desc *idesc;
559
-
struct irq_chip *irq_type;
565
+
struct irq_chip *chip, *irq_type;
560
566
int index;
561
567
struct iosapic_rte_info *rte;
562
568
···
602
610
603
611
irq_type = iosapic_get_irq_chip(trigger);
604
612
605
-
idesc = irq_desc + irq;
606
-
if (irq_type != NULL && idesc->chip != irq_type) {
607
-
if (idesc->chip != &no_irq_chip)
613
+
chip = irq_get_chip(irq);
614
+
if (irq_type != NULL && chip != irq_type) {
615
+
if (chip != &no_irq_chip)
608
616
printk(KERN_WARNING
609
617
"%s: changing vector %d from %s to %s\n",
610
618
__func__, irq_to_vector(irq),
611
-
idesc->chip->name, irq_type->name);
612
-
idesc->chip = irq_type;
619
+
chip->name, irq_type->name);
620
+
chip = irq_type;
613
621
}
614
-
if (trigger == IOSAPIC_EDGE)
615
-
__set_irq_handler_unlocked(irq, handle_edge_irq);
616
-
else
617
-
__set_irq_handler_unlocked(irq, handle_level_irq);
622
+
__irq_set_chip_handler_name_locked(irq, chip, trigger == IOSAPIC_EDGE ?
623
+
handle_edge_irq : handle_level_irq,
624
+
NULL);
618
625
return 0;
619
626
}
620
627
···
723
732
struct iosapic_rte_info *rte;
724
733
u32 low32;
725
734
unsigned char dmode;
735
+
struct irq_desc *desc;
726
736
727
737
/*
728
738
* If this GSI has already been registered (i.e., it's a
···
751
759
goto unlock_iosapic_lock;
752
760
}
753
761
754
-
raw_spin_lock(&irq_desc[irq].lock);
762
+
desc = irq_to_desc(irq);
763
+
raw_spin_lock(&desc->lock);
755
764
dest = get_target_cpu(gsi, irq);
756
765
dmode = choose_dmode();
757
766
err = register_intr(gsi, irq, dmode, polarity, trigger);
758
767
if (err < 0) {
759
-
raw_spin_unlock(&irq_desc[irq].lock);
768
+
raw_spin_unlock(&desc->lock);
760
769
irq = err;
761
770
goto unlock_iosapic_lock;
762
771
}
···
776
783
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
777
784
cpu_logical_id(dest), dest, irq_to_vector(irq));
778
785
779
-
raw_spin_unlock(&irq_desc[irq].lock);
786
+
raw_spin_unlock(&desc->lock);
780
787
unlock_iosapic_lock:
781
788
spin_unlock_irqrestore(&iosapic_lock, flags);
782
789
return irq;
···
787
794
{
788
795
unsigned long flags;
789
796
int irq, index;
790
-
struct irq_desc *idesc;
791
797
u32 low32;
792
798
unsigned long trigger, polarity;
793
799
unsigned int dest;
···
816
824
if (--rte->refcnt > 0)
817
825
goto out;
818
826
819
-
idesc = irq_desc + irq;
820
827
rte->refcnt = NO_REF_RTE;
821
828
822
829
/* Mask the interrupt */
···
839
848
if (iosapic_intr_info[irq].count == 0) {
840
849
#ifdef CONFIG_SMP
841
850
/* Clear affinity */
842
-
cpumask_setall(idesc->affinity);
851
+
cpumask_setall(irq_get_irq_data(irq)->affinity);
843
852
#endif
844
853
/* Clear the interrupt information */
845
854
iosapic_intr_info[irq].dest = 0;
+18
-55
arch/ia64/kernel/irq.c
+18
-55
arch/ia64/kernel/irq.c
···
53
53
/*
54
54
* /proc/interrupts printing:
55
55
*/
56
-
57
-
int show_interrupts(struct seq_file *p, void *v)
56
+
int arch_show_interrupts(struct seq_file *p, int prec)
58
57
{
59
-
int i = *(loff_t *) v, j;
60
-
struct irqaction * action;
61
-
unsigned long flags;
62
-
63
-
if (i == 0) {
64
-
char cpuname[16];
65
-
seq_printf(p, " ");
66
-
for_each_online_cpu(j) {
67
-
snprintf(cpuname, 10, "CPU%d", j);
68
-
seq_printf(p, "%10s ", cpuname);
69
-
}
70
-
seq_putc(p, '\n');
71
-
}
72
-
73
-
if (i < NR_IRQS) {
74
-
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
75
-
action = irq_desc[i].action;
76
-
if (!action)
77
-
goto skip;
78
-
seq_printf(p, "%3d: ",i);
79
-
#ifndef CONFIG_SMP
80
-
seq_printf(p, "%10u ", kstat_irqs(i));
81
-
#else
82
-
for_each_online_cpu(j) {
83
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
84
-
}
85
-
#endif
86
-
seq_printf(p, " %14s", irq_desc[i].chip->name);
87
-
seq_printf(p, " %s", action->name);
88
-
89
-
for (action=action->next; action; action = action->next)
90
-
seq_printf(p, ", %s", action->name);
91
-
92
-
seq_putc(p, '\n');
93
-
skip:
94
-
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
95
-
} else if (i == NR_IRQS)
96
-
seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
58
+
seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
97
59
return 0;
98
60
}
99
61
···
65
103
void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
66
104
{
67
105
if (irq < NR_IRQS) {
68
-
cpumask_copy(irq_desc[irq].affinity,
106
+
cpumask_copy(irq_get_irq_data(irq)->affinity,
69
107
cpumask_of(cpu_logical_id(hwid)));
70
108
irq_redir[irq] = (char) (redir & 0xff);
71
109
}
···
92
130
*/
93
131
static void migrate_irqs(void)
94
132
{
95
-
struct irq_desc *desc;
96
133
int irq, new_cpu;
97
134
98
135
for (irq=0; irq < NR_IRQS; irq++) {
99
-
desc = irq_desc + irq;
136
+
struct irq_desc *desc = irq_to_desc(irq);
137
+
struct irq_data *data = irq_desc_get_irq_data(desc);
138
+
struct irq_chip *chip = irq_data_get_irq_chip(data);
100
139
101
-
if (desc->status == IRQ_DISABLED)
140
+
if (irqd_irq_disabled(data))
102
141
continue;
103
142
104
143
/*
···
108
145
* tell CPU not to respond to these local intr sources.
109
146
* such as ITV,CPEI,MCA etc.
110
147
*/
111
-
if (desc->status == IRQ_PER_CPU)
148
+
if (irqd_is_per_cpu(data))
112
149
continue;
113
150
114
-
if (cpumask_any_and(irq_desc[irq].affinity, cpu_online_mask)
151
+
if (cpumask_any_and(data->affinity, cpu_online_mask)
115
152
>= nr_cpu_ids) {
116
153
/*
117
154
* Save it for phase 2 processing
···
123
160
/*
124
161
* Al three are essential, currently WARN_ON.. maybe panic?
125
162
*/
126
-
if (desc->chip && desc->chip->disable &&
127
-
desc->chip->enable && desc->chip->set_affinity) {
128
-
desc->chip->disable(irq);
129
-
desc->chip->set_affinity(irq,
130
-
cpumask_of(new_cpu));
131
-
desc->chip->enable(irq);
163
+
if (chip && chip->irq_disable &&
164
+
chip->irq_enable && chip->irq_set_affinity) {
165
+
chip->irq_disable(data);
166
+
chip->irq_set_affinity(data,
167
+
cpumask_of(new_cpu), false);
168
+
chip->irq_enable(data);
132
169
} else {
133
-
WARN_ON((!(desc->chip) || !(desc->chip->disable) ||
134
-
!(desc->chip->enable) ||
135
-
!(desc->chip->set_affinity)));
170
+
WARN_ON((!chip || !chip->irq_disable ||
171
+
!chip->irq_enable ||
172
+
!chip->irq_set_affinity));
136
173
}
137
174
}
138
175
}
+4
-6
arch/ia64/kernel/irq_ia64.c
+4
-6
arch/ia64/kernel/irq_ia64.c
···
343
343
if (irq < 0)
344
344
continue;
345
345
346
-
desc = irq_desc + irq;
346
+
desc = irq_to_desc(irq);
347
347
cfg = irq_cfg + irq;
348
348
raw_spin_lock(&desc->lock);
349
349
if (!cfg->move_cleanup_count)
···
626
626
void
627
627
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
628
628
{
629
-
struct irq_desc *desc;
630
629
unsigned int irq;
631
630
632
631
irq = vec;
633
632
BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
634
-
desc = irq_desc + irq;
635
-
desc->status |= IRQ_PER_CPU;
636
-
set_irq_chip(irq, &irq_type_ia64_lsapic);
633
+
irq_set_status_flags(irq, IRQ_PER_CPU);
634
+
irq_set_chip(irq, &irq_type_ia64_lsapic);
637
635
if (action)
638
636
setup_irq(irq, action);
639
-
set_irq_handler(irq, handle_percpu_irq);
637
+
irq_set_handler(irq, handle_percpu_irq);
640
638
}
641
639
642
640
void __init
+11
-12
arch/ia64/kernel/irq_lsapic.c
+11
-12
arch/ia64/kernel/irq_lsapic.c
···
15
15
#include <linux/irq.h>
16
16
17
17
static unsigned int
18
-
lsapic_noop_startup (unsigned int irq)
18
+
lsapic_noop_startup (struct irq_data *data)
19
19
{
20
20
return 0;
21
21
}
22
22
23
23
static void
24
-
lsapic_noop (unsigned int irq)
24
+
lsapic_noop (struct irq_data *data)
25
25
{
26
26
/* nothing to do... */
27
27
}
28
28
29
-
static int lsapic_retrigger(unsigned int irq)
29
+
static int lsapic_retrigger(struct irq_data *data)
30
30
{
31
-
ia64_resend_irq(irq);
31
+
ia64_resend_irq(data->irq);
32
32
33
33
return 1;
34
34
}
35
35
36
36
struct irq_chip irq_type_ia64_lsapic = {
37
-
.name = "LSAPIC",
38
-
.startup = lsapic_noop_startup,
39
-
.shutdown = lsapic_noop,
40
-
.enable = lsapic_noop,
41
-
.disable = lsapic_noop,
42
-
.ack = lsapic_noop,
43
-
.end = lsapic_noop,
44
-
.retrigger = lsapic_retrigger,
37
+
.name = "LSAPIC",
38
+
.irq_startup = lsapic_noop_startup,
39
+
.irq_shutdown = lsapic_noop,
40
+
.irq_enable = lsapic_noop,
41
+
.irq_disable = lsapic_noop,
42
+
.irq_ack = lsapic_noop,
43
+
.irq_retrigger = lsapic_retrigger,
45
44
};
+1
-3
arch/ia64/kernel/mca.c
+1
-3
arch/ia64/kernel/mca.c
···
2125
2125
cpe_poll_timer.function = ia64_mca_cpe_poll;
2126
2126
2127
2127
{
2128
-
struct irq_desc *desc;
2129
2128
unsigned int irq;
2130
2129
2131
2130
if (cpe_vector >= 0) {
···
2132
2133
irq = local_vector_to_irq(cpe_vector);
2133
2134
if (irq > 0) {
2134
2135
cpe_poll_enabled = 0;
2135
-
desc = irq_desc + irq;
2136
-
desc->status |= IRQ_PER_CPU;
2136
+
irq_set_status_flags(irq, IRQ_PER_CPU);
2137
2137
setup_irq(irq, &mca_cpe_irqaction);
2138
2138
ia64_cpe_irq = irq;
2139
2139
ia64_mca_register_cpev(cpe_vector);
+26
-23
arch/ia64/kernel/msi_ia64.c
+26
-23
arch/ia64/kernel/msi_ia64.c
···
12
12
static struct irq_chip ia64_msi_chip;
13
13
14
14
#ifdef CONFIG_SMP
15
-
static int ia64_set_msi_irq_affinity(unsigned int irq,
16
-
const cpumask_t *cpu_mask)
15
+
static int ia64_set_msi_irq_affinity(struct irq_data *idata,
16
+
const cpumask_t *cpu_mask, bool force)
17
17
{
18
18
struct msi_msg msg;
19
19
u32 addr, data;
20
20
int cpu = first_cpu(*cpu_mask);
21
+
unsigned int irq = idata->irq;
21
22
22
23
if (!cpu_online(cpu))
23
24
return -1;
···
39
38
msg.data = data;
40
39
41
40
write_msi_msg(irq, &msg);
42
-
cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
41
+
cpumask_copy(idata->affinity, cpumask_of(cpu));
43
42
44
43
return 0;
45
44
}
···
56
55
if (irq < 0)
57
56
return irq;
58
57
59
-
set_irq_msi(irq, desc);
58
+
irq_set_msi_desc(irq, desc);
60
59
cpus_and(mask, irq_to_domain(irq), cpu_online_map);
61
60
dest_phys_id = cpu_physical_id(first_cpu(mask));
62
61
vector = irq_to_vector(irq);
···
75
74
MSI_DATA_VECTOR(vector);
76
75
77
76
write_msi_msg(irq, &msg);
78
-
set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
77
+
irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
79
78
80
79
return 0;
81
80
}
···
85
84
destroy_irq(irq);
86
85
}
87
86
88
-
static void ia64_ack_msi_irq(unsigned int irq)
87
+
static void ia64_ack_msi_irq(struct irq_data *data)
89
88
{
90
-
irq_complete_move(irq);
91
-
move_native_irq(irq);
89
+
irq_complete_move(data->irq);
90
+
irq_move_irq(data);
92
91
ia64_eoi();
93
92
}
94
93
95
-
static int ia64_msi_retrigger_irq(unsigned int irq)
94
+
static int ia64_msi_retrigger_irq(struct irq_data *data)
96
95
{
97
-
unsigned int vector = irq_to_vector(irq);
96
+
unsigned int vector = irq_to_vector(data->irq);
98
97
ia64_resend_irq(vector);
99
98
100
99
return 1;
···
104
103
* Generic ops used on most IA64 platforms.
105
104
*/
106
105
static struct irq_chip ia64_msi_chip = {
107
-
.name = "PCI-MSI",
108
-
.irq_mask = mask_msi_irq,
109
-
.irq_unmask = unmask_msi_irq,
110
-
.ack = ia64_ack_msi_irq,
106
+
.name = "PCI-MSI",
107
+
.irq_mask = mask_msi_irq,
108
+
.irq_unmask = unmask_msi_irq,
109
+
.irq_ack = ia64_ack_msi_irq,
111
110
#ifdef CONFIG_SMP
112
-
.set_affinity = ia64_set_msi_irq_affinity,
111
+
.irq_set_affinity = ia64_set_msi_irq_affinity,
113
112
#endif
114
-
.retrigger = ia64_msi_retrigger_irq,
113
+
.irq_retrigger = ia64_msi_retrigger_irq,
115
114
};
116
115
117
116
···
133
132
134
133
#ifdef CONFIG_DMAR
135
134
#ifdef CONFIG_SMP
136
-
static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
135
+
static int dmar_msi_set_affinity(struct irq_data *data,
136
+
const struct cpumask *mask, bool force)
137
137
{
138
+
unsigned int irq = data->irq;
138
139
struct irq_cfg *cfg = irq_cfg + irq;
139
140
struct msi_msg msg;
140
141
int cpu = cpumask_first(mask);
···
155
152
msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
156
153
157
154
dmar_msi_write(irq, &msg);
158
-
cpumask_copy(irq_desc[irq].affinity, mask);
155
+
cpumask_copy(data->affinity, mask);
159
156
160
157
return 0;
161
158
}
···
165
162
.name = "DMAR_MSI",
166
163
.irq_unmask = dmar_msi_unmask,
167
164
.irq_mask = dmar_msi_mask,
168
-
.ack = ia64_ack_msi_irq,
165
+
.irq_ack = ia64_ack_msi_irq,
169
166
#ifdef CONFIG_SMP
170
-
.set_affinity = dmar_msi_set_affinity,
167
+
.irq_set_affinity = dmar_msi_set_affinity,
171
168
#endif
172
-
.retrigger = ia64_msi_retrigger_irq,
169
+
.irq_retrigger = ia64_msi_retrigger_irq,
173
170
};
174
171
175
172
static int
···
206
203
if (ret < 0)
207
204
return ret;
208
205
dmar_msi_write(irq, &msg);
209
-
set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
210
-
"edge");
206
+
irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
207
+
"edge");
211
208
return 0;
212
209
}
213
210
#endif /* CONFIG_DMAR */
+7
-7
arch/ia64/kernel/smpboot.c
+7
-7
arch/ia64/kernel/smpboot.c
···
677
677
int migrate_platform_irqs(unsigned int cpu)
678
678
{
679
679
int new_cpei_cpu;
680
-
struct irq_desc *desc = NULL;
680
+
struct irq_data *data = NULL;
681
681
const struct cpumask *mask;
682
682
int retval = 0;
683
683
···
693
693
new_cpei_cpu = any_online_cpu(cpu_online_map);
694
694
mask = cpumask_of(new_cpei_cpu);
695
695
set_cpei_target_cpu(new_cpei_cpu);
696
-
desc = irq_desc + ia64_cpe_irq;
696
+
data = irq_get_irq_data(ia64_cpe_irq);
697
697
/*
698
698
* Switch for now, immediately, we need to do fake intr
699
699
* as other interrupts, but need to study CPEI behaviour with
700
700
* polling before making changes.
701
701
*/
702
-
if (desc) {
703
-
desc->chip->disable(ia64_cpe_irq);
704
-
desc->chip->set_affinity(ia64_cpe_irq, mask);
705
-
desc->chip->enable(ia64_cpe_irq);
702
+
if (data && data->chip) {
703
+
data->chip->irq_disable(data);
704
+
data->chip->irq_set_affinity(data, mask, false);
705
+
data->chip->irq_enable(data);
706
706
printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu);
707
707
}
708
708
}
709
-
if (!desc) {
709
+
if (!data) {
710
710
printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
711
711
retval = -EBUSY;
712
712
}
+28
-69
arch/ia64/sn/kernel/irq.c
+28
-69
arch/ia64/sn/kernel/irq.c
···
23
23
#include <asm/sn/sn_sal.h>
24
24
#include <asm/sn/sn_feature_sets.h>
25
25
26
-
static void force_interrupt(int irq);
27
26
static void register_intr_pda(struct sn_irq_info *sn_irq_info);
28
27
static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
29
28
30
-
int sn_force_interrupt_flag = 1;
31
29
extern int sn_ioif_inited;
32
30
struct list_head **sn_irq_lh;
33
31
static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
···
76
78
return ret_stuff.status;
77
79
}
78
80
79
-
static unsigned int sn_startup_irq(unsigned int irq)
81
+
static unsigned int sn_startup_irq(struct irq_data *data)
80
82
{
81
83
return 0;
82
84
}
83
85
84
-
static void sn_shutdown_irq(unsigned int irq)
86
+
static void sn_shutdown_irq(struct irq_data *data)
85
87
{
86
88
}
87
89
88
90
extern void ia64_mca_register_cpev(int);
89
91
90
-
static void sn_disable_irq(unsigned int irq)
92
+
static void sn_disable_irq(struct irq_data *data)
91
93
{
92
-
if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
94
+
if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
93
95
ia64_mca_register_cpev(0);
94
96
}
95
97
96
-
static void sn_enable_irq(unsigned int irq)
98
+
static void sn_enable_irq(struct irq_data *data)
97
99
{
98
-
if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
99
-
ia64_mca_register_cpev(irq);
100
+
if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
101
+
ia64_mca_register_cpev(data->irq);
100
102
}
101
103
102
-
static void sn_ack_irq(unsigned int irq)
104
+
static void sn_ack_irq(struct irq_data *data)
103
105
{
104
106
u64 event_occurred, mask;
107
+
unsigned int irq = data->irq & 0xff;
105
108
106
-
irq = irq & 0xff;
107
109
event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
108
110
mask = event_occurred & SH_ALL_INT_MASK;
109
111
HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
110
112
__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
111
113
112
-
move_native_irq(irq);
113
-
}
114
-
115
-
static void sn_end_irq(unsigned int irq)
116
-
{
117
-
int ivec;
118
-
u64 event_occurred;
119
-
120
-
ivec = irq & 0xff;
121
-
if (ivec == SGI_UART_VECTOR) {
122
-
event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
123
-
/* If the UART bit is set here, we may have received an
124
-
* interrupt from the UART that the driver missed. To
125
-
* make sure, we IPI ourselves to force us to look again.
126
-
*/
127
-
if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
128
-
platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
129
-
IA64_IPI_DM_INT, 0);
130
-
}
131
-
}
132
-
__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
133
-
if (sn_force_interrupt_flag)
134
-
force_interrupt(irq);
114
+
irq_move_irq(data);
135
115
}
136
116
137
117
static void sn_irq_info_free(struct rcu_head *head);
···
204
228
return new_irq_info;
205
229
}
206
230
207
-
static int sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask)
231
+
static int sn_set_affinity_irq(struct irq_data *data,
232
+
const struct cpumask *mask, bool force)
208
233
{
209
234
struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
235
+
unsigned int irq = data->irq;
210
236
nasid_t nasid;
211
237
int slice;
212
238
···
237
259
#endif
238
260
239
261
static void
240
-
sn_mask_irq(unsigned int irq)
262
+
sn_mask_irq(struct irq_data *data)
241
263
{
242
264
}
243
265
244
266
static void
245
-
sn_unmask_irq(unsigned int irq)
267
+
sn_unmask_irq(struct irq_data *data)
246
268
{
247
269
}
248
270
249
271
struct irq_chip irq_type_sn = {
250
-
.name = "SN hub",
251
-
.startup = sn_startup_irq,
252
-
.shutdown = sn_shutdown_irq,
253
-
.enable = sn_enable_irq,
254
-
.disable = sn_disable_irq,
255
-
.ack = sn_ack_irq,
256
-
.end = sn_end_irq,
257
-
.mask = sn_mask_irq,
258
-
.unmask = sn_unmask_irq,
259
-
.set_affinity = sn_set_affinity_irq
272
+
.name = "SN hub",
273
+
.irq_startup = sn_startup_irq,
274
+
.irq_shutdown = sn_shutdown_irq,
275
+
.irq_enable = sn_enable_irq,
276
+
.irq_disable = sn_disable_irq,
277
+
.irq_ack = sn_ack_irq,
278
+
.irq_mask = sn_mask_irq,
279
+
.irq_unmask = sn_unmask_irq,
280
+
.irq_set_affinity = sn_set_affinity_irq
260
281
};
261
282
262
283
ia64_vector sn_irq_to_vector(int irq)
···
273
296
void sn_irq_init(void)
274
297
{
275
298
int i;
276
-
struct irq_desc *base_desc = irq_desc;
277
299
278
300
ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
279
301
ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
280
302
281
303
for (i = 0; i < NR_IRQS; i++) {
282
-
if (base_desc[i].chip == &no_irq_chip) {
283
-
base_desc[i].chip = &irq_type_sn;
284
-
}
304
+
if (irq_get_chip(i) == &no_irq_chip)
305
+
irq_set_chip(i, &irq_type_sn);
285
306
}
286
307
}
287
308
···
353
378
int cpu = nasid_slice_to_cpuid(nasid, slice);
354
379
#ifdef CONFIG_SMP
355
380
int cpuphys;
356
-
struct irq_desc *desc;
357
381
#endif
358
382
359
383
pci_dev_get(pci_dev);
···
369
395
#ifdef CONFIG_SMP
370
396
cpuphys = cpu_physical_id(cpu);
371
397
set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
372
-
desc = irq_to_desc(sn_irq_info->irq_irq);
373
398
/*
374
399
* Affinity was set by the PROM, prevent it from
375
400
* being reset by the request_irq() path.
376
401
*/
377
-
desc->status |= IRQ_AFFINITY_SET;
402
+
irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq));
378
403
#endif
379
404
}
380
405
···
412
439
pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
413
440
414
441
/* Don't force an interrupt if the irq has been disabled */
415
-
if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) &&
442
+
if (!irqd_irq_disabled(sn_irq_info->irq_irq) &&
416
443
pci_provider && pci_provider->force_interrupt)
417
444
(*pci_provider->force_interrupt)(sn_irq_info);
418
-
}
419
-
420
-
static void force_interrupt(int irq)
421
-
{
422
-
struct sn_irq_info *sn_irq_info;
423
-
424
-
if (!sn_ioif_inited)
425
-
return;
426
-
427
-
rcu_read_lock();
428
-
list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
429
-
sn_call_force_intr_provider(sn_irq_info);
430
-
431
-
rcu_read_unlock();
432
445
}
433
446
434
447
/*
+16
-16
arch/ia64/sn/kernel/msi_sn.c
+16
-16
arch/ia64/sn/kernel/msi_sn.c
···
144
144
*/
145
145
msg.data = 0x100 + irq;
146
146
147
-
set_irq_msi(irq, entry);
147
+
irq_set_msi_desc(irq, entry);
148
148
write_msi_msg(irq, &msg);
149
-
set_irq_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
149
+
irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
150
150
151
151
return 0;
152
152
}
153
153
154
154
#ifdef CONFIG_SMP
155
-
static int sn_set_msi_irq_affinity(unsigned int irq,
156
-
const struct cpumask *cpu_mask)
155
+
static int sn_set_msi_irq_affinity(struct irq_data *data,
156
+
const struct cpumask *cpu_mask, bool force)
157
157
{
158
158
struct msi_msg msg;
159
159
int slice;
···
164
164
struct sn_irq_info *sn_irq_info;
165
165
struct sn_irq_info *new_irq_info;
166
166
struct sn_pcibus_provider *provider;
167
-
unsigned int cpu;
167
+
unsigned int cpu, irq = data->irq;
168
168
169
169
cpu = cpumask_first(cpu_mask);
170
170
sn_irq_info = sn_msi_info[irq].sn_irq_info;
···
206
206
msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
207
207
208
208
write_msi_msg(irq, &msg);
209
-
cpumask_copy(irq_desc[irq].affinity, cpu_mask);
209
+
cpumask_copy(data->affinity, cpu_mask);
210
210
211
211
return 0;
212
212
}
213
213
#endif /* CONFIG_SMP */
214
214
215
-
static void sn_ack_msi_irq(unsigned int irq)
215
+
static void sn_ack_msi_irq(struct irq_data *data)
216
216
{
217
-
move_native_irq(irq);
217
+
irq_move_irq(data);
218
218
ia64_eoi();
219
219
}
220
220
221
-
static int sn_msi_retrigger_irq(unsigned int irq)
221
+
static int sn_msi_retrigger_irq(struct irq_data *data)
222
222
{
223
-
unsigned int vector = irq;
223
+
unsigned int vector = data->irq;
224
224
ia64_resend_irq(vector);
225
225
226
226
return 1;
227
227
}
228
228
229
229
static struct irq_chip sn_msi_chip = {
230
-
.name = "PCI-MSI",
231
-
.irq_mask = mask_msi_irq,
232
-
.irq_unmask = unmask_msi_irq,
233
-
.ack = sn_ack_msi_irq,
230
+
.name = "PCI-MSI",
231
+
.irq_mask = mask_msi_irq,
232
+
.irq_unmask = unmask_msi_irq,
233
+
.irq_ack = sn_ack_msi_irq,
234
234
#ifdef CONFIG_SMP
235
-
.set_affinity = sn_set_msi_irq_affinity,
235
+
.irq_set_affinity = sn_set_msi_irq_affinity,
236
236
#endif
237
-
.retrigger = sn_msi_retrigger_irq,
237
+
.irq_retrigger = sn_msi_retrigger_irq,
238
238
};
+1
-3
arch/ia64/xen/irq_xen.c
+1
-3
arch/ia64/xen/irq_xen.c
···
138
138
__xen_register_percpu_irq(unsigned int cpu, unsigned int vec,
139
139
struct irqaction *action, int save)
140
140
{
141
-
struct irq_desc *desc;
142
141
int irq = 0;
143
142
144
143
if (xen_slab_ready) {
···
222
223
* mark the interrupt for migrations and trigger it
223
224
* on cpu hotplug.
224
225
*/
225
-
desc = irq_desc + irq;
226
-
desc->status |= IRQ_PER_CPU;
226
+
irq_set_status_flags(irq, IRQ_PER_CPU);
227
227
}
228
228
}
229
229
+1
-1
arch/m68k/kernel/irq.c
+1
-1
arch/m68k/kernel/irq.c
···
44
44
if (ap) {
45
45
seq_printf(p, "%3d: ", irq);
46
46
seq_printf(p, "%10u ", kstat_irqs(irq));
47
-
seq_printf(p, "%14s ", get_irq_desc_chip(desc)->name);
47
+
seq_printf(p, "%14s ", irq_desc_get_chip(desc)->name);
48
48
49
49
seq_printf(p, "%s", ap->name);
50
50
for (ap = ap->next; ap; ap = ap->next)
+2
-2
arch/m68k/platform/5249/intc2.c
+2
-2
arch/m68k/platform/5249/intc2.c
···
51
51
52
52
/* GPIO interrupt sources */
53
53
for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
54
-
set_irq_chip(irq, &intc2_irq_gpio_chip);
55
-
set_irq_handler(irq, handle_edge_irq);
54
+
irq_set_chip(irq, &intc2_irq_gpio_chip);
55
+
irq_set_handler(irq, handle_edge_irq);
56
56
}
57
57
58
58
return 0;
+6
-6
arch/m68k/platform/5272/intc.c
+6
-6
arch/m68k/platform/5272/intc.c
···
145
145
*/
146
146
static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
147
147
{
148
-
get_irq_desc_chip(desc)->irq_ack(&desc->irq_data);
148
+
irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
149
149
handle_simple_irq(irq, desc);
150
150
}
151
151
···
171
171
writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
172
172
173
173
for (irq = 0; (irq < NR_IRQS); irq++) {
174
-
set_irq_chip(irq, &intc_irq_chip);
174
+
irq_set_chip(irq, &intc_irq_chip);
175
175
edge = 0;
176
176
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
177
177
edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
178
178
if (edge) {
179
-
set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
180
-
set_irq_handler(irq, intc_external_irq);
179
+
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
180
+
irq_set_handler(irq, intc_external_irq);
181
181
} else {
182
-
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
183
-
set_irq_handler(irq, handle_level_irq);
182
+
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
183
+
irq_set_handler(irq, handle_level_irq);
184
184
}
185
185
}
186
186
}
+2
-2
arch/m68k/platform/68328/ints.c
+2
-2
arch/m68k/platform/68328/ints.c
+2
-2
arch/m68k/platform/68360/ints.c
+2
-2
arch/m68k/platform/68360/ints.c
+5
-5
arch/m68k/platform/coldfire/intc-2.c
+5
-5
arch/m68k/platform/coldfire/intc-2.c
···
164
164
}
165
165
166
166
if (tb)
167
-
set_irq_handler(irq, handle_edge_irq);
167
+
irq_set_handler(irq, handle_edge_irq);
168
168
169
169
irq -= EINT0;
170
170
pa = __raw_readw(MCFEPORT_EPPAR);
···
204
204
205
205
for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
206
206
if ((irq >= EINT1) && (irq <=EINT7))
207
-
set_irq_chip(irq, &intc_irq_chip_edge_port);
207
+
irq_set_chip(irq, &intc_irq_chip_edge_port);
208
208
else
209
-
set_irq_chip(irq, &intc_irq_chip);
210
-
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
211
-
set_irq_handler(irq, handle_level_irq);
209
+
irq_set_chip(irq, &intc_irq_chip);
210
+
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
211
+
irq_set_handler(irq, handle_level_irq);
212
212
}
213
213
}
214
214
+5
-5
arch/m68k/platform/coldfire/intc-simr.c
+5
-5
arch/m68k/platform/coldfire/intc-simr.c
···
141
141
}
142
142
143
143
if (tb)
144
-
set_irq_handler(irq, handle_edge_irq);
144
+
irq_set_handler(irq, handle_edge_irq);
145
145
146
146
ebit = irq2ebit(irq) * 2;
147
147
pa = __raw_readw(MCFEPORT_EPPAR);
···
181
181
eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
182
182
for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
183
183
if ((irq >= EINT1) && (irq <= EINT7))
184
-
set_irq_chip(irq, &intc_irq_chip_edge_port);
184
+
irq_set_chip(irq, &intc_irq_chip_edge_port);
185
185
else
186
-
set_irq_chip(irq, &intc_irq_chip);
187
-
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
188
-
set_irq_handler(irq, handle_level_irq);
186
+
irq_set_chip(irq, &intc_irq_chip);
187
+
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
188
+
irq_set_handler(irq, handle_level_irq);
189
189
}
190
190
}
191
191
+3
-3
arch/m68k/platform/coldfire/intc.c
+3
-3
arch/m68k/platform/coldfire/intc.c
···
143
143
mcf_maskimr(0xffffffff);
144
144
145
145
for (irq = 0; (irq < NR_IRQS); irq++) {
146
-
set_irq_chip(irq, &intc_irq_chip);
147
-
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
148
-
set_irq_handler(irq, handle_level_irq);
146
+
irq_set_chip(irq, &intc_irq_chip);
147
+
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
148
+
irq_set_handler(irq, handle_level_irq);
149
149
}
150
150
}
151
151
+1
arch/microblaze/Kconfig
+1
arch/microblaze/Kconfig
+3
-3
arch/microblaze/kernel/intc.c
+3
-3
arch/microblaze/kernel/intc.c
···
50
50
* ack function since the handle_level_irq function
51
51
* acks the irq before calling the interrupt handler
52
52
*/
53
-
if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
53
+
if (irqd_is_level_type(d))
54
54
out_be32(INTC_BASE + IAR, mask);
55
55
}
56
56
···
157
157
158
158
for (i = 0; i < nr_irq; ++i) {
159
159
if (intr_type & (0x00000001 << i)) {
160
-
set_irq_chip_and_handler_name(i, &intc_dev,
160
+
irq_set_chip_and_handler_name(i, &intc_dev,
161
161
handle_edge_irq, intc_dev.name);
162
162
irq_clear_status_flags(i, IRQ_LEVEL);
163
163
} else {
164
-
set_irq_chip_and_handler_name(i, &intc_dev,
164
+
irq_set_chip_and_handler_name(i, &intc_dev,
165
165
handle_level_irq, intc_dev.name);
166
166
irq_set_status_flags(i, IRQ_LEVEL);
167
167
}
-42
arch/microblaze/kernel/irq.c
-42
arch/microblaze/kernel/irq.c
···
47
47
trace_hardirqs_on();
48
48
}
49
49
50
-
int show_interrupts(struct seq_file *p, void *v)
51
-
{
52
-
int i = *(loff_t *) v, j;
53
-
struct irq_desc *desc;
54
-
struct irqaction *action;
55
-
unsigned long flags;
56
-
57
-
if (i == 0) {
58
-
seq_printf(p, " ");
59
-
for_each_online_cpu(j)
60
-
seq_printf(p, "CPU%-8d", j);
61
-
seq_putc(p, '\n');
62
-
}
63
-
64
-
if (i < nr_irq) {
65
-
desc = irq_to_desc(i);
66
-
raw_spin_lock_irqsave(&desc->lock, flags);
67
-
action = desc->action;
68
-
if (!action)
69
-
goto skip;
70
-
seq_printf(p, "%3d: ", i);
71
-
#ifndef CONFIG_SMP
72
-
seq_printf(p, "%10u ", kstat_irqs(i));
73
-
#else
74
-
for_each_online_cpu(j)
75
-
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
76
-
#endif
77
-
seq_printf(p, " %8s", desc->status &
78
-
IRQ_LEVEL ? "level" : "edge");
79
-
seq_printf(p, " %8s", desc->irq_data.chip->name);
80
-
seq_printf(p, " %s", action->name);
81
-
82
-
for (action = action->next; action; action = action->next)
83
-
seq_printf(p, ", %s", action->name);
84
-
85
-
seq_putc(p, '\n');
86
-
skip:
87
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
88
-
}
89
-
return 0;
90
-
}
91
-
92
50
/* MS: There is no any advance mapping mechanism. We are using simple 32bit
93
51
intc without any cascades or any connection that's why mapping is 1:1 */
94
52
unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq)
+1
-1
arch/microblaze/pci/pci-common.c
+1
-1
arch/microblaze/pci/pci-common.c
···
237
237
238
238
virq = irq_create_mapping(NULL, line);
239
239
if (virq != NO_IRQ)
240
-
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
240
+
irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
241
241
} else {
242
242
pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
243
243
oirq.size, oirq.specifier[0], oirq.specifier[1],
+3
-3
arch/mips/alchemy/devboards/bcsr.c
+3
-3
arch/mips/alchemy/devboards/bcsr.c
···
142
142
bcsr_csc_base = csc_start;
143
143
144
144
for (irq = csc_start; irq <= csc_end; irq++)
145
-
set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
146
-
handle_level_irq, "level");
145
+
irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
146
+
handle_level_irq, "level");
147
147
148
-
set_irq_chained_handler(hook_irq, bcsr_csc_handler);
148
+
irq_set_chained_handler(hook_irq, bcsr_csc_handler);
149
149
}
+7
-8
arch/mips/alchemy/devboards/db1200/setup.c
+7
-8
arch/mips/alchemy/devboards/db1200/setup.c
···
63
63
static int __init db1200_arch_init(void)
64
64
{
65
65
/* GPIO7 is low-level triggered CPLD cascade */
66
-
set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
66
+
irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
67
67
bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
68
68
69
69
/* insert/eject pairs: one of both is always screaming. To avoid
70
70
* issues they must not be automatically enabled when initially
71
71
* requested.
72
72
*/
73
-
irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
74
-
irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
75
-
irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN;
76
-
irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN;
77
-
irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN;
78
-
irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN;
79
-
73
+
irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
74
+
irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
75
+
irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
76
+
irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
77
+
irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
78
+
irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
80
79
return 0;
81
80
}
82
81
arch_initcall(db1200_arch_init);
+25
-25
arch/mips/alchemy/devboards/db1x00/board_setup.c
+25
-25
arch/mips/alchemy/devboards/db1x00/board_setup.c
···
215
215
static int __init db1x00_init_irq(void)
216
216
{
217
217
#if defined(CONFIG_MIPS_MIRAGE)
218
-
set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
218
+
irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
219
219
#elif defined(CONFIG_MIPS_DB1550)
220
-
set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
221
-
set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
222
-
set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
223
-
set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
224
-
set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
225
-
set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
220
+
irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
221
+
irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
222
+
irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
223
+
irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
224
+
irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
225
+
irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
226
226
#elif defined(CONFIG_MIPS_DB1500)
227
-
set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
228
-
set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
229
-
set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
230
-
set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
231
-
set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
232
-
set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
227
+
irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
228
+
irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
229
+
irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
230
+
irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
231
+
irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
232
+
irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
233
233
#elif defined(CONFIG_MIPS_DB1100)
234
-
set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
235
-
set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
236
-
set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
237
-
set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
238
-
set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
239
-
set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
234
+
irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
235
+
irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
236
+
irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
237
+
irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
238
+
irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
239
+
irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
240
240
#elif defined(CONFIG_MIPS_DB1000)
241
-
set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
242
-
set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
243
-
set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
244
-
set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
245
-
set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
246
-
set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
241
+
irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
242
+
irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
243
+
irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
244
+
irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
245
+
irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
246
+
irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
247
247
#endif
248
248
return 0;
249
249
}
+1
-1
arch/mips/alchemy/devboards/pb1000/board_setup.c
+1
-1
arch/mips/alchemy/devboards/pb1000/board_setup.c
+4
-4
arch/mips/alchemy/devboards/pb1100/board_setup.c
+4
-4
arch/mips/alchemy/devboards/pb1100/board_setup.c
···
117
117
118
118
static int __init pb1100_init_irq(void)
119
119
{
120
-
set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
121
-
set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
122
-
set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
123
-
set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
120
+
irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
121
+
irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
122
+
irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
123
+
irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
124
124
125
125
return 0;
126
126
}
+1
-1
arch/mips/alchemy/devboards/pb1200/board_setup.c
+1
-1
arch/mips/alchemy/devboards/pb1200/board_setup.c
+8
-8
arch/mips/alchemy/devboards/pb1500/board_setup.c
+8
-8
arch/mips/alchemy/devboards/pb1500/board_setup.c
···
134
134
135
135
static int __init pb1500_init_irq(void)
136
136
{
137
-
set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
138
-
set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
139
-
set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
140
-
set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
141
-
set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
142
-
set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
143
-
set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
144
-
set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
137
+
irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
138
+
irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
139
+
irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
140
+
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
141
+
irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
142
+
irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
143
+
irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
144
+
irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
145
145
146
146
return 0;
147
147
}
+3
-3
arch/mips/alchemy/devboards/pb1550/board_setup.c
+3
-3
arch/mips/alchemy/devboards/pb1550/board_setup.c
···
73
73
74
74
static int __init pb1550_init_irq(void)
75
75
{
76
-
set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
77
-
set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
78
-
set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
76
+
irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
77
+
irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
78
+
irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
79
79
80
80
/* enable both PCMCIA card irqs in the shared line */
81
81
alchemy_gpio2_enable_int(201);
+5
-5
arch/mips/alchemy/mtx-1/board_setup.c
+5
-5
arch/mips/alchemy/mtx-1/board_setup.c
···
123
123
124
124
static int __init mtx1_init_irq(void)
125
125
{
126
-
set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
127
-
set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
128
-
set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
129
-
set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
130
-
set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
126
+
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
127
+
irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
128
+
irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
129
+
irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
130
+
irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
131
131
132
132
return 0;
133
133
}
+12
-12
arch/mips/alchemy/xxs1500/board_setup.c
+12
-12
arch/mips/alchemy/xxs1500/board_setup.c
···
85
85
86
86
static int __init xxs1500_init_irq(void)
87
87
{
88
-
set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
89
-
set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
90
-
set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
91
-
set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
92
-
set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
93
-
set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
88
+
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
89
+
irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
90
+
irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
91
+
irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
92
+
irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
93
+
irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
94
94
95
-
set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
96
-
set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
97
-
set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
98
-
set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
99
-
set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
100
-
set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
95
+
irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
96
+
irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
97
+
irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
98
+
irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
99
+
irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
100
+
irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
101
101
102
102
return 0;
103
103
}
+2
-2
arch/mips/ar7/irq.c
+2
-2
arch/mips/ar7/irq.c
···
119
119
for (i = 0; i < 40; i++) {
120
120
writel(i, REG(CHNL_OFFSET(i)));
121
121
/* Primary IRQ's */
122
-
set_irq_chip_and_handler(base + i, &ar7_irq_type,
122
+
irq_set_chip_and_handler(base + i, &ar7_irq_type,
123
123
handle_level_irq);
124
124
/* Secondary IRQ's */
125
125
if (i < 32)
126
-
set_irq_chip_and_handler(base + i + 40,
126
+
irq_set_chip_and_handler(base + i + 40,
127
127
&ar7_sec_irq_type,
128
128
handle_level_irq);
129
129
}
+2
-2
arch/mips/ath79/irq.c
+2
-2
arch/mips/ath79/irq.c
···
124
124
125
125
for (i = ATH79_MISC_IRQ_BASE;
126
126
i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
127
-
set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
127
+
irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
128
128
handle_level_irq);
129
129
}
130
130
131
-
set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
131
+
irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
132
132
}
133
133
134
134
asmlinkage void plat_irq_dispatch(void)
+2
-2
arch/mips/bcm63xx/irq.c
+2
-2
arch/mips/bcm63xx/irq.c
···
230
230
231
231
mips_cpu_irq_init();
232
232
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
233
-
set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
233
+
irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
234
234
handle_level_irq);
235
235
236
236
for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
237
-
set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
237
+
irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
238
238
handle_edge_irq);
239
239
240
240
setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
+852
-681
arch/mips/cavium-octeon/octeon-irq.c
+852
-681
arch/mips/cavium-octeon/octeon-irq.c
···
3
3
* License. See the file "COPYING" in the main directory of this archive
4
4
* for more details.
5
5
*
6
-
* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
6
+
* Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks
7
7
*/
8
-
#include <linux/irq.h>
8
+
9
9
#include <linux/interrupt.h>
10
+
#include <linux/bitops.h>
11
+
#include <linux/percpu.h>
12
+
#include <linux/irq.h>
10
13
#include <linux/smp.h>
11
14
12
15
#include <asm/octeon/octeon.h>
13
16
14
17
static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
15
18
static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
19
+
20
+
static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
21
+
static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
22
+
23
+
static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
24
+
25
+
union octeon_ciu_chip_data {
26
+
void *p;
27
+
unsigned long l;
28
+
struct {
29
+
unsigned int line:6;
30
+
unsigned int bit:6;
31
+
} s;
32
+
};
33
+
34
+
struct octeon_core_chip_data {
35
+
struct mutex core_irq_mutex;
36
+
bool current_en;
37
+
bool desired_en;
38
+
u8 bit;
39
+
};
40
+
41
+
#define MIPS_CORE_IRQ_LINES 8
42
+
43
+
static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
44
+
45
+
static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit,
46
+
struct irq_chip *chip,
47
+
irq_flow_handler_t handler)
48
+
{
49
+
union octeon_ciu_chip_data cd;
50
+
51
+
irq_set_chip_and_handler(irq, chip, handler);
52
+
53
+
cd.l = 0;
54
+
cd.s.line = line;
55
+
cd.s.bit = bit;
56
+
57
+
irq_set_chip_data(irq, cd.p);
58
+
octeon_irq_ciu_to_irq[line][bit] = irq;
59
+
}
16
60
17
61
static int octeon_coreid_for_cpu(int cpu)
18
62
{
···
67
23
#endif
68
24
}
69
25
70
-
static void octeon_irq_core_ack(unsigned int irq)
26
+
static int octeon_cpu_for_coreid(int coreid)
71
27
{
72
-
unsigned int bit = irq - OCTEON_IRQ_SW0;
28
+
#ifdef CONFIG_SMP
29
+
return cpu_number_map(coreid);
30
+
#else
31
+
return smp_processor_id();
32
+
#endif
33
+
}
34
+
35
+
static void octeon_irq_core_ack(struct irq_data *data)
36
+
{
37
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
38
+
unsigned int bit = cd->bit;
39
+
73
40
/*
74
41
* We don't need to disable IRQs to make these atomic since
75
42
* they are already disabled earlier in the low level
···
92
37
clear_c0_cause(0x100 << bit);
93
38
}
94
39
95
-
static void octeon_irq_core_eoi(unsigned int irq)
40
+
static void octeon_irq_core_eoi(struct irq_data *data)
96
41
{
97
-
struct irq_desc *desc = irq_to_desc(irq);
98
-
unsigned int bit = irq - OCTEON_IRQ_SW0;
99
-
/*
100
-
* If an IRQ is being processed while we are disabling it the
101
-
* handler will attempt to unmask the interrupt after it has
102
-
* been disabled.
103
-
*/
104
-
if ((unlikely(desc->status & IRQ_DISABLED)))
105
-
return;
42
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
43
+
106
44
/*
107
45
* We don't need to disable IRQs to make these atomic since
108
46
* they are already disabled earlier in the low level
109
47
* interrupt code.
110
48
*/
111
-
set_c0_status(0x100 << bit);
49
+
set_c0_status(0x100 << cd->bit);
112
50
}
113
51
114
-
static void octeon_irq_core_enable(unsigned int irq)
52
+
static void octeon_irq_core_set_enable_local(void *arg)
115
53
{
116
-
unsigned long flags;
117
-
unsigned int bit = irq - OCTEON_IRQ_SW0;
54
+
struct irq_data *data = arg;
55
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
56
+
unsigned int mask = 0x100 << cd->bit;
118
57
119
58
/*
120
-
* We need to disable interrupts to make sure our updates are
121
-
* atomic.
59
+
* Interrupts are already disabled, so these are atomic.
122
60
*/
123
-
local_irq_save(flags);
124
-
set_c0_status(0x100 << bit);
125
-
local_irq_restore(flags);
61
+
if (cd->desired_en)
62
+
set_c0_status(mask);
63
+
else
64
+
clear_c0_status(mask);
65
+
126
66
}
127
67
128
-
static void octeon_irq_core_disable_local(unsigned int irq)
68
+
static void octeon_irq_core_disable(struct irq_data *data)
129
69
{
130
-
unsigned long flags;
131
-
unsigned int bit = irq - OCTEON_IRQ_SW0;
132
-
/*
133
-
* We need to disable interrupts to make sure our updates are
134
-
* atomic.
135
-
*/
136
-
local_irq_save(flags);
137
-
clear_c0_status(0x100 << bit);
138
-
local_irq_restore(flags);
70
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
71
+
cd->desired_en = false;
139
72
}
140
73
141
-
static void octeon_irq_core_disable(unsigned int irq)
74
+
static void octeon_irq_core_enable(struct irq_data *data)
142
75
{
143
-
#ifdef CONFIG_SMP
144
-
on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
145
-
(void *) (long) irq, 1);
146
-
#else
147
-
octeon_irq_core_disable_local(irq);
148
-
#endif
76
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
77
+
cd->desired_en = true;
78
+
}
79
+
80
+
static void octeon_irq_core_bus_lock(struct irq_data *data)
81
+
{
82
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
83
+
84
+
mutex_lock(&cd->core_irq_mutex);
85
+
}
86
+
87
+
static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
88
+
{
89
+
struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
90
+
91
+
if (cd->desired_en != cd->current_en) {
92
+
on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
93
+
94
+
cd->current_en = cd->desired_en;
95
+
}
96
+
97
+
mutex_unlock(&cd->core_irq_mutex);
149
98
}
150
99
151
100
static struct irq_chip octeon_irq_chip_core = {
152
101
.name = "Core",
153
-
.enable = octeon_irq_core_enable,
154
-
.disable = octeon_irq_core_disable,
155
-
.ack = octeon_irq_core_ack,
156
-
.eoi = octeon_irq_core_eoi,
102
+
.irq_enable = octeon_irq_core_enable,
103
+
.irq_disable = octeon_irq_core_disable,
104
+
.irq_ack = octeon_irq_core_ack,
105
+
.irq_eoi = octeon_irq_core_eoi,
106
+
.irq_bus_lock = octeon_irq_core_bus_lock,
107
+
.irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
108
+
109
+
.irq_cpu_online = octeon_irq_core_eoi,
110
+
.irq_cpu_offline = octeon_irq_core_ack,
111
+
.flags = IRQCHIP_ONOFFLINE_ENABLED,
157
112
};
158
113
159
-
160
-
static void octeon_irq_ciu0_ack(unsigned int irq)
114
+
static void __init octeon_irq_init_core(void)
161
115
{
162
-
switch (irq) {
163
-
case OCTEON_IRQ_GMX_DRP0:
164
-
case OCTEON_IRQ_GMX_DRP1:
165
-
case OCTEON_IRQ_IPD_DRP:
166
-
case OCTEON_IRQ_KEY_ZERO:
167
-
case OCTEON_IRQ_TIMER0:
168
-
case OCTEON_IRQ_TIMER1:
169
-
case OCTEON_IRQ_TIMER2:
170
-
case OCTEON_IRQ_TIMER3:
171
-
{
172
-
int index = cvmx_get_core_num() * 2;
173
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
174
-
/*
175
-
* CIU timer type interrupts must be acknoleged by
176
-
* writing a '1' bit to their sum0 bit.
177
-
*/
178
-
cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
179
-
break;
180
-
}
181
-
default:
182
-
break;
183
-
}
116
+
int i;
117
+
int irq;
118
+
struct octeon_core_chip_data *cd;
184
119
185
-
/*
186
-
* In order to avoid any locking accessing the CIU, we
187
-
* acknowledge CIU interrupts by disabling all of them. This
188
-
* way we can use a per core register and avoid any out of
189
-
* core locking requirements. This has the side affect that
190
-
* CIU interrupts can't be processed recursively.
191
-
*
192
-
* We don't need to disable IRQs to make these atomic since
193
-
* they are already disabled earlier in the low level
194
-
* interrupt code.
195
-
*/
196
-
clear_c0_status(0x100 << 2);
120
+
for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
121
+
cd = &octeon_irq_core_chip_data[i];
122
+
cd->current_en = false;
123
+
cd->desired_en = false;
124
+
cd->bit = i;
125
+
mutex_init(&cd->core_irq_mutex);
126
+
127
+
irq = OCTEON_IRQ_SW0 + i;
128
+
switch (irq) {
129
+
case OCTEON_IRQ_TIMER:
130
+
case OCTEON_IRQ_SW0:
131
+
case OCTEON_IRQ_SW1:
132
+
case OCTEON_IRQ_5:
133
+
case OCTEON_IRQ_PERF:
134
+
irq_set_chip_data(irq, cd);
135
+
irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
136
+
handle_percpu_irq);
137
+
break;
138
+
default:
139
+
break;
140
+
}
141
+
}
197
142
}
198
143
199
-
static void octeon_irq_ciu0_eoi(unsigned int irq)
200
-
{
201
-
/*
202
-
* Enable all CIU interrupts again. We don't need to disable
203
-
* IRQs to make these atomic since they are already disabled
204
-
* earlier in the low level interrupt code.
205
-
*/
206
-
set_c0_status(0x100 << 2);
207
-
}
208
-
209
-
static int next_coreid_for_irq(struct irq_desc *desc)
144
+
static int next_cpu_for_irq(struct irq_data *data)
210
145
{
211
146
212
147
#ifdef CONFIG_SMP
213
-
int coreid;
214
-
int weight = cpumask_weight(desc->affinity);
148
+
int cpu;
149
+
int weight = cpumask_weight(data->affinity);
215
150
216
151
if (weight > 1) {
217
-
int cpu = smp_processor_id();
152
+
cpu = smp_processor_id();
218
153
for (;;) {
219
-
cpu = cpumask_next(cpu, desc->affinity);
154
+
cpu = cpumask_next(cpu, data->affinity);
220
155
if (cpu >= nr_cpu_ids) {
221
156
cpu = -1;
222
157
continue;
···
214
169
break;
215
170
}
216
171
}
217
-
coreid = octeon_coreid_for_cpu(cpu);
218
172
} else if (weight == 1) {
219
-
coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
173
+
cpu = cpumask_first(data->affinity);
220
174
} else {
221
-
coreid = cvmx_get_core_num();
175
+
cpu = smp_processor_id();
222
176
}
223
-
return coreid;
177
+
return cpu;
224
178
#else
225
-
return cvmx_get_core_num();
179
+
return smp_processor_id();
226
180
#endif
227
181
}
228
182
229
-
static void octeon_irq_ciu0_enable(unsigned int irq)
183
+
static void octeon_irq_ciu_enable(struct irq_data *data)
230
184
{
231
-
struct irq_desc *desc = irq_to_desc(irq);
232
-
int coreid = next_coreid_for_irq(desc);
185
+
int cpu = next_cpu_for_irq(data);
186
+
int coreid = octeon_coreid_for_cpu(cpu);
187
+
unsigned long *pen;
233
188
unsigned long flags;
234
-
uint64_t en0;
235
-
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
189
+
union octeon_ciu_chip_data cd;
236
190
237
-
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
238
-
en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
239
-
en0 |= 1ull << bit;
240
-
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
241
-
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
242
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
243
-
}
191
+
cd.p = irq_data_get_irq_chip_data(data);
244
192
245
-
static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
246
-
{
247
-
int coreid = cvmx_get_core_num();
248
-
unsigned long flags;
249
-
uint64_t en0;
250
-
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
251
-
252
-
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
253
-
en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
254
-
en0 |= 1ull << bit;
255
-
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
256
-
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
257
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
258
-
}
259
-
260
-
static void octeon_irq_ciu0_disable(unsigned int irq)
261
-
{
262
-
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
263
-
unsigned long flags;
264
-
uint64_t en0;
265
-
int cpu;
266
-
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
267
-
for_each_online_cpu(cpu) {
268
-
int coreid = octeon_coreid_for_cpu(cpu);
269
-
en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
270
-
en0 &= ~(1ull << bit);
271
-
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
193
+
if (cd.s.line == 0) {
194
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
195
+
pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
196
+
set_bit(cd.s.bit, pen);
197
+
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
198
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
199
+
} else {
200
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
201
+
pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
202
+
set_bit(cd.s.bit, pen);
203
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
204
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
272
205
}
273
-
/*
274
-
* We need to do a read after the last update to make sure all
275
-
* of them are done.
276
-
*/
277
-
cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
278
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
206
+
}
207
+
208
+
static void octeon_irq_ciu_enable_local(struct irq_data *data)
209
+
{
210
+
unsigned long *pen;
211
+
unsigned long flags;
212
+
union octeon_ciu_chip_data cd;
213
+
214
+
cd.p = irq_data_get_irq_chip_data(data);
215
+
216
+
if (cd.s.line == 0) {
217
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
218
+
pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
219
+
set_bit(cd.s.bit, pen);
220
+
cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
221
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
222
+
} else {
223
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
224
+
pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
225
+
set_bit(cd.s.bit, pen);
226
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
227
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
228
+
}
229
+
}
230
+
231
+
static void octeon_irq_ciu_disable_local(struct irq_data *data)
232
+
{
233
+
unsigned long *pen;
234
+
unsigned long flags;
235
+
union octeon_ciu_chip_data cd;
236
+
237
+
cd.p = irq_data_get_irq_chip_data(data);
238
+
239
+
if (cd.s.line == 0) {
240
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
241
+
pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
242
+
clear_bit(cd.s.bit, pen);
243
+
cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
244
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
245
+
} else {
246
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
247
+
pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
248
+
clear_bit(cd.s.bit, pen);
249
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
250
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
251
+
}
252
+
}
253
+
254
+
static void octeon_irq_ciu_disable_all(struct irq_data *data)
255
+
{
256
+
unsigned long flags;
257
+
unsigned long *pen;
258
+
int cpu;
259
+
union octeon_ciu_chip_data cd;
260
+
261
+
wmb(); /* Make sure flag changes arrive before register updates. */
262
+
263
+
cd.p = irq_data_get_irq_chip_data(data);
264
+
265
+
if (cd.s.line == 0) {
266
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
267
+
for_each_online_cpu(cpu) {
268
+
int coreid = octeon_coreid_for_cpu(cpu);
269
+
pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
270
+
clear_bit(cd.s.bit, pen);
271
+
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
272
+
}
273
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
274
+
} else {
275
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
276
+
for_each_online_cpu(cpu) {
277
+
int coreid = octeon_coreid_for_cpu(cpu);
278
+
pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
279
+
clear_bit(cd.s.bit, pen);
280
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
281
+
}
282
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
283
+
}
284
+
}
285
+
286
+
static void octeon_irq_ciu_enable_all(struct irq_data *data)
287
+
{
288
+
unsigned long flags;
289
+
unsigned long *pen;
290
+
int cpu;
291
+
union octeon_ciu_chip_data cd;
292
+
293
+
cd.p = irq_data_get_irq_chip_data(data);
294
+
295
+
if (cd.s.line == 0) {
296
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
297
+
for_each_online_cpu(cpu) {
298
+
int coreid = octeon_coreid_for_cpu(cpu);
299
+
pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
300
+
set_bit(cd.s.bit, pen);
301
+
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
302
+
}
303
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
304
+
} else {
305
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
306
+
for_each_online_cpu(cpu) {
307
+
int coreid = octeon_coreid_for_cpu(cpu);
308
+
pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
309
+
set_bit(cd.s.bit, pen);
310
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
311
+
}
312
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
313
+
}
279
314
}
280
315
281
316
/*
282
317
* Enable the irq on the next core in the affinity set for chips that
283
318
* have the EN*_W1{S,C} registers.
284
319
*/
285
-
static void octeon_irq_ciu0_enable_v2(unsigned int irq)
320
+
static void octeon_irq_ciu_enable_v2(struct irq_data *data)
286
321
{
287
-
int index;
288
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
289
-
struct irq_desc *desc = irq_to_desc(irq);
322
+
u64 mask;
323
+
int cpu = next_cpu_for_irq(data);
324
+
union octeon_ciu_chip_data cd;
290
325
291
-
if ((desc->status & IRQ_DISABLED) == 0) {
292
-
index = next_coreid_for_irq(desc) * 2;
326
+
cd.p = irq_data_get_irq_chip_data(data);
327
+
mask = 1ull << (cd.s.bit);
328
+
329
+
/*
330
+
* Called under the desc lock, so these should never get out
331
+
* of sync.
332
+
*/
333
+
if (cd.s.line == 0) {
334
+
int index = octeon_coreid_for_cpu(cpu) * 2;
335
+
set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
293
336
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
337
+
} else {
338
+
int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
339
+
set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
340
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
294
341
}
295
342
}
296
343
···
390
253
* Enable the irq on the current CPU for chips that
391
254
* have the EN*_W1{S,C} registers.
392
255
*/
393
-
static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
256
+
static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
394
257
{
395
-
int index;
396
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
258
+
u64 mask;
259
+
union octeon_ciu_chip_data cd;
397
260
398
-
index = cvmx_get_core_num() * 2;
399
-
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
400
-
}
261
+
cd.p = irq_data_get_irq_chip_data(data);
262
+
mask = 1ull << (cd.s.bit);
401
263
402
-
/*
403
-
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
404
-
* registers.
405
-
*/
406
-
static void octeon_irq_ciu0_ack_v2(unsigned int irq)
407
-
{
408
-
int index = cvmx_get_core_num() * 2;
409
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
410
-
411
-
switch (irq) {
412
-
case OCTEON_IRQ_GMX_DRP0:
413
-
case OCTEON_IRQ_GMX_DRP1:
414
-
case OCTEON_IRQ_IPD_DRP:
415
-
case OCTEON_IRQ_KEY_ZERO:
416
-
case OCTEON_IRQ_TIMER0:
417
-
case OCTEON_IRQ_TIMER1:
418
-
case OCTEON_IRQ_TIMER2:
419
-
case OCTEON_IRQ_TIMER3:
420
-
/*
421
-
* CIU timer type interrupts must be acknoleged by
422
-
* writing a '1' bit to their sum0 bit.
423
-
*/
424
-
cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
425
-
break;
426
-
default:
427
-
break;
428
-
}
429
-
430
-
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
431
-
}
432
-
433
-
/*
434
-
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
435
-
* registers.
436
-
*/
437
-
static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
438
-
{
439
-
struct irq_desc *desc = irq_to_desc(irq);
440
-
int index = cvmx_get_core_num() * 2;
441
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
442
-
443
-
if (likely((desc->status & IRQ_DISABLED) == 0))
264
+
if (cd.s.line == 0) {
265
+
int index = cvmx_get_core_num() * 2;
266
+
set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror));
444
267
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
268
+
} else {
269
+
int index = cvmx_get_core_num() * 2 + 1;
270
+
set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror));
271
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
272
+
}
445
273
}
446
274
447
-
/*
448
-
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
449
-
* registers.
450
-
*/
451
-
static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
275
+
static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
452
276
{
453
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
454
-
int index;
455
-
int cpu;
456
-
for_each_online_cpu(cpu) {
457
-
index = octeon_coreid_for_cpu(cpu) * 2;
277
+
u64 mask;
278
+
union octeon_ciu_chip_data cd;
279
+
280
+
cd.p = irq_data_get_irq_chip_data(data);
281
+
mask = 1ull << (cd.s.bit);
282
+
283
+
if (cd.s.line == 0) {
284
+
int index = cvmx_get_core_num() * 2;
285
+
clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror));
458
286
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
459
-
}
460
-
}
461
-
462
-
#ifdef CONFIG_SMP
463
-
static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
464
-
{
465
-
int cpu;
466
-
struct irq_desc *desc = irq_to_desc(irq);
467
-
int enable_one = (desc->status & IRQ_DISABLED) == 0;
468
-
unsigned long flags;
469
-
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
470
-
471
-
/*
472
-
* For non-v2 CIU, we will allow only single CPU affinity.
473
-
* This removes the need to do locking in the .ack/.eoi
474
-
* functions.
475
-
*/
476
-
if (cpumask_weight(dest) != 1)
477
-
return -EINVAL;
478
-
479
-
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
480
-
for_each_online_cpu(cpu) {
481
-
int coreid = octeon_coreid_for_cpu(cpu);
482
-
uint64_t en0 =
483
-
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
484
-
if (cpumask_test_cpu(cpu, dest) && enable_one) {
485
-
enable_one = 0;
486
-
en0 |= 1ull << bit;
487
-
} else {
488
-
en0 &= ~(1ull << bit);
489
-
}
490
-
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
491
-
}
492
-
/*
493
-
* We need to do a read after the last update to make sure all
494
-
* of them are done.
495
-
*/
496
-
cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
497
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
498
-
499
-
return 0;
500
-
}
501
-
502
-
/*
503
-
* Set affinity for the irq for chips that have the EN*_W1{S,C}
504
-
* registers.
505
-
*/
506
-
static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
507
-
const struct cpumask *dest)
508
-
{
509
-
int cpu;
510
-
int index;
511
-
struct irq_desc *desc = irq_to_desc(irq);
512
-
int enable_one = (desc->status & IRQ_DISABLED) == 0;
513
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
514
-
515
-
for_each_online_cpu(cpu) {
516
-
index = octeon_coreid_for_cpu(cpu) * 2;
517
-
if (cpumask_test_cpu(cpu, dest) && enable_one) {
518
-
enable_one = 0;
519
-
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
520
-
} else {
521
-
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
522
-
}
523
-
}
524
-
return 0;
525
-
}
526
-
#endif
527
-
528
-
/*
529
-
* Newer octeon chips have support for lockless CIU operation.
530
-
*/
531
-
static struct irq_chip octeon_irq_chip_ciu0_v2 = {
532
-
.name = "CIU0",
533
-
.enable = octeon_irq_ciu0_enable_v2,
534
-
.disable = octeon_irq_ciu0_disable_all_v2,
535
-
.eoi = octeon_irq_ciu0_enable_v2,
536
-
#ifdef CONFIG_SMP
537
-
.set_affinity = octeon_irq_ciu0_set_affinity_v2,
538
-
#endif
539
-
};
540
-
541
-
static struct irq_chip octeon_irq_chip_ciu0 = {
542
-
.name = "CIU0",
543
-
.enable = octeon_irq_ciu0_enable,
544
-
.disable = octeon_irq_ciu0_disable,
545
-
.eoi = octeon_irq_ciu0_eoi,
546
-
#ifdef CONFIG_SMP
547
-
.set_affinity = octeon_irq_ciu0_set_affinity,
548
-
#endif
549
-
};
550
-
551
-
/* The mbox versions don't do any affinity or round-robin. */
552
-
static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
553
-
.name = "CIU0-M",
554
-
.enable = octeon_irq_ciu0_enable_mbox_v2,
555
-
.disable = octeon_irq_ciu0_disable,
556
-
.eoi = octeon_irq_ciu0_eoi_mbox_v2,
557
-
};
558
-
559
-
static struct irq_chip octeon_irq_chip_ciu0_mbox = {
560
-
.name = "CIU0-M",
561
-
.enable = octeon_irq_ciu0_enable_mbox,
562
-
.disable = octeon_irq_ciu0_disable,
563
-
.eoi = octeon_irq_ciu0_eoi,
564
-
};
565
-
566
-
static void octeon_irq_ciu1_ack(unsigned int irq)
567
-
{
568
-
/*
569
-
* In order to avoid any locking accessing the CIU, we
570
-
* acknowledge CIU interrupts by disabling all of them. This
571
-
* way we can use a per core register and avoid any out of
572
-
* core locking requirements. This has the side affect that
573
-
* CIU interrupts can't be processed recursively. We don't
574
-
* need to disable IRQs to make these atomic since they are
575
-
* already disabled earlier in the low level interrupt code.
576
-
*/
577
-
clear_c0_status(0x100 << 3);
578
-
}
579
-
580
-
static void octeon_irq_ciu1_eoi(unsigned int irq)
581
-
{
582
-
/*
583
-
* Enable all CIU interrupts again. We don't need to disable
584
-
* IRQs to make these atomic since they are already disabled
585
-
* earlier in the low level interrupt code.
586
-
*/
587
-
set_c0_status(0x100 << 3);
588
-
}
589
-
590
-
static void octeon_irq_ciu1_enable(unsigned int irq)
591
-
{
592
-
struct irq_desc *desc = irq_to_desc(irq);
593
-
int coreid = next_coreid_for_irq(desc);
594
-
unsigned long flags;
595
-
uint64_t en1;
596
-
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
597
-
598
-
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
599
-
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
600
-
en1 |= 1ull << bit;
601
-
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
602
-
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
603
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
604
-
}
605
-
606
-
/*
607
-
* Watchdog interrupts are special. They are associated with a single
608
-
* core, so we hardwire the affinity to that core.
609
-
*/
610
-
static void octeon_irq_ciu1_wd_enable(unsigned int irq)
611
-
{
612
-
unsigned long flags;
613
-
uint64_t en1;
614
-
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
615
-
int coreid = bit;
616
-
617
-
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
618
-
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
619
-
en1 |= 1ull << bit;
620
-
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
621
-
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
622
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
623
-
}
624
-
625
-
static void octeon_irq_ciu1_disable(unsigned int irq)
626
-
{
627
-
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
628
-
unsigned long flags;
629
-
uint64_t en1;
630
-
int cpu;
631
-
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
632
-
for_each_online_cpu(cpu) {
633
-
int coreid = octeon_coreid_for_cpu(cpu);
634
-
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
635
-
en1 &= ~(1ull << bit);
636
-
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
637
-
}
638
-
/*
639
-
* We need to do a read after the last update to make sure all
640
-
* of them are done.
641
-
*/
642
-
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
643
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
644
-
}
645
-
646
-
/*
647
-
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
648
-
* registers.
649
-
*/
650
-
static void octeon_irq_ciu1_enable_v2(unsigned int irq)
651
-
{
652
-
int index;
653
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
654
-
struct irq_desc *desc = irq_to_desc(irq);
655
-
656
-
if ((desc->status & IRQ_DISABLED) == 0) {
657
-
index = next_coreid_for_irq(desc) * 2 + 1;
658
-
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
659
-
}
660
-
}
661
-
662
-
/*
663
-
* Watchdog interrupts are special. They are associated with a single
664
-
* core, so we hardwire the affinity to that core.
665
-
*/
666
-
static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
667
-
{
668
-
int index;
669
-
int coreid = irq - OCTEON_IRQ_WDOG0;
670
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
671
-
struct irq_desc *desc = irq_to_desc(irq);
672
-
673
-
if ((desc->status & IRQ_DISABLED) == 0) {
674
-
index = coreid * 2 + 1;
675
-
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
676
-
}
677
-
}
678
-
679
-
/*
680
-
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
681
-
* registers.
682
-
*/
683
-
static void octeon_irq_ciu1_ack_v2(unsigned int irq)
684
-
{
685
-
int index = cvmx_get_core_num() * 2 + 1;
686
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
687
-
688
-
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
689
-
}
690
-
691
-
/*
692
-
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
693
-
* registers.
694
-
*/
695
-
static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
696
-
{
697
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
698
-
int index;
699
-
int cpu;
700
-
for_each_online_cpu(cpu) {
701
-
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
287
+
} else {
288
+
int index = cvmx_get_core_num() * 2 + 1;
289
+
clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror));
702
290
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
703
291
}
704
292
}
705
293
706
-
#ifdef CONFIG_SMP
707
-
static int octeon_irq_ciu1_set_affinity(unsigned int irq,
708
-
const struct cpumask *dest)
294
+
/*
295
+
* Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
296
+
*/
297
+
static void octeon_irq_ciu_ack(struct irq_data *data)
298
+
{
299
+
u64 mask;
300
+
union octeon_ciu_chip_data cd;
301
+
302
+
cd.p = data->chip_data;
303
+
mask = 1ull << (cd.s.bit);
304
+
305
+
if (cd.s.line == 0) {
306
+
int index = cvmx_get_core_num() * 2;
307
+
cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
308
+
} else {
309
+
cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
310
+
}
311
+
}
312
+
313
+
/*
314
+
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
315
+
* registers.
316
+
*/
317
+
static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
709
318
{
710
319
int cpu;
711
-
struct irq_desc *desc = irq_to_desc(irq);
712
-
int enable_one = (desc->status & IRQ_DISABLED) == 0;
320
+
u64 mask;
321
+
union octeon_ciu_chip_data cd;
322
+
323
+
wmb(); /* Make sure flag changes arrive before register updates. */
324
+
325
+
cd.p = data->chip_data;
326
+
mask = 1ull << (cd.s.bit);
327
+
328
+
if (cd.s.line == 0) {
329
+
for_each_online_cpu(cpu) {
330
+
int index = octeon_coreid_for_cpu(cpu) * 2;
331
+
clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
332
+
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
333
+
}
334
+
} else {
335
+
for_each_online_cpu(cpu) {
336
+
int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
337
+
clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
338
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
339
+
}
340
+
}
341
+
}
342
+
343
+
/*
344
+
* Enable the irq on the all cores for chips that have the EN*_W1{S,C}
345
+
* registers.
346
+
*/
347
+
static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
348
+
{
349
+
int cpu;
350
+
u64 mask;
351
+
union octeon_ciu_chip_data cd;
352
+
353
+
cd.p = data->chip_data;
354
+
mask = 1ull << (cd.s.bit);
355
+
356
+
if (cd.s.line == 0) {
357
+
for_each_online_cpu(cpu) {
358
+
int index = octeon_coreid_for_cpu(cpu) * 2;
359
+
set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
360
+
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
361
+
}
362
+
} else {
363
+
for_each_online_cpu(cpu) {
364
+
int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
365
+
set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
366
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
367
+
}
368
+
}
369
+
}
370
+
371
+
#ifdef CONFIG_SMP
372
+
373
+
static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
374
+
{
375
+
int cpu = smp_processor_id();
376
+
cpumask_t new_affinity;
377
+
378
+
if (!cpumask_test_cpu(cpu, data->affinity))
379
+
return;
380
+
381
+
if (cpumask_weight(data->affinity) > 1) {
382
+
/*
383
+
* It has multi CPU affinity, just remove this CPU
384
+
* from the affinity set.
385
+
*/
386
+
cpumask_copy(&new_affinity, data->affinity);
387
+
cpumask_clear_cpu(cpu, &new_affinity);
388
+
} else {
389
+
/* Otherwise, put it on lowest numbered online CPU. */
390
+
cpumask_clear(&new_affinity);
391
+
cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
392
+
}
393
+
__irq_set_affinity_locked(data, &new_affinity);
394
+
}
395
+
396
+
static int octeon_irq_ciu_set_affinity(struct irq_data *data,
397
+
const struct cpumask *dest, bool force)
398
+
{
399
+
int cpu;
400
+
bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
713
401
unsigned long flags;
714
-
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
402
+
union octeon_ciu_chip_data cd;
403
+
404
+
cd.p = data->chip_data;
715
405
716
406
/*
717
407
* For non-v2 CIU, we will allow only single CPU affinity.
···
548
584
if (cpumask_weight(dest) != 1)
549
585
return -EINVAL;
550
586
551
-
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
552
-
for_each_online_cpu(cpu) {
553
-
int coreid = octeon_coreid_for_cpu(cpu);
554
-
uint64_t en1 =
555
-
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
556
-
if (cpumask_test_cpu(cpu, dest) && enable_one) {
557
-
enable_one = 0;
558
-
en1 |= 1ull << bit;
559
-
} else {
560
-
en1 &= ~(1ull << bit);
561
-
}
562
-
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
563
-
}
564
-
/*
565
-
* We need to do a read after the last update to make sure all
566
-
* of them are done.
567
-
*/
568
-
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
569
-
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
587
+
if (!enable_one)
588
+
return 0;
570
589
590
+
if (cd.s.line == 0) {
591
+
raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
592
+
for_each_online_cpu(cpu) {
593
+
int coreid = octeon_coreid_for_cpu(cpu);
594
+
unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
595
+
596
+
if (cpumask_test_cpu(cpu, dest) && enable_one) {
597
+
enable_one = false;
598
+
set_bit(cd.s.bit, pen);
599
+
} else {
600
+
clear_bit(cd.s.bit, pen);
601
+
}
602
+
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
603
+
}
604
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
605
+
} else {
606
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
607
+
for_each_online_cpu(cpu) {
608
+
int coreid = octeon_coreid_for_cpu(cpu);
609
+
unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
610
+
611
+
if (cpumask_test_cpu(cpu, dest) && enable_one) {
612
+
enable_one = false;
613
+
set_bit(cd.s.bit, pen);
614
+
} else {
615
+
clear_bit(cd.s.bit, pen);
616
+
}
617
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
618
+
}
619
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
620
+
}
571
621
return 0;
572
622
}
573
623
···
589
611
* Set affinity for the irq for chips that have the EN*_W1{S,C}
590
612
* registers.
591
613
*/
592
-
static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
593
-
const struct cpumask *dest)
614
+
static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
615
+
const struct cpumask *dest,
616
+
bool force)
594
617
{
595
618
int cpu;
596
-
int index;
597
-
struct irq_desc *desc = irq_to_desc(irq);
598
-
int enable_one = (desc->status & IRQ_DISABLED) == 0;
599
-
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
600
-
for_each_online_cpu(cpu) {
601
-
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
602
-
if (cpumask_test_cpu(cpu, dest) && enable_one) {
603
-
enable_one = 0;
604
-
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
605
-
} else {
606
-
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
619
+
bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
620
+
u64 mask;
621
+
union octeon_ciu_chip_data cd;
622
+
623
+
if (!enable_one)
624
+
return 0;
625
+
626
+
cd.p = data->chip_data;
627
+
mask = 1ull << cd.s.bit;
628
+
629
+
if (cd.s.line == 0) {
630
+
for_each_online_cpu(cpu) {
631
+
unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
632
+
int index = octeon_coreid_for_cpu(cpu) * 2;
633
+
if (cpumask_test_cpu(cpu, dest) && enable_one) {
634
+
enable_one = false;
635
+
set_bit(cd.s.bit, pen);
636
+
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
637
+
} else {
638
+
clear_bit(cd.s.bit, pen);
639
+
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
640
+
}
641
+
}
642
+
} else {
643
+
for_each_online_cpu(cpu) {
644
+
unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
645
+
int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
646
+
if (cpumask_test_cpu(cpu, dest) && enable_one) {
647
+
enable_one = false;
648
+
set_bit(cd.s.bit, pen);
649
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
650
+
} else {
651
+
clear_bit(cd.s.bit, pen);
652
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
653
+
}
607
654
}
608
655
}
609
656
return 0;
···
636
633
#endif
637
634
638
635
/*
636
+
* The v1 CIU code already masks things, so supply a dummy version to
637
+
* the core chip code.
638
+
*/
639
+
static void octeon_irq_dummy_mask(struct irq_data *data)
640
+
{
641
+
}
642
+
643
+
/*
639
644
* Newer octeon chips have support for lockless CIU operation.
640
645
*/
641
-
static struct irq_chip octeon_irq_chip_ciu1_v2 = {
642
-
.name = "CIU1",
643
-
.enable = octeon_irq_ciu1_enable_v2,
644
-
.disable = octeon_irq_ciu1_disable_all_v2,
645
-
.eoi = octeon_irq_ciu1_enable_v2,
646
+
static struct irq_chip octeon_irq_chip_ciu_v2 = {
647
+
.name = "CIU",
648
+
.irq_enable = octeon_irq_ciu_enable_v2,
649
+
.irq_disable = octeon_irq_ciu_disable_all_v2,
650
+
.irq_mask = octeon_irq_ciu_disable_local_v2,
651
+
.irq_unmask = octeon_irq_ciu_enable_v2,
646
652
#ifdef CONFIG_SMP
647
-
.set_affinity = octeon_irq_ciu1_set_affinity_v2,
653
+
.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
654
+
.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
648
655
#endif
649
656
};
650
657
651
-
static struct irq_chip octeon_irq_chip_ciu1 = {
652
-
.name = "CIU1",
653
-
.enable = octeon_irq_ciu1_enable,
654
-
.disable = octeon_irq_ciu1_disable,
655
-
.eoi = octeon_irq_ciu1_eoi,
658
+
static struct irq_chip octeon_irq_chip_ciu_edge_v2 = {
659
+
.name = "CIU-E",
660
+
.irq_enable = octeon_irq_ciu_enable_v2,
661
+
.irq_disable = octeon_irq_ciu_disable_all_v2,
662
+
.irq_ack = octeon_irq_ciu_ack,
663
+
.irq_mask = octeon_irq_ciu_disable_local_v2,
664
+
.irq_unmask = octeon_irq_ciu_enable_v2,
656
665
#ifdef CONFIG_SMP
657
-
.set_affinity = octeon_irq_ciu1_set_affinity,
666
+
.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
667
+
.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
658
668
#endif
659
669
};
660
670
661
-
static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
662
-
.name = "CIU1-W",
663
-
.enable = octeon_irq_ciu1_wd_enable_v2,
664
-
.disable = octeon_irq_ciu1_disable_all_v2,
665
-
.eoi = octeon_irq_ciu1_wd_enable_v2,
671
+
static struct irq_chip octeon_irq_chip_ciu = {
672
+
.name = "CIU",
673
+
.irq_enable = octeon_irq_ciu_enable,
674
+
.irq_disable = octeon_irq_ciu_disable_all,
675
+
.irq_mask = octeon_irq_dummy_mask,
676
+
#ifdef CONFIG_SMP
677
+
.irq_set_affinity = octeon_irq_ciu_set_affinity,
678
+
.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
679
+
#endif
666
680
};
667
681
668
-
static struct irq_chip octeon_irq_chip_ciu1_wd = {
669
-
.name = "CIU1-W",
670
-
.enable = octeon_irq_ciu1_wd_enable,
671
-
.disable = octeon_irq_ciu1_disable,
672
-
.eoi = octeon_irq_ciu1_eoi,
682
+
static struct irq_chip octeon_irq_chip_ciu_edge = {
683
+
.name = "CIU-E",
684
+
.irq_enable = octeon_irq_ciu_enable,
685
+
.irq_disable = octeon_irq_ciu_disable_all,
686
+
.irq_mask = octeon_irq_dummy_mask,
687
+
.irq_ack = octeon_irq_ciu_ack,
688
+
#ifdef CONFIG_SMP
689
+
.irq_set_affinity = octeon_irq_ciu_set_affinity,
690
+
.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
691
+
#endif
673
692
};
674
693
675
-
static void (*octeon_ciu0_ack)(unsigned int);
676
-
static void (*octeon_ciu1_ack)(unsigned int);
694
+
/* The mbox versions don't do any affinity or round-robin. */
695
+
static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
696
+
.name = "CIU-M",
697
+
.irq_enable = octeon_irq_ciu_enable_all_v2,
698
+
.irq_disable = octeon_irq_ciu_disable_all_v2,
699
+
.irq_ack = octeon_irq_ciu_disable_local_v2,
700
+
.irq_eoi = octeon_irq_ciu_enable_local_v2,
701
+
702
+
.irq_cpu_online = octeon_irq_ciu_enable_local_v2,
703
+
.irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
704
+
.flags = IRQCHIP_ONOFFLINE_ENABLED,
705
+
};
706
+
707
+
static struct irq_chip octeon_irq_chip_ciu_mbox = {
708
+
.name = "CIU-M",
709
+
.irq_enable = octeon_irq_ciu_enable_all,
710
+
.irq_disable = octeon_irq_ciu_disable_all,
711
+
712
+
.irq_cpu_online = octeon_irq_ciu_enable_local,
713
+
.irq_cpu_offline = octeon_irq_ciu_disable_local,
714
+
.flags = IRQCHIP_ONOFFLINE_ENABLED,
715
+
};
716
+
717
+
/*
718
+
* Watchdog interrupts are special. They are associated with a single
719
+
* core, so we hardwire the affinity to that core.
720
+
*/
721
+
static void octeon_irq_ciu_wd_enable(struct irq_data *data)
722
+
{
723
+
unsigned long flags;
724
+
unsigned long *pen;
725
+
int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
726
+
int cpu = octeon_cpu_for_coreid(coreid);
727
+
728
+
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
729
+
pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
730
+
set_bit(coreid, pen);
731
+
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
732
+
raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
733
+
}
734
+
735
+
/*
736
+
* Watchdog interrupts are special. They are associated with a single
737
+
* core, so we hardwire the affinity to that core.
738
+
*/
739
+
static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
740
+
{
741
+
int coreid = data->irq - OCTEON_IRQ_WDOG0;
742
+
int cpu = octeon_cpu_for_coreid(coreid);
743
+
744
+
set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
745
+
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
746
+
}
747
+
748
+
749
+
static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
750
+
.name = "CIU-W",
751
+
.irq_enable = octeon_irq_ciu1_wd_enable_v2,
752
+
.irq_disable = octeon_irq_ciu_disable_all_v2,
753
+
.irq_mask = octeon_irq_ciu_disable_local_v2,
754
+
.irq_unmask = octeon_irq_ciu_enable_local_v2,
755
+
};
756
+
757
+
static struct irq_chip octeon_irq_chip_ciu_wd = {
758
+
.name = "CIU-W",
759
+
.irq_enable = octeon_irq_ciu_wd_enable,
760
+
.irq_disable = octeon_irq_ciu_disable_all,
761
+
.irq_mask = octeon_irq_dummy_mask,
762
+
};
763
+
764
+
static void octeon_irq_ip2_v1(void)
765
+
{
766
+
const unsigned long core_id = cvmx_get_core_num();
767
+
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
768
+
769
+
ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
770
+
clear_c0_status(STATUSF_IP2);
771
+
if (likely(ciu_sum)) {
772
+
int bit = fls64(ciu_sum) - 1;
773
+
int irq = octeon_irq_ciu_to_irq[0][bit];
774
+
if (likely(irq))
775
+
do_IRQ(irq);
776
+
else
777
+
spurious_interrupt();
778
+
} else {
779
+
spurious_interrupt();
780
+
}
781
+
set_c0_status(STATUSF_IP2);
782
+
}
783
+
784
+
static void octeon_irq_ip2_v2(void)
785
+
{
786
+
const unsigned long core_id = cvmx_get_core_num();
787
+
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
788
+
789
+
ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
790
+
if (likely(ciu_sum)) {
791
+
int bit = fls64(ciu_sum) - 1;
792
+
int irq = octeon_irq_ciu_to_irq[0][bit];
793
+
if (likely(irq))
794
+
do_IRQ(irq);
795
+
else
796
+
spurious_interrupt();
797
+
} else {
798
+
spurious_interrupt();
799
+
}
800
+
}
801
+
static void octeon_irq_ip3_v1(void)
802
+
{
803
+
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
804
+
805
+
ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
806
+
clear_c0_status(STATUSF_IP3);
807
+
if (likely(ciu_sum)) {
808
+
int bit = fls64(ciu_sum) - 1;
809
+
int irq = octeon_irq_ciu_to_irq[1][bit];
810
+
if (likely(irq))
811
+
do_IRQ(irq);
812
+
else
813
+
spurious_interrupt();
814
+
} else {
815
+
spurious_interrupt();
816
+
}
817
+
set_c0_status(STATUSF_IP3);
818
+
}
819
+
820
+
static void octeon_irq_ip3_v2(void)
821
+
{
822
+
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
823
+
824
+
ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
825
+
if (likely(ciu_sum)) {
826
+
int bit = fls64(ciu_sum) - 1;
827
+
int irq = octeon_irq_ciu_to_irq[1][bit];
828
+
if (likely(irq))
829
+
do_IRQ(irq);
830
+
else
831
+
spurious_interrupt();
832
+
} else {
833
+
spurious_interrupt();
834
+
}
835
+
}
836
+
837
+
static void octeon_irq_ip4_mask(void)
838
+
{
839
+
clear_c0_status(STATUSF_IP4);
840
+
spurious_interrupt();
841
+
}
842
+
843
+
static void (*octeon_irq_ip2)(void);
844
+
static void (*octeon_irq_ip3)(void);
845
+
static void (*octeon_irq_ip4)(void);
846
+
847
+
void __cpuinitdata (*octeon_irq_setup_secondary)(void);
848
+
849
+
static void __cpuinit octeon_irq_percpu_enable(void)
850
+
{
851
+
irq_cpu_online();
852
+
}
853
+
854
+
static void __cpuinit octeon_irq_init_ciu_percpu(void)
855
+
{
856
+
int coreid = cvmx_get_core_num();
857
+
/*
858
+
* Disable All CIU Interrupts. The ones we need will be
859
+
* enabled later. Read the SUM register so we know the write
860
+
* completed.
861
+
*/
862
+
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
863
+
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
864
+
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
865
+
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
866
+
cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
867
+
}
868
+
869
+
static void __cpuinit octeon_irq_setup_secondary_ciu(void)
870
+
{
871
+
872
+
__get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
873
+
__get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
874
+
875
+
octeon_irq_init_ciu_percpu();
876
+
octeon_irq_percpu_enable();
877
+
878
+
/* Enable the CIU lines */
879
+
set_c0_status(STATUSF_IP3 | STATUSF_IP2);
880
+
clear_c0_status(STATUSF_IP4);
881
+
}
882
+
883
+
static void __init octeon_irq_init_ciu(void)
884
+
{
885
+
unsigned int i;
886
+
struct irq_chip *chip;
887
+
struct irq_chip *chip_edge;
888
+
struct irq_chip *chip_mbox;
889
+
struct irq_chip *chip_wd;
890
+
891
+
octeon_irq_init_ciu_percpu();
892
+
octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
893
+
894
+
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
895
+
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
896
+
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
897
+
OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
898
+
octeon_irq_ip2 = octeon_irq_ip2_v2;
899
+
octeon_irq_ip3 = octeon_irq_ip3_v2;
900
+
chip = &octeon_irq_chip_ciu_v2;
901
+
chip_edge = &octeon_irq_chip_ciu_edge_v2;
902
+
chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
903
+
chip_wd = &octeon_irq_chip_ciu_wd_v2;
904
+
} else {
905
+
octeon_irq_ip2 = octeon_irq_ip2_v1;
906
+
octeon_irq_ip3 = octeon_irq_ip3_v1;
907
+
chip = &octeon_irq_chip_ciu;
908
+
chip_edge = &octeon_irq_chip_ciu_edge;
909
+
chip_mbox = &octeon_irq_chip_ciu_mbox;
910
+
chip_wd = &octeon_irq_chip_ciu_wd;
911
+
}
912
+
octeon_irq_ip4 = octeon_irq_ip4_mask;
913
+
914
+
/* Mips internal */
915
+
octeon_irq_init_core();
916
+
917
+
/* CIU_0 */
918
+
for (i = 0; i < 16; i++)
919
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
920
+
for (i = 0; i < 16; i++)
921
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq);
922
+
923
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
924
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
925
+
926
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq);
927
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq);
928
+
929
+
for (i = 0; i < 4; i++)
930
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
931
+
for (i = 0; i < 4; i++)
932
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
933
+
934
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq);
935
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
936
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq);
937
+
938
+
for (i = 0; i < 2; i++)
939
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq);
940
+
941
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq);
942
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq);
943
+
944
+
for (i = 0; i < 4; i++)
945
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq);
946
+
947
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
948
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq);
949
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq);
950
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq);
951
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq);
952
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq);
953
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq);
954
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
955
+
956
+
/* CIU_1 */
957
+
for (i = 0; i < 16; i++)
958
+
octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
959
+
960
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq);
961
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
962
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq);
963
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq);
964
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq);
965
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq);
966
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq);
967
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq);
968
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq);
969
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq);
970
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq);
971
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq);
972
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq);
973
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq);
974
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq);
975
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq);
976
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq);
977
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq);
978
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq);
979
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq);
980
+
981
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq);
982
+
983
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq);
984
+
985
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq);
986
+
987
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq);
988
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq);
989
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq);
990
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq);
991
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq);
992
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq);
993
+
octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq);
994
+
995
+
/* Enable the CIU lines */
996
+
set_c0_status(STATUSF_IP3 | STATUSF_IP2);
997
+
clear_c0_status(STATUSF_IP4);
998
+
}
677
999
678
1000
void __init arch_init_irq(void)
679
1001
{
680
-
unsigned int irq;
681
-
struct irq_chip *chip0;
682
-
struct irq_chip *chip0_mbox;
683
-
struct irq_chip *chip1;
684
-
struct irq_chip *chip1_wd;
685
-
686
1002
#ifdef CONFIG_SMP
687
1003
/* Set the default affinity to the boot cpu. */
688
1004
cpumask_clear(irq_default_affinity);
689
1005
cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
690
1006
#endif
691
-
692
-
if (NR_IRQS < OCTEON_IRQ_LAST)
693
-
pr_err("octeon_irq_init: NR_IRQS is set too low\n");
694
-
695
-
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
696
-
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
697
-
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
698
-
octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
699
-
octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
700
-
chip0 = &octeon_irq_chip_ciu0_v2;
701
-
chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
702
-
chip1 = &octeon_irq_chip_ciu1_v2;
703
-
chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
704
-
} else {
705
-
octeon_ciu0_ack = octeon_irq_ciu0_ack;
706
-
octeon_ciu1_ack = octeon_irq_ciu1_ack;
707
-
chip0 = &octeon_irq_chip_ciu0;
708
-
chip0_mbox = &octeon_irq_chip_ciu0_mbox;
709
-
chip1 = &octeon_irq_chip_ciu1;
710
-
chip1_wd = &octeon_irq_chip_ciu1_wd;
711
-
}
712
-
713
-
/* 0 - 15 reserved for i8259 master and slave controller. */
714
-
715
-
/* 17 - 23 Mips internal */
716
-
for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
717
-
set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
718
-
handle_percpu_irq);
719
-
}
720
-
721
-
/* 24 - 87 CIU_INT_SUM0 */
722
-
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
723
-
switch (irq) {
724
-
case OCTEON_IRQ_MBOX0:
725
-
case OCTEON_IRQ_MBOX1:
726
-
set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
727
-
break;
728
-
default:
729
-
set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
730
-
break;
731
-
}
732
-
}
733
-
734
-
/* 88 - 151 CIU_INT_SUM1 */
735
-
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
736
-
set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
737
-
738
-
for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
739
-
set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
740
-
741
-
set_c0_status(0x300 << 2);
1007
+
octeon_irq_init_ciu();
742
1008
}
743
1009
744
1010
asmlinkage void plat_irq_dispatch(void)
745
1011
{
746
-
const unsigned long core_id = cvmx_get_core_num();
747
-
const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
748
-
const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
749
-
const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
750
-
const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
751
1012
unsigned long cop0_cause;
752
1013
unsigned long cop0_status;
753
-
uint64_t ciu_en;
754
-
uint64_t ciu_sum;
755
-
unsigned int irq;
756
1014
757
1015
while (1) {
758
1016
cop0_cause = read_c0_cause();
···
1021
757
cop0_cause &= cop0_status;
1022
758
cop0_cause &= ST0_IM;
1023
759
1024
-
if (unlikely(cop0_cause & STATUSF_IP2)) {
1025
-
ciu_sum = cvmx_read_csr(ciu_sum0_address);
1026
-
ciu_en = cvmx_read_csr(ciu_en0_address);
1027
-
ciu_sum &= ciu_en;
1028
-
if (likely(ciu_sum)) {
1029
-
irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
1030
-
octeon_ciu0_ack(irq);
1031
-
do_IRQ(irq);
1032
-
} else {
1033
-
spurious_interrupt();
1034
-
}
1035
-
} else if (unlikely(cop0_cause & STATUSF_IP3)) {
1036
-
ciu_sum = cvmx_read_csr(ciu_sum1_address);
1037
-
ciu_en = cvmx_read_csr(ciu_en1_address);
1038
-
ciu_sum &= ciu_en;
1039
-
if (likely(ciu_sum)) {
1040
-
irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
1041
-
octeon_ciu1_ack(irq);
1042
-
do_IRQ(irq);
1043
-
} else {
1044
-
spurious_interrupt();
1045
-
}
1046
-
} else if (likely(cop0_cause)) {
760
+
if (unlikely(cop0_cause & STATUSF_IP2))
761
+
octeon_irq_ip2();
762
+
else if (unlikely(cop0_cause & STATUSF_IP3))
763
+
octeon_irq_ip3();
764
+
else if (unlikely(cop0_cause & STATUSF_IP4))
765
+
octeon_irq_ip4();
766
+
else if (likely(cop0_cause))
1047
767
do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
1048
-
} else {
768
+
else
1049
769
break;
1050
-
}
1051
770
}
1052
771
}
1053
772
···
1038
791
1039
792
void fixup_irqs(void)
1040
793
{
1041
-
int irq;
1042
-
struct irq_desc *desc;
1043
-
cpumask_t new_affinity;
1044
-
unsigned long flags;
1045
-
int do_set_affinity;
1046
-
int cpu;
1047
-
1048
-
cpu = smp_processor_id();
1049
-
1050
-
for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
1051
-
octeon_irq_core_disable_local(irq);
1052
-
1053
-
for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
1054
-
desc = irq_to_desc(irq);
1055
-
switch (irq) {
1056
-
case OCTEON_IRQ_MBOX0:
1057
-
case OCTEON_IRQ_MBOX1:
1058
-
/* The eoi function will disable them on this CPU. */
1059
-
desc->chip->eoi(irq);
1060
-
break;
1061
-
case OCTEON_IRQ_WDOG0:
1062
-
case OCTEON_IRQ_WDOG1:
1063
-
case OCTEON_IRQ_WDOG2:
1064
-
case OCTEON_IRQ_WDOG3:
1065
-
case OCTEON_IRQ_WDOG4:
1066
-
case OCTEON_IRQ_WDOG5:
1067
-
case OCTEON_IRQ_WDOG6:
1068
-
case OCTEON_IRQ_WDOG7:
1069
-
case OCTEON_IRQ_WDOG8:
1070
-
case OCTEON_IRQ_WDOG9:
1071
-
case OCTEON_IRQ_WDOG10:
1072
-
case OCTEON_IRQ_WDOG11:
1073
-
case OCTEON_IRQ_WDOG12:
1074
-
case OCTEON_IRQ_WDOG13:
1075
-
case OCTEON_IRQ_WDOG14:
1076
-
case OCTEON_IRQ_WDOG15:
1077
-
/*
1078
-
* These have special per CPU semantics and
1079
-
* are handled in the watchdog driver.
1080
-
*/
1081
-
break;
1082
-
default:
1083
-
raw_spin_lock_irqsave(&desc->lock, flags);
1084
-
/*
1085
-
* If this irq has an action, it is in use and
1086
-
* must be migrated if it has affinity to this
1087
-
* cpu.
1088
-
*/
1089
-
if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
1090
-
if (cpumask_weight(desc->affinity) > 1) {
1091
-
/*
1092
-
* It has multi CPU affinity,
1093
-
* just remove this CPU from
1094
-
* the affinity set.
1095
-
*/
1096
-
cpumask_copy(&new_affinity, desc->affinity);
1097
-
cpumask_clear_cpu(cpu, &new_affinity);
1098
-
} else {
1099
-
/*
1100
-
* Otherwise, put it on lowest
1101
-
* numbered online CPU.
1102
-
*/
1103
-
cpumask_clear(&new_affinity);
1104
-
cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
1105
-
}
1106
-
do_set_affinity = 1;
1107
-
} else {
1108
-
do_set_affinity = 0;
1109
-
}
1110
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
1111
-
1112
-
if (do_set_affinity)
1113
-
irq_set_affinity(irq, &new_affinity);
1114
-
1115
-
break;
1116
-
}
1117
-
}
794
+
irq_cpu_offline();
1118
795
}
1119
796
1120
797
#endif /* CONFIG_HOTPLUG_CPU */
-12
arch/mips/cavium-octeon/setup.c
-12
arch/mips/cavium-octeon/setup.c
···
420
420
void __init prom_init(void)
421
421
{
422
422
struct cvmx_sysinfo *sysinfo;
423
-
const int coreid = cvmx_get_core_num();
424
423
int i;
425
424
int argc;
426
425
#ifdef CONFIG_CAVIUM_RESERVE32
···
535
536
octeon_check_cpu_bist();
536
537
537
538
octeon_uart = octeon_get_boot_uart();
538
-
539
-
/*
540
-
* Disable All CIU Interrupts. The ones we need will be
541
-
* enabled later. Read the SUM register so we know the write
542
-
* completed.
543
-
*/
544
-
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
545
-
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
546
-
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
547
-
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
548
-
cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
549
539
550
540
#ifdef CONFIG_SMP
551
541
octeon_write_lcd("LinuxSMP");
+18
-31
arch/mips/cavium-octeon/smp.c
+18
-31
arch/mips/cavium-octeon/smp.c
···
171
171
* After we've done initial boot, this function is called to allow the
172
172
* board code to clean up state, if needed
173
173
*/
174
-
static void octeon_init_secondary(void)
174
+
static void __cpuinit octeon_init_secondary(void)
175
175
{
176
-
const int coreid = cvmx_get_core_num();
177
-
union cvmx_ciu_intx_sum0 interrupt_enable;
178
176
unsigned int sr;
179
177
178
+
sr = set_c0_status(ST0_BEV);
179
+
write_c0_ebase((u32)ebase);
180
+
write_c0_status(sr);
181
+
182
+
octeon_check_cpu_bist();
183
+
octeon_init_cvmcount();
184
+
185
+
octeon_irq_setup_secondary();
186
+
raw_local_irq_enable();
187
+
}
188
+
189
+
/**
190
+
* Callout to firmware before smp_init
191
+
*
192
+
*/
193
+
void octeon_prepare_cpus(unsigned int max_cpus)
194
+
{
180
195
#ifdef CONFIG_HOTPLUG_CPU
181
196
struct linux_app_boot_info *labi;
182
197
···
201
186
panic("The bootloader version on this board is incorrect.");
202
187
#endif
203
188
204
-
sr = set_c0_status(ST0_BEV);
205
-
write_c0_ebase((u32)ebase);
206
-
write_c0_status(sr);
207
-
208
-
octeon_check_cpu_bist();
209
-
octeon_init_cvmcount();
210
-
/*
211
-
pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
212
-
*/
213
-
/* Enable Mailbox interrupts to this core. These are the only
214
-
interrupts allowed on line 3 */
215
-
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
216
-
interrupt_enable.u64 = 0;
217
-
interrupt_enable.s.mbox = 0x3;
218
-
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
219
-
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
220
-
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
221
-
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
222
-
/* Enable core interrupt processing for 2,3 and 7 */
223
-
set_c0_status(0x8c01);
224
-
}
225
-
226
-
/**
227
-
* Callout to firmware before smp_init
228
-
*
229
-
*/
230
-
void octeon_prepare_cpus(unsigned int max_cpus)
231
-
{
232
189
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
233
190
if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
234
191
"mailbox0", mailbox_interrupt)) {
+2
-2
arch/mips/dec/ioasic-irq.c
+2
-2
arch/mips/dec/ioasic-irq.c
···
68
68
fast_iob();
69
69
70
70
for (i = base; i < base + IO_INR_DMA; i++)
71
-
set_irq_chip_and_handler(i, &ioasic_irq_type,
71
+
irq_set_chip_and_handler(i, &ioasic_irq_type,
72
72
handle_level_irq);
73
73
for (; i < base + IO_IRQ_LINES; i++)
74
-
set_irq_chip(i, &ioasic_dma_irq_type);
74
+
irq_set_chip(i, &ioasic_dma_irq_type);
75
75
76
76
ioasic_irq_base = base;
77
77
}
+1
-1
arch/mips/dec/kn02-irq.c
+1
-1
arch/mips/dec/kn02-irq.c
+3
-3
arch/mips/emma/markeins/irq.c
+3
-3
arch/mips/emma/markeins/irq.c
···
69
69
u32 i;
70
70
71
71
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
72
-
set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
72
+
irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
73
73
&emma2rh_irq_controller,
74
74
handle_level_irq, "level");
75
75
}
···
105
105
u32 i;
106
106
107
107
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
108
-
set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
108
+
irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
109
109
&emma2rh_sw_irq_controller,
110
110
handle_level_irq, "level");
111
111
}
···
162
162
u32 i;
163
163
164
164
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
165
-
set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
165
+
irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
166
166
&emma2rh_gpio_irq_controller,
167
167
handle_edge_irq, "edge");
168
168
}
+81
-162
arch/mips/include/asm/mach-cavium-octeon/irq.h
+81
-162
arch/mips/include/asm/mach-cavium-octeon/irq.h
···
11
11
#define NR_IRQS OCTEON_IRQ_LAST
12
12
#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13
13
14
-
/* 0 - 7 represent the i8259 master */
15
-
#define OCTEON_IRQ_I8259M0 0
16
-
#define OCTEON_IRQ_I8259M1 1
17
-
#define OCTEON_IRQ_I8259M2 2
18
-
#define OCTEON_IRQ_I8259M3 3
19
-
#define OCTEON_IRQ_I8259M4 4
20
-
#define OCTEON_IRQ_I8259M5 5
21
-
#define OCTEON_IRQ_I8259M6 6
22
-
#define OCTEON_IRQ_I8259M7 7
23
-
/* 8 - 15 represent the i8259 slave */
24
-
#define OCTEON_IRQ_I8259S0 8
25
-
#define OCTEON_IRQ_I8259S1 9
26
-
#define OCTEON_IRQ_I8259S2 10
27
-
#define OCTEON_IRQ_I8259S3 11
28
-
#define OCTEON_IRQ_I8259S4 12
29
-
#define OCTEON_IRQ_I8259S5 13
30
-
#define OCTEON_IRQ_I8259S6 14
31
-
#define OCTEON_IRQ_I8259S7 15
32
-
/* 16 - 23 represent the 8 MIPS standard interrupt sources */
33
-
#define OCTEON_IRQ_SW0 16
34
-
#define OCTEON_IRQ_SW1 17
35
-
#define OCTEON_IRQ_CIU0 18
36
-
#define OCTEON_IRQ_CIU1 19
37
-
#define OCTEON_IRQ_CIU4 20
38
-
#define OCTEON_IRQ_5 21
39
-
#define OCTEON_IRQ_PERF 22
40
-
#define OCTEON_IRQ_TIMER 23
41
-
/* 24 - 87 represent the sources in CIU_INTX_EN0 */
42
-
#define OCTEON_IRQ_WORKQ0 24
43
-
#define OCTEON_IRQ_WORKQ1 25
44
-
#define OCTEON_IRQ_WORKQ2 26
45
-
#define OCTEON_IRQ_WORKQ3 27
46
-
#define OCTEON_IRQ_WORKQ4 28
47
-
#define OCTEON_IRQ_WORKQ5 29
48
-
#define OCTEON_IRQ_WORKQ6 30
49
-
#define OCTEON_IRQ_WORKQ7 31
50
-
#define OCTEON_IRQ_WORKQ8 32
51
-
#define OCTEON_IRQ_WORKQ9 33
52
-
#define OCTEON_IRQ_WORKQ10 34
53
-
#define OCTEON_IRQ_WORKQ11 35
54
-
#define OCTEON_IRQ_WORKQ12 36
55
-
#define OCTEON_IRQ_WORKQ13 37
56
-
#define OCTEON_IRQ_WORKQ14 38
57
-
#define OCTEON_IRQ_WORKQ15 39
58
-
#define OCTEON_IRQ_GPIO0 40
59
-
#define OCTEON_IRQ_GPIO1 41
60
-
#define OCTEON_IRQ_GPIO2 42
61
-
#define OCTEON_IRQ_GPIO3 43
62
-
#define OCTEON_IRQ_GPIO4 44
63
-
#define OCTEON_IRQ_GPIO5 45
64
-
#define OCTEON_IRQ_GPIO6 46
65
-
#define OCTEON_IRQ_GPIO7 47
66
-
#define OCTEON_IRQ_GPIO8 48
67
-
#define OCTEON_IRQ_GPIO9 49
68
-
#define OCTEON_IRQ_GPIO10 50
69
-
#define OCTEON_IRQ_GPIO11 51
70
-
#define OCTEON_IRQ_GPIO12 52
71
-
#define OCTEON_IRQ_GPIO13 53
72
-
#define OCTEON_IRQ_GPIO14 54
73
-
#define OCTEON_IRQ_GPIO15 55
74
-
#define OCTEON_IRQ_MBOX0 56
75
-
#define OCTEON_IRQ_MBOX1 57
76
-
#define OCTEON_IRQ_UART0 58
77
-
#define OCTEON_IRQ_UART1 59
78
-
#define OCTEON_IRQ_PCI_INT0 60
79
-
#define OCTEON_IRQ_PCI_INT1 61
80
-
#define OCTEON_IRQ_PCI_INT2 62
81
-
#define OCTEON_IRQ_PCI_INT3 63
82
-
#define OCTEON_IRQ_PCI_MSI0 64
83
-
#define OCTEON_IRQ_PCI_MSI1 65
84
-
#define OCTEON_IRQ_PCI_MSI2 66
85
-
#define OCTEON_IRQ_PCI_MSI3 67
86
-
#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */
87
-
#define OCTEON_IRQ_TWSI 69
88
-
#define OCTEON_IRQ_RML 70
89
-
#define OCTEON_IRQ_TRACE 71
90
-
#define OCTEON_IRQ_GMX_DRP0 72
91
-
#define OCTEON_IRQ_GMX_DRP1 73
92
-
#define OCTEON_IRQ_IPD_DRP 74
93
-
#define OCTEON_IRQ_KEY_ZERO 75
94
-
#define OCTEON_IRQ_TIMER0 76
95
-
#define OCTEON_IRQ_TIMER1 77
96
-
#define OCTEON_IRQ_TIMER2 78
97
-
#define OCTEON_IRQ_TIMER3 79
98
-
#define OCTEON_IRQ_USB0 80
99
-
#define OCTEON_IRQ_PCM 81
100
-
#define OCTEON_IRQ_MPI 82
101
-
#define OCTEON_IRQ_TWSI2 83
102
-
#define OCTEON_IRQ_POWIQ 84
103
-
#define OCTEON_IRQ_IPDPPTHR 85
104
-
#define OCTEON_IRQ_MII0 86
105
-
#define OCTEON_IRQ_BOOTDMA 87
106
-
/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107
-
#define OCTEON_IRQ_WDOG0 88
108
-
#define OCTEON_IRQ_WDOG1 89
109
-
#define OCTEON_IRQ_WDOG2 90
110
-
#define OCTEON_IRQ_WDOG3 91
111
-
#define OCTEON_IRQ_WDOG4 92
112
-
#define OCTEON_IRQ_WDOG5 93
113
-
#define OCTEON_IRQ_WDOG6 94
114
-
#define OCTEON_IRQ_WDOG7 95
115
-
#define OCTEON_IRQ_WDOG8 96
116
-
#define OCTEON_IRQ_WDOG9 97
117
-
#define OCTEON_IRQ_WDOG10 98
118
-
#define OCTEON_IRQ_WDOG11 99
119
-
#define OCTEON_IRQ_WDOG12 100
120
-
#define OCTEON_IRQ_WDOG13 101
121
-
#define OCTEON_IRQ_WDOG14 102
122
-
#define OCTEON_IRQ_WDOG15 103
123
-
#define OCTEON_IRQ_UART2 104
124
-
#define OCTEON_IRQ_USB1 105
125
-
#define OCTEON_IRQ_MII1 106
126
-
#define OCTEON_IRQ_RESERVED107 107
127
-
#define OCTEON_IRQ_RESERVED108 108
128
-
#define OCTEON_IRQ_RESERVED109 109
129
-
#define OCTEON_IRQ_RESERVED110 110
130
-
#define OCTEON_IRQ_RESERVED111 111
131
-
#define OCTEON_IRQ_RESERVED112 112
132
-
#define OCTEON_IRQ_RESERVED113 113
133
-
#define OCTEON_IRQ_RESERVED114 114
134
-
#define OCTEON_IRQ_RESERVED115 115
135
-
#define OCTEON_IRQ_RESERVED116 116
136
-
#define OCTEON_IRQ_RESERVED117 117
137
-
#define OCTEON_IRQ_RESERVED118 118
138
-
#define OCTEON_IRQ_RESERVED119 119
139
-
#define OCTEON_IRQ_RESERVED120 120
140
-
#define OCTEON_IRQ_RESERVED121 121
141
-
#define OCTEON_IRQ_RESERVED122 122
142
-
#define OCTEON_IRQ_RESERVED123 123
143
-
#define OCTEON_IRQ_RESERVED124 124
144
-
#define OCTEON_IRQ_RESERVED125 125
145
-
#define OCTEON_IRQ_RESERVED126 126
146
-
#define OCTEON_IRQ_RESERVED127 127
147
-
#define OCTEON_IRQ_RESERVED128 128
148
-
#define OCTEON_IRQ_RESERVED129 129
149
-
#define OCTEON_IRQ_RESERVED130 130
150
-
#define OCTEON_IRQ_RESERVED131 131
151
-
#define OCTEON_IRQ_RESERVED132 132
152
-
#define OCTEON_IRQ_RESERVED133 133
153
-
#define OCTEON_IRQ_RESERVED134 134
154
-
#define OCTEON_IRQ_RESERVED135 135
155
-
#define OCTEON_IRQ_RESERVED136 136
156
-
#define OCTEON_IRQ_RESERVED137 137
157
-
#define OCTEON_IRQ_RESERVED138 138
158
-
#define OCTEON_IRQ_RESERVED139 139
159
-
#define OCTEON_IRQ_RESERVED140 140
160
-
#define OCTEON_IRQ_RESERVED141 141
161
-
#define OCTEON_IRQ_RESERVED142 142
162
-
#define OCTEON_IRQ_RESERVED143 143
163
-
#define OCTEON_IRQ_RESERVED144 144
164
-
#define OCTEON_IRQ_RESERVED145 145
165
-
#define OCTEON_IRQ_RESERVED146 146
166
-
#define OCTEON_IRQ_RESERVED147 147
167
-
#define OCTEON_IRQ_RESERVED148 148
168
-
#define OCTEON_IRQ_RESERVED149 149
169
-
#define OCTEON_IRQ_RESERVED150 150
170
-
#define OCTEON_IRQ_RESERVED151 151
14
+
enum octeon_irq {
15
+
/* 1 - 8 represent the 8 MIPS standard interrupt sources */
16
+
OCTEON_IRQ_SW0 = 1,
17
+
OCTEON_IRQ_SW1,
18
+
/* CIU0, CUI2, CIU4 are 3, 4, 5 */
19
+
OCTEON_IRQ_5 = 6,
20
+
OCTEON_IRQ_PERF,
21
+
OCTEON_IRQ_TIMER,
22
+
/* sources in CIU_INTX_EN0 */
23
+
OCTEON_IRQ_WORKQ0,
24
+
OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
25
+
OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
26
+
OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
27
+
OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
28
+
OCTEON_IRQ_MBOX1,
29
+
OCTEON_IRQ_UART0,
30
+
OCTEON_IRQ_UART1,
31
+
OCTEON_IRQ_UART2,
32
+
OCTEON_IRQ_PCI_INT0,
33
+
OCTEON_IRQ_PCI_INT1,
34
+
OCTEON_IRQ_PCI_INT2,
35
+
OCTEON_IRQ_PCI_INT3,
36
+
OCTEON_IRQ_PCI_MSI0,
37
+
OCTEON_IRQ_PCI_MSI1,
38
+
OCTEON_IRQ_PCI_MSI2,
39
+
OCTEON_IRQ_PCI_MSI3,
40
+
41
+
OCTEON_IRQ_TWSI,
42
+
OCTEON_IRQ_TWSI2,
43
+
OCTEON_IRQ_RML,
44
+
OCTEON_IRQ_TRACE0,
45
+
OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
46
+
OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
47
+
OCTEON_IRQ_KEY_ZERO,
48
+
OCTEON_IRQ_TIMER0,
49
+
OCTEON_IRQ_TIMER1,
50
+
OCTEON_IRQ_TIMER2,
51
+
OCTEON_IRQ_TIMER3,
52
+
OCTEON_IRQ_USB0,
53
+
OCTEON_IRQ_USB1,
54
+
OCTEON_IRQ_PCM,
55
+
OCTEON_IRQ_MPI,
56
+
OCTEON_IRQ_POWIQ,
57
+
OCTEON_IRQ_IPDPPTHR,
58
+
OCTEON_IRQ_MII0,
59
+
OCTEON_IRQ_MII1,
60
+
OCTEON_IRQ_BOOTDMA,
61
+
62
+
OCTEON_IRQ_NAND,
63
+
OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */
64
+
OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
65
+
OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
66
+
OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
67
+
OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
68
+
OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
69
+
OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
70
+
OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
71
+
OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
72
+
OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
73
+
OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
74
+
OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
75
+
OCTEON_IRQ_DFA, /* Summary of DFA */
76
+
OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
77
+
OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
78
+
OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
79
+
OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
80
+
OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
81
+
OCTEON_IRQ_PTP,
82
+
OCTEON_IRQ_PEM0,
83
+
OCTEON_IRQ_PEM1,
84
+
OCTEON_IRQ_SRIO0,
85
+
OCTEON_IRQ_SRIO1,
86
+
OCTEON_IRQ_LMC0,
87
+
OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
88
+
OCTEON_IRQ_RST,
89
+
};
171
90
172
91
#ifdef CONFIG_PCI_MSI
173
-
/* 152 - 215 represent the MSI interrupts 0-63 */
174
-
#define OCTEON_IRQ_MSI_BIT0 152
175
-
#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
92
+
/* 152 - 407 represent the MSI interrupts 0-255 */
93
+
#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1)
176
94
177
-
#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
95
+
#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
96
+
#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
178
97
#else
179
-
#define OCTEON_IRQ_LAST 152
98
+
#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
180
99
#endif
181
100
182
101
#endif
+2
arch/mips/include/asm/octeon/octeon.h
+2
arch/mips/include/asm/octeon/octeon.h
+1
-1
arch/mips/include/asm/unistd.h
+1
-1
arch/mips/include/asm/unistd.h
···
1005
1005
#define __NR_name_to_handle_at (__NR_Linux + 303)
1006
1006
#define __NR_open_by_handle_at (__NR_Linux + 304)
1007
1007
#define __NR_clock_adjtime (__NR_Linux + 305)
1008
-
#define __NR_clock_adjtime (__NR_Linux + 306)
1008
+
#define __NR_syncfs (__NR_Linux + 306)
1009
1009
1010
1010
/*
1011
1011
* Offset of the last N32 flavoured syscall
+1
-1
arch/mips/jazz/irq.c
+1
-1
arch/mips/jazz/irq.c
···
56
56
int i;
57
57
58
58
for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
59
-
set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
59
+
irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
60
60
61
61
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
62
62
r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
+7
-7
arch/mips/jz4740/gpio.c
+7
-7
arch/mips/jz4740/gpio.c
···
306
306
uint32_t flag;
307
307
unsigned int gpio_irq;
308
308
unsigned int gpio_bank;
309
-
struct jz_gpio_chip *chip = get_irq_desc_data(desc);
309
+
struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
310
310
311
311
gpio_bank = JZ4740_IRQ_GPIO0 - irq;
312
312
···
416
416
chip->wakeup &= ~IRQ_TO_BIT(data->irq);
417
417
spin_unlock(&chip->lock);
418
418
419
-
set_irq_wake(chip->irq, on);
419
+
irq_set_irq_wake(chip->irq, on);
420
420
return 0;
421
421
}
422
422
···
510
510
gpiochip_add(&chip->gpio_chip);
511
511
512
512
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
513
-
set_irq_data(chip->irq, chip);
514
-
set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
513
+
irq_set_handler_data(chip->irq, chip);
514
+
irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
515
515
516
516
for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
517
517
irq_set_lockdep_class(irq, &gpio_lock_class);
518
-
set_irq_chip_data(irq, chip);
519
-
set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
520
-
handle_level_irq);
518
+
irq_set_chip_data(irq, chip);
519
+
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
520
+
handle_level_irq);
521
521
}
522
522
523
523
return 0;
+2
-2
arch/mips/jz4740/irq.c
+2
-2
arch/mips/jz4740/irq.c
···
104
104
writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
105
105
106
106
for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
107
-
set_irq_chip_data(i, (void *)IRQ_BIT(i));
108
-
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
107
+
irq_set_chip_data(i, (void *)IRQ_BIT(i));
108
+
irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
109
109
}
110
110
111
111
setup_irq(2, &jz4740_cascade_action);
+3
-3
arch/mips/kernel/i8259.c
+3
-3
arch/mips/kernel/i8259.c
···
110
110
void make_8259A_irq(unsigned int irq)
111
111
{
112
112
disable_irq_nosync(irq);
113
-
set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
113
+
irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
114
114
enable_irq(irq);
115
115
}
116
116
···
336
336
init_8259A(0);
337
337
338
338
for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
339
-
set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
340
-
set_irq_probe(i);
339
+
irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
340
+
irq_set_probe(i);
341
341
}
342
342
343
343
setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
+1
-1
arch/mips/kernel/irq-gic.c
+1
-1
arch/mips/kernel/irq-gic.c
+2
-2
arch/mips/kernel/irq-gt641xx.c
+2
-2
arch/mips/kernel/irq-gt641xx.c
+8
-4
arch/mips/kernel/irq-msc01.c
+8
-4
arch/mips/kernel/irq-msc01.c
···
137
137
138
138
switch (imp->im_type) {
139
139
case MSC01_IRQ_EDGE:
140
-
set_irq_chip_and_handler_name(irqbase + n,
141
-
&msc_edgeirq_type, handle_edge_irq, "edge");
140
+
irq_set_chip_and_handler_name(irqbase + n,
141
+
&msc_edgeirq_type,
142
+
handle_edge_irq,
143
+
"edge");
142
144
if (cpu_has_veic)
143
145
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
144
146
else
145
147
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
146
148
break;
147
149
case MSC01_IRQ_LEVEL:
148
-
set_irq_chip_and_handler_name(irqbase+n,
149
-
&msc_levelirq_type, handle_level_irq, "level");
150
+
irq_set_chip_and_handler_name(irqbase + n,
151
+
&msc_levelirq_type,
152
+
handle_level_irq,
153
+
"level");
150
154
if (cpu_has_veic)
151
155
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
152
156
else
+1
-1
arch/mips/kernel/irq-rm7000.c
+1
-1
arch/mips/kernel/irq-rm7000.c
+2
-2
arch/mips/kernel/irq-rm9000.c
+2
-2
arch/mips/kernel/irq-rm9000.c
···
98
98
clear_c0_intcontrol(0x0000f000); /* Mask all */
99
99
100
100
for (i = base; i < base + 4; i++)
101
-
set_irq_chip_and_handler(i, &rm9k_irq_controller,
101
+
irq_set_chip_and_handler(i, &rm9k_irq_controller,
102
102
handle_level_irq);
103
103
104
104
rm9000_perfcount_irq = base + 1;
105
-
set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
105
+
irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
106
106
handle_percpu_irq);
107
107
}
+1
-1
arch/mips/kernel/irq.c
+1
-1
arch/mips/kernel/irq.c
+2
-2
arch/mips/kernel/irq_cpu.c
+2
-2
arch/mips/kernel/irq_cpu.c
···
109
109
*/
110
110
if (cpu_has_mipsmt)
111
111
for (i = irq_base; i < irq_base + 2; i++)
112
-
set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
112
+
irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
113
113
handle_percpu_irq);
114
114
115
115
for (i = irq_base + 2; i < irq_base + 8; i++)
116
-
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
116
+
irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
117
117
handle_percpu_irq);
118
118
}
+2
-2
arch/mips/kernel/irq_txx9.c
+2
-2
arch/mips/kernel/irq_txx9.c
···
154
154
for (i = 0; i < TXx9_MAX_IR; i++) {
155
155
txx9irq[i].level = 4; /* middle level */
156
156
txx9irq[i].mode = TXx9_IRCR_LOW;
157
-
set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
158
-
&txx9_irq_chip, handle_level_irq);
157
+
irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip,
158
+
handle_level_irq);
159
159
}
160
160
161
161
/* mask all IRC interrupts */
+1
-1
arch/mips/kernel/smtc.c
+1
-1
arch/mips/kernel/smtc.c
+1
-1
arch/mips/lasat/interrupt.c
+1
-1
arch/mips/lasat/interrupt.c
···
128
128
mips_cpu_irq_init();
129
129
130
130
for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
131
-
set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
131
+
irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
132
132
133
133
setup_irq(LASAT_CASCADE_IRQ, &cascade);
134
134
}
+2
-1
arch/mips/loongson/common/bonito-irq.c
+2
-1
arch/mips/loongson/common/bonito-irq.c
···
44
44
u32 i;
45
45
46
46
for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
47
-
set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
47
+
irq_set_chip_and_handler(i, &bonito_irq_type,
48
+
handle_level_irq);
48
49
49
50
#ifdef CONFIG_CPU_LOONGSON2E
50
51
setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
+1
-1
arch/mips/mti-malta/malta-int.c
+1
-1
arch/mips/mti-malta/malta-int.c
+1
-1
arch/mips/mti-malta/malta-time.c
+1
-1
arch/mips/mti-malta/malta-time.c
···
119
119
set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
120
120
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
121
121
#ifdef CONFIG_SMP
122
-
set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
122
+
irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
123
123
#endif
124
124
}
125
125
}
+12
-12
arch/mips/pci/msi-octeon.c
+12
-12
arch/mips/pci/msi-octeon.c
···
172
172
pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
173
173
control);
174
174
175
-
set_irq_msi(irq, desc);
175
+
irq_set_msi_desc(irq, desc);
176
176
write_msi_msg(irq, &msg);
177
177
return 0;
178
178
}
···
259
259
static u64 msi_rcv_reg[4];
260
260
static u64 mis_ena_reg[4];
261
261
262
-
static void octeon_irq_msi_enable_pcie(unsigned int irq)
262
+
static void octeon_irq_msi_enable_pcie(struct irq_data *data)
263
263
{
264
264
u64 en;
265
265
unsigned long flags;
266
-
int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
266
+
int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
267
267
int irq_index = msi_number >> 6;
268
268
int irq_bit = msi_number & 0x3f;
269
269
···
275
275
raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
276
276
}
277
277
278
-
static void octeon_irq_msi_disable_pcie(unsigned int irq)
278
+
static void octeon_irq_msi_disable_pcie(struct irq_data *data)
279
279
{
280
280
u64 en;
281
281
unsigned long flags;
282
-
int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
282
+
int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
283
283
int irq_index = msi_number >> 6;
284
284
int irq_bit = msi_number & 0x3f;
285
285
···
293
293
294
294
static struct irq_chip octeon_irq_chip_msi_pcie = {
295
295
.name = "MSI",
296
-
.enable = octeon_irq_msi_enable_pcie,
297
-
.disable = octeon_irq_msi_disable_pcie,
296
+
.irq_enable = octeon_irq_msi_enable_pcie,
297
+
.irq_disable = octeon_irq_msi_disable_pcie,
298
298
};
299
299
300
-
static void octeon_irq_msi_enable_pci(unsigned int irq)
300
+
static void octeon_irq_msi_enable_pci(struct irq_data *data)
301
301
{
302
302
/*
303
303
* Octeon PCI doesn't have the ability to mask/unmask MSI
···
308
308
*/
309
309
}
310
310
311
-
static void octeon_irq_msi_disable_pci(unsigned int irq)
311
+
static void octeon_irq_msi_disable_pci(struct irq_data *data)
312
312
{
313
313
/* See comment in enable */
314
314
}
315
315
316
316
static struct irq_chip octeon_irq_chip_msi_pci = {
317
317
.name = "MSI",
318
-
.enable = octeon_irq_msi_enable_pci,
319
-
.disable = octeon_irq_msi_disable_pci,
318
+
.irq_enable = octeon_irq_msi_enable_pci,
319
+
.irq_disable = octeon_irq_msi_disable_pci,
320
320
};
321
321
322
322
/*
···
388
388
}
389
389
390
390
for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
391
-
set_irq_chip_and_handler(irq, msi, handle_simple_irq);
391
+
irq_set_chip_and_handler(irq, msi, handle_simple_irq);
392
392
393
393
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
394
394
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
+1
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+1
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
···
182
182
183
183
/* initialize all the IRQ descriptors */
184
184
for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
185
-
set_irq_chip_and_handler(i, &msp_cic_irq_controller,
185
+
irq_set_chip_and_handler(i, &msp_cic_irq_controller,
186
186
handle_level_irq);
187
187
#ifdef CONFIG_MIPS_MT_SMTC
188
188
/* Mask of CIC interrupt */
+1
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+1
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+1
-1
arch/mips/pmc-sierra/msp71xx/msp_smp.c
+1
-1
arch/mips/pmc-sierra/msp71xx/msp_smp.c
+4
-2
arch/mips/pnx833x/common/interrupts.c
+4
-2
arch/mips/pnx833x/common/interrupts.c
···
259
259
/* Set IRQ information in irq_desc */
260
260
for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
261
261
pnx833x_hard_disable_pic_irq(irq);
262
-
set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
262
+
irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
263
+
handle_simple_irq);
263
264
}
264
265
265
266
for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
266
-
set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
267
+
irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
268
+
handle_simple_irq);
267
269
268
270
/* Set PIC priority limiter register to 0 */
269
271
PNX833X_PIC_INT_PRIORITY = 0;
+5
-5
arch/mips/pnx8550/common/int.c
+5
-5
arch/mips/pnx8550/common/int.c
···
183
183
int configPR;
184
184
185
185
for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
186
-
set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
186
+
irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
187
187
188
188
/* init of GIC/IPC interrupts */
189
189
/* should be done before cp0 since cp0 init enables the GIC int */
···
206
206
/* mask/priority is still 0 so we will not get any
207
207
* interrupts until it is unmasked */
208
208
209
-
set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
209
+
irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
210
210
}
211
211
212
212
/* Priority level 0 */
···
215
215
/* Set int vector table address */
216
216
PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
217
217
218
-
set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
218
+
irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
219
219
handle_level_irq);
220
220
setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
221
221
222
222
/* init of Timer interrupts */
223
223
for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
224
-
set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
224
+
irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
225
225
226
226
/* Stop Timer 1-3 */
227
227
configPR = read_c0_config7();
228
228
configPR |= 0x00000038;
229
229
write_c0_config7(configPR);
230
230
231
-
set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
231
+
irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
232
232
handle_level_irq);
233
233
setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
234
234
}
+1
-1
arch/mips/powertv/asic/irq_asic.c
+1
-1
arch/mips/powertv/asic/irq_asic.c
+2
-2
arch/mips/rb532/irq.c
+2
-2
arch/mips/rb532/irq.c
···
207
207
pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
208
208
209
209
for (i = 0; i < RC32434_NR_IRQS; i++)
210
-
set_irq_chip_and_handler(i, &rc32434_irq_type,
211
-
handle_level_irq);
210
+
irq_set_chip_and_handler(i, &rc32434_irq_type,
211
+
handle_level_irq);
212
212
}
213
213
214
214
/* Main Interrupt dispatcher */
+1
-1
arch/mips/sgi-ip22/ip22-int.c
+1
-1
arch/mips/sgi-ip22/ip22-int.c
+1
-1
arch/mips/sgi-ip27/ip27-irq.c
+1
-1
arch/mips/sgi-ip27/ip27-irq.c
···
337
337
338
338
void __devinit register_bridge_irq(unsigned int irq)
339
339
{
340
-
set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
340
+
irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
341
341
}
342
342
343
343
int __devinit request_bridge_irq(struct bridge_controller *bc)
+1
-1
arch/mips/sgi-ip27/ip27-timer.c
+1
-1
arch/mips/sgi-ip27/ip27-timer.c
···
153
153
panic("Allocation of irq number for timer failed");
154
154
} while (xchg(&rt_timer_irq, irq));
155
155
156
-
set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
156
+
irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
157
157
setup_irq(irq, &hub_rt_irqaction);
158
158
}
159
159
+24
-16
arch/mips/sgi-ip32/ip32-irq.c
+24
-16
arch/mips/sgi-ip32/ip32-irq.c
···
451
451
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
452
452
switch (irq) {
453
453
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
454
-
set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
455
-
handle_level_irq, "level");
454
+
irq_set_chip_and_handler_name(irq,
455
+
&ip32_mace_interrupt,
456
+
handle_level_irq,
457
+
"level");
456
458
break;
457
459
458
460
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
459
-
set_irq_chip_and_handler_name(irq,
460
-
&ip32_macepci_interrupt, handle_level_irq,
461
-
"level");
461
+
irq_set_chip_and_handler_name(irq,
462
+
&ip32_macepci_interrupt,
463
+
handle_level_irq,
464
+
"level");
462
465
break;
463
466
464
467
case CRIME_CPUERR_IRQ:
465
468
case CRIME_MEMERR_IRQ:
466
-
set_irq_chip_and_handler_name(irq,
467
-
&crime_level_interrupt, handle_level_irq,
468
-
"level");
469
+
irq_set_chip_and_handler_name(irq,
470
+
&crime_level_interrupt,
471
+
handle_level_irq,
472
+
"level");
469
473
break;
470
474
471
475
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
472
476
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
473
477
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
474
478
case CRIME_VICE_IRQ:
475
-
set_irq_chip_and_handler_name(irq,
476
-
&crime_edge_interrupt, handle_edge_irq, "edge");
479
+
irq_set_chip_and_handler_name(irq,
480
+
&crime_edge_interrupt,
481
+
handle_edge_irq,
482
+
"edge");
477
483
break;
478
484
479
485
case MACEISA_PARALLEL_IRQ:
480
486
case MACEISA_SERIAL1_TDMAPR_IRQ:
481
487
case MACEISA_SERIAL2_TDMAPR_IRQ:
482
-
set_irq_chip_and_handler_name(irq,
483
-
&ip32_maceisa_edge_interrupt, handle_edge_irq,
484
-
"edge");
488
+
irq_set_chip_and_handler_name(irq,
489
+
&ip32_maceisa_edge_interrupt,
490
+
handle_edge_irq,
491
+
"edge");
485
492
break;
486
493
487
494
default:
488
-
set_irq_chip_and_handler_name(irq,
489
-
&ip32_maceisa_level_interrupt, handle_level_irq,
490
-
"level");
495
+
irq_set_chip_and_handler_name(irq,
496
+
&ip32_maceisa_level_interrupt,
497
+
handle_level_irq,
498
+
"level");
491
499
break;
492
500
}
493
501
}
+2
-1
arch/mips/sibyte/bcm1480/irq.c
+2
-1
arch/mips/sibyte/bcm1480/irq.c
+2
-1
arch/mips/sibyte/sb1250/irq.c
+2
-1
arch/mips/sibyte/sb1250/irq.c
+1
-1
arch/mips/sni/a20r.c
+1
-1
arch/mips/sni/a20r.c
···
209
209
int i;
210
210
211
211
for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
212
-
set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
212
+
irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
213
213
sni_hwint = a20r_hwint;
214
214
change_c0_status(ST0_IM, IE_IRQ0);
215
215
setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
+1
-1
arch/mips/sni/pcimt.c
+1
-1
arch/mips/sni/pcimt.c
···
296
296
mips_cpu_irq_init();
297
297
/* Actually we've got more interrupts to handle ... */
298
298
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
299
-
set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
299
+
irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
300
300
sni_hwint = sni_pcimt_hwint;
301
301
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
302
302
}
+2
-2
arch/mips/sni/pcit.c
+2
-2
arch/mips/sni/pcit.c
···
238
238
239
239
mips_cpu_irq_init();
240
240
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
241
-
set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
241
+
irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
242
242
*(volatile u32 *)SNI_PCIT_INT_REG = 0;
243
243
sni_hwint = sni_pcit_hwint;
244
244
change_c0_status(ST0_IM, IE_IRQ1);
···
251
251
252
252
mips_cpu_irq_init();
253
253
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
254
-
set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
254
+
irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
255
255
*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
256
256
sni_hwint = sni_pcit_hwint_cplus;
257
257
change_c0_status(ST0_IM, IE_IRQ0);
+2
-2
arch/mips/sni/rm200.c
+2
-2
arch/mips/sni/rm200.c
···
413
413
sni_rm200_init_8259A();
414
414
415
415
for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
416
-
set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip,
416
+
irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip,
417
417
handle_level_irq);
418
418
419
419
setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
···
477
477
mips_cpu_irq_init();
478
478
/* Actually we've got more interrupts to handle ... */
479
479
for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
480
-
set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
480
+
irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
481
481
sni_hwint = sni_rm200_hwint;
482
482
change_c0_status(ST0_IM, IE_IRQ0);
483
483
setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
+1
-1
arch/mips/txx9/generic/irq_tx4927.c
+1
-1
arch/mips/txx9/generic/irq_tx4927.c
···
35
35
36
36
mips_cpu_irq_init();
37
37
txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
38
-
set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
38
+
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
39
39
handle_simple_irq);
40
40
/* raise priority for errors, timers, SIO */
41
41
txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
+1
-1
arch/mips/txx9/generic/irq_tx4938.c
+1
-1
arch/mips/txx9/generic/irq_tx4938.c
···
23
23
24
24
mips_cpu_irq_init();
25
25
txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
26
-
set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
26
+
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
27
27
handle_simple_irq);
28
28
/* raise priority for errors, timers, SIO */
29
29
txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
+3
-3
arch/mips/txx9/generic/irq_tx4939.c
+3
-3
arch/mips/txx9/generic/irq_tx4939.c
···
176
176
for (i = 1; i < TX4939_NUM_IR; i++) {
177
177
tx4939irq[i].level = 4; /* middle level */
178
178
tx4939irq[i].mode = TXx9_IRCR_LOW;
179
-
set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
180
-
&tx4939_irq_chip, handle_level_irq);
179
+
irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip,
180
+
handle_level_irq);
181
181
}
182
182
183
183
/* mask all IRC interrupts */
···
193
193
__raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
194
194
__raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
195
195
196
-
set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
196
+
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
197
197
handle_simple_irq);
198
198
199
199
/* raise priority for errors, timers, sio */
+3
-2
arch/mips/txx9/jmr3927/irq.c
+3
-2
arch/mips/txx9/jmr3927/irq.c
···
120
120
121
121
tx3927_irq_init();
122
122
for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
123
-
set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
123
+
irq_set_chip_and_handler(i, &jmr3927_irq_ioc,
124
+
handle_level_irq);
124
125
125
126
/* setup IOC interrupt 1 (PCI, MODEM) */
126
-
set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
127
+
irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
127
128
}
+3
-3
arch/mips/txx9/rbtx4927/irq.c
+3
-3
arch/mips/txx9/rbtx4927/irq.c
···
164
164
165
165
for (i = RBTX4927_IRQ_IOC;
166
166
i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
167
-
set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
167
+
irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
168
168
handle_level_irq);
169
-
set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
169
+
irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
170
170
}
171
171
172
172
static int rbtx4927_irq_dispatch(int pending)
···
194
194
tx4927_irq_init();
195
195
toshiba_rbtx4927_irq_ioc_init();
196
196
/* Onboard 10M Ether: High Active */
197
-
set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
197
+
irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
198
198
}
+3
-3
arch/mips/txx9/rbtx4938/irq.c
+3
-3
arch/mips/txx9/rbtx4938/irq.c
···
132
132
133
133
for (i = RBTX4938_IRQ_IOC;
134
134
i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
135
-
set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
135
+
irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
136
136
handle_level_irq);
137
137
138
-
set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
138
+
irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
139
139
}
140
140
141
141
void __init rbtx4938_irq_setup(void)
···
153
153
tx4938_irq_init();
154
154
toshiba_rbtx4938_irq_ioc_init();
155
155
/* Onboard 10M Ether: High Active */
156
-
set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
156
+
irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
157
157
}
+2
-2
arch/mips/txx9/rbtx4939/irq.c
+2
-2
arch/mips/txx9/rbtx4939/irq.c
···
88
88
tx4939_irq_init();
89
89
for (i = RBTX4939_IRQ_IOC;
90
90
i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
91
-
set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
91
+
irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
92
92
handle_level_irq);
93
93
94
-
set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
94
+
irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
95
95
}
+2
-2
arch/mips/vr41xx/common/icu.c
+2
-2
arch/mips/vr41xx/common/icu.c
···
710
710
icu2_write(MGIUINTHREG, 0xffff);
711
711
712
712
for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
713
-
set_irq_chip_and_handler(i, &sysint1_irq_type,
713
+
irq_set_chip_and_handler(i, &sysint1_irq_type,
714
714
handle_level_irq);
715
715
716
716
for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
717
-
set_irq_chip_and_handler(i, &sysint2_irq_type,
717
+
irq_set_chip_and_handler(i, &sysint2_irq_type,
718
718
handle_level_irq);
719
719
720
720
cascade_irq(INT0_IRQ, icu_get_irq);
+1
-1
arch/mips/vr41xx/common/irq.c
+1
-1
arch/mips/vr41xx/common/irq.c
+1
arch/mn10300/Kconfig
+1
arch/mn10300/Kconfig
+18
-67
arch/mn10300/kernel/irq.c
+18
-67
arch/mn10300/kernel/irq.c
···
263
263
*/
264
264
void mn10300_set_lateack_irq_type(int irq)
265
265
{
266
-
set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level,
266
+
irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
267
267
handle_level_irq);
268
268
}
269
269
···
275
275
int irq;
276
276
277
277
for (irq = 0; irq < NR_IRQS; irq++)
278
-
if (get_irq_chip(irq) == &no_irq_chip)
278
+
if (irq_get_chip(irq) == &no_irq_chip)
279
279
/* due to the PIC latching interrupt requests, even
280
280
* when the IRQ is disabled, IRQ_PENDING is superfluous
281
281
* and we can use handle_level_irq() for edge-triggered
282
282
* interrupts */
283
-
set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge,
283
+
irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
284
284
handle_level_irq);
285
285
286
286
unit_init_IRQ();
···
335
335
/*
336
336
* Display interrupt management information through /proc/interrupts
337
337
*/
338
-
int show_interrupts(struct seq_file *p, void *v)
338
+
int arch_show_interrupts(struct seq_file *p, int prec)
339
339
{
340
-
int i = *(loff_t *) v, j, cpu;
341
-
struct irqaction *action;
342
-
unsigned long flags;
343
-
344
-
switch (i) {
345
-
/* display column title bar naming CPUs */
346
-
case 0:
347
-
seq_printf(p, " ");
348
-
for (j = 0; j < NR_CPUS; j++)
349
-
if (cpu_online(j))
350
-
seq_printf(p, "CPU%d ", j);
351
-
seq_putc(p, '\n');
352
-
break;
353
-
354
-
/* display information rows, one per active CPU */
355
-
case 1 ... NR_IRQS - 1:
356
-
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
357
-
358
-
action = irq_desc[i].action;
359
-
if (action) {
360
-
seq_printf(p, "%3d: ", i);
361
-
for_each_present_cpu(cpu)
362
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
363
-
364
-
if (i < NR_CPU_IRQS)
365
-
seq_printf(p, " %14s.%u",
366
-
irq_desc[i].irq_data.chip->name,
367
-
(GxICR(i) & GxICR_LEVEL) >>
368
-
GxICR_LEVEL_SHIFT);
369
-
else
370
-
seq_printf(p, " %14s",
371
-
irq_desc[i].irq_data.chip->name);
372
-
373
-
seq_printf(p, " %s", action->name);
374
-
375
-
for (action = action->next;
376
-
action;
377
-
action = action->next)
378
-
seq_printf(p, ", %s", action->name);
379
-
380
-
seq_putc(p, '\n');
381
-
}
382
-
383
-
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
384
-
break;
385
-
386
-
/* polish off with NMI and error counters */
387
-
case NR_IRQS:
388
340
#ifdef CONFIG_MN10300_WD_TIMER
389
-
seq_printf(p, "NMI: ");
390
-
for (j = 0; j < NR_CPUS; j++)
391
-
if (cpu_online(j))
392
-
seq_printf(p, "%10u ", nmi_count(j));
393
-
seq_putc(p, '\n');
341
+
int j;
342
+
343
+
seq_printf(p, "%*s: ", prec, "NMI");
344
+
for (j = 0; j < NR_CPUS; j++)
345
+
if (cpu_online(j))
346
+
seq_printf(p, "%10u ", nmi_count(j));
347
+
seq_putc(p, '\n');
394
348
#endif
395
349
396
-
seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
397
-
break;
398
-
}
399
-
350
+
seq_printf(p, "%*s: ", prec, "ERR");
351
+
seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
400
352
return 0;
401
353
}
402
354
403
355
#ifdef CONFIG_HOTPLUG_CPU
404
356
void migrate_irqs(void)
405
357
{
406
-
irq_desc_t *desc;
407
358
int irq;
408
359
unsigned int self, new;
409
360
unsigned long flags;
410
361
411
362
self = smp_processor_id();
412
363
for (irq = 0; irq < NR_IRQS; irq++) {
413
-
desc = irq_desc + irq;
364
+
struct irq_data *data = irq_get_irq_data(irq);
414
365
415
-
if (desc->status == IRQ_PER_CPU)
366
+
if (irqd_is_per_cpu(data))
416
367
continue;
417
368
418
-
if (cpu_isset(self, irq_desc[irq].affinity) &&
369
+
if (cpu_isset(self, data->affinity) &&
419
370
!cpus_intersects(irq_affinity[irq], cpu_online_map)) {
420
371
int cpu_id;
421
372
cpu_id = first_cpu(cpu_online_map);
422
-
cpu_set(cpu_id, irq_desc[irq].affinity);
373
+
cpu_set(cpu_id, data->affinity);
423
374
}
424
375
/* We need to operate irq_affinity_online atomically. */
425
376
arch_local_cli_save(flags);
···
381
430
GxICR(irq) = x & GxICR_LEVEL;
382
431
tmp = GxICR(irq);
383
432
384
-
new = any_online_cpu(irq_desc[irq].affinity);
433
+
new = any_online_cpu(data->affinity);
385
434
irq_affinity_online[irq] = new;
386
435
387
436
CROSS_GxICR(irq, new) =
+1
-1
arch/mn10300/kernel/mn10300-serial.c
+1
-1
arch/mn10300/kernel/mn10300-serial.c
···
933
933
NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
934
934
set_intr_level(port->tx_irq,
935
935
NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
936
-
set_irq_chip(port->tm_irq, &mn10300_serial_pic);
936
+
irq_set_chip(port->tm_irq, &mn10300_serial_pic);
937
937
938
938
if (request_irq(port->rx_irq, mn10300_serial_interrupt,
939
939
IRQF_DISABLED, port->rx_name, port) < 0)
+6
-6
arch/mn10300/kernel/smp.c
+6
-6
arch/mn10300/kernel/smp.c
···
156
156
u16 tmp16;
157
157
158
158
/* set up the reschedule IPI */
159
-
set_irq_chip_and_handler(RESCHEDULE_IPI,
160
-
&mn10300_ipi_type, handle_percpu_irq);
159
+
irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type,
160
+
handle_percpu_irq);
161
161
setup_irq(RESCHEDULE_IPI, &reschedule_ipi);
162
162
set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV);
163
163
mn10300_ipi_enable(RESCHEDULE_IPI);
164
164
165
165
/* set up the call function IPI */
166
-
set_irq_chip_and_handler(CALL_FUNC_SINGLE_IPI,
167
-
&mn10300_ipi_type, handle_percpu_irq);
166
+
irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type,
167
+
handle_percpu_irq);
168
168
setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi);
169
169
set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV);
170
170
mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI);
···
172
172
/* set up the local timer IPI */
173
173
#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \
174
174
defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
175
-
set_irq_chip_and_handler(LOCAL_TIMER_IPI,
176
-
&mn10300_ipi_type, handle_percpu_irq);
175
+
irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type,
176
+
handle_percpu_irq);
177
177
setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi);
178
178
set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV);
179
179
mn10300_ipi_enable(LOCAL_TIMER_IPI);
+2
-1
arch/mn10300/unit-asb2364/irq-fpga.c
+2
-1
arch/mn10300/unit-asb2364/irq-fpga.c
···
100
100
SyncExBus();
101
101
102
102
for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++)
103
-
set_irq_chip_and_handler(irq, &asb2364_fpga_pic, handle_level_irq);
103
+
irq_set_chip_and_handler(irq, &asb2364_fpga_pic,
104
+
handle_level_irq);
104
105
105
106
/* the FPGA drives the XIRQ1 input on the CPU PIC */
106
107
setup_irq(XIRQ1, &fpga_irq[0]);
+14
-18
arch/parisc/kernel/irq.c
+14
-18
arch/parisc/kernel/irq.c
···
113
113
int cpu_dest;
114
114
115
115
/* timer and ipi have to always be received on all CPUs */
116
-
if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) {
117
-
/* Bad linux design decision. The mask has already
118
-
* been set; we must reset it. Will fix - tglx
119
-
*/
120
-
cpumask_setall(d->affinity);
116
+
if (irqd_is_per_cpu(d))
121
117
return -EINVAL;
122
-
}
123
118
124
119
/* whatever mask they set, we just allow one CPU */
125
120
cpu_dest = first_cpu(*dest);
···
169
174
}
170
175
171
176
if (i < NR_IRQS) {
177
+
struct irq_desc *desc = irq_to_desc(i);
172
178
struct irqaction *action;
173
179
174
-
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
175
-
action = irq_desc[i].action;
180
+
raw_spin_lock_irqsave(&desc->lock, flags);
181
+
action = desc->action;
176
182
if (!action)
177
183
goto skip;
178
184
seq_printf(p, "%3d: ", i);
···
184
188
seq_printf(p, "%10u ", kstat_irqs(i));
185
189
#endif
186
190
187
-
seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
191
+
seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
188
192
#ifndef PARISC_IRQ_CR16_COUNTS
189
193
seq_printf(p, " %s", action->name);
190
194
···
216
220
217
221
seq_putc(p, '\n');
218
222
skip:
219
-
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
223
+
raw_spin_unlock_irqrestore(&desc->lock, flags);
220
224
}
221
225
222
226
return 0;
···
234
238
235
239
int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
236
240
{
237
-
if (irq_desc[irq].action)
241
+
if (irq_has_action(irq))
238
242
return -EBUSY;
239
-
if (get_irq_chip(irq) != &cpu_interrupt_type)
243
+
if (irq_get_chip(irq) != &cpu_interrupt_type)
240
244
return -EBUSY;
241
245
242
246
/* for iosapic interrupts */
243
247
if (type) {
244
-
set_irq_chip_and_handler(irq, type, handle_percpu_irq);
245
-
set_irq_chip_data(irq, data);
248
+
irq_set_chip_and_handler(irq, type, handle_percpu_irq);
249
+
irq_set_chip_data(irq, data);
246
250
__cpu_unmask_irq(irq);
247
251
}
248
252
return 0;
···
353
357
#ifdef CONFIG_SMP
354
358
desc = irq_to_desc(irq);
355
359
cpumask_copy(&dest, desc->irq_data.affinity);
356
-
if (CHECK_IRQ_PER_CPU(desc->status) &&
360
+
if (irqd_is_per_cpu(&desc->irq_data) &&
357
361
!cpu_isset(smp_processor_id(), dest)) {
358
362
int cpu = first_cpu(dest);
359
363
···
394
398
{
395
399
int i;
396
400
for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
397
-
set_irq_chip_and_handler(i, &cpu_interrupt_type,
401
+
irq_set_chip_and_handler(i, &cpu_interrupt_type,
398
402
handle_percpu_irq);
399
403
}
400
404
401
-
set_irq_handler(TIMER_IRQ, handle_percpu_irq);
405
+
irq_set_handler(TIMER_IRQ, handle_percpu_irq);
402
406
setup_irq(TIMER_IRQ, &timer_action);
403
407
#ifdef CONFIG_SMP
404
-
set_irq_handler(IPI_IRQ, handle_percpu_irq);
408
+
irq_set_handler(IPI_IRQ, handle_percpu_irq);
405
409
setup_irq(IPI_IRQ, &ipi_action);
406
410
#endif
407
411
}
+2
arch/powerpc/Kconfig
+2
arch/powerpc/Kconfig
+12
-69
arch/powerpc/kernel/irq.c
+12
-69
arch/powerpc/kernel/irq.c
···
195
195
EXPORT_SYMBOL(arch_local_irq_restore);
196
196
#endif /* CONFIG_PPC64 */
197
197
198
-
static int show_other_interrupts(struct seq_file *p, int prec)
198
+
int arch_show_interrupts(struct seq_file *p, int prec)
199
199
{
200
200
int j;
201
201
···
231
231
return 0;
232
232
}
233
233
234
-
int show_interrupts(struct seq_file *p, void *v)
235
-
{
236
-
unsigned long flags, any_count = 0;
237
-
int i = *(loff_t *) v, j, prec;
238
-
struct irqaction *action;
239
-
struct irq_desc *desc;
240
-
struct irq_chip *chip;
241
-
242
-
if (i > nr_irqs)
243
-
return 0;
244
-
245
-
for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
246
-
j *= 10;
247
-
248
-
if (i == nr_irqs)
249
-
return show_other_interrupts(p, prec);
250
-
251
-
/* print header */
252
-
if (i == 0) {
253
-
seq_printf(p, "%*s", prec + 8, "");
254
-
for_each_online_cpu(j)
255
-
seq_printf(p, "CPU%-8d", j);
256
-
seq_putc(p, '\n');
257
-
}
258
-
259
-
desc = irq_to_desc(i);
260
-
if (!desc)
261
-
return 0;
262
-
263
-
raw_spin_lock_irqsave(&desc->lock, flags);
264
-
for_each_online_cpu(j)
265
-
any_count |= kstat_irqs_cpu(i, j);
266
-
action = desc->action;
267
-
if (!action && !any_count)
268
-
goto out;
269
-
270
-
seq_printf(p, "%*d: ", prec, i);
271
-
for_each_online_cpu(j)
272
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
273
-
274
-
chip = get_irq_desc_chip(desc);
275
-
if (chip)
276
-
seq_printf(p, " %-16s", chip->name);
277
-
else
278
-
seq_printf(p, " %-16s", "None");
279
-
seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge");
280
-
281
-
if (action) {
282
-
seq_printf(p, " %s", action->name);
283
-
while ((action = action->next) != NULL)
284
-
seq_printf(p, ", %s", action->name);
285
-
}
286
-
287
-
seq_putc(p, '\n');
288
-
out:
289
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
290
-
return 0;
291
-
}
292
-
293
234
/*
294
235
* /proc/stat helpers
295
236
*/
···
256
315
alloc_cpumask_var(&mask, GFP_KERNEL);
257
316
258
317
for_each_irq(irq) {
318
+
struct irq_data *data;
259
319
struct irq_chip *chip;
260
320
261
321
desc = irq_to_desc(irq);
262
322
if (!desc)
263
323
continue;
264
324
265
-
if (desc->status & IRQ_PER_CPU)
325
+
data = irq_desc_get_irq_data(desc);
326
+
if (irqd_is_per_cpu(data))
266
327
continue;
267
328
268
-
chip = get_irq_desc_chip(desc);
329
+
chip = irq_data_get_irq_chip(data);
269
330
270
-
cpumask_and(mask, desc->irq_data.affinity, map);
331
+
cpumask_and(mask, data->affinity, map);
271
332
if (cpumask_any(mask) >= nr_cpu_ids) {
272
333
printk("Breaking affinity for irq %i\n", irq);
273
334
cpumask_copy(mask, map);
274
335
}
275
336
if (chip->irq_set_affinity)
276
-
chip->irq_set_affinity(&desc->irq_data, mask, true);
337
+
chip->irq_set_affinity(data, mask, true);
277
338
else if (desc->action && !(warned++))
278
339
printk("Cannot set affinity for irq %i\n", irq);
279
340
}
···
561
618
smp_wmb();
562
619
563
620
/* Clear norequest flags */
564
-
irq_to_desc(i)->status &= ~IRQ_NOREQUEST;
621
+
irq_clear_status_flags(i, IRQ_NOREQUEST);
565
622
566
623
/* Legacy flags are left to default at this point,
567
624
* one can then use irq_create_mapping() to
···
770
827
771
828
/* Set type if specified and different than the current one */
772
829
if (type != IRQ_TYPE_NONE &&
773
-
type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK))
774
-
set_irq_type(virq, type);
830
+
type != (irqd_get_trigger_type(irq_get_irq_data(virq))))
831
+
irq_set_irq_type(virq, type);
775
832
return virq;
776
833
}
777
834
EXPORT_SYMBOL_GPL(irq_create_of_mapping);
···
794
851
return;
795
852
796
853
/* remove chip and handler */
797
-
set_irq_chip_and_handler(virq, NULL, NULL);
854
+
irq_set_chip_and_handler(virq, NULL, NULL);
798
855
799
856
/* Make sure it's completed */
800
857
synchronize_irq(virq);
···
1099
1156
seq_printf(m, "%5d ", i);
1100
1157
seq_printf(m, "0x%05lx ", virq_to_hw(i));
1101
1158
1102
-
chip = get_irq_desc_chip(desc);
1159
+
chip = irq_desc_get_chip(desc);
1103
1160
if (chip && chip->name)
1104
1161
p = chip->name;
1105
1162
else
+3
-3
arch/powerpc/kernel/machine_kexec.c
+3
-3
arch/powerpc/kernel/machine_kexec.c
···
31
31
if (!desc)
32
32
continue;
33
33
34
-
chip = get_irq_desc_chip(desc);
34
+
chip = irq_desc_get_chip(desc);
35
35
if (!chip)
36
36
continue;
37
37
38
-
if (chip->irq_eoi && desc->status & IRQ_INPROGRESS)
38
+
if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data))
39
39
chip->irq_eoi(&desc->irq_data);
40
40
41
41
if (chip->irq_mask)
42
42
chip->irq_mask(&desc->irq_data);
43
43
44
-
if (chip->irq_disable && !(desc->status & IRQ_DISABLED))
44
+
if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
45
45
chip->irq_disable(&desc->irq_data);
46
46
}
47
47
}
+1
-1
arch/powerpc/kernel/pci-common.c
+1
-1
arch/powerpc/kernel/pci-common.c
···
261
261
262
262
virq = irq_create_mapping(NULL, line);
263
263
if (virq != NO_IRQ)
264
-
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
264
+
irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
265
265
} else {
266
266
pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
267
267
oirq.size, oirq.specifier[0], oirq.specifier[1],
+3
-3
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
+3
-3
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
···
132
132
cpld_pic_host_map(struct irq_host *h, unsigned int virq,
133
133
irq_hw_number_t hw)
134
134
{
135
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
136
-
set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
135
+
irq_set_status_flags(virq, IRQ_LEVEL);
136
+
irq_set_chip_and_handler(virq, &cpld_pic, handle_level_irq);
137
137
return 0;
138
138
}
139
139
···
198
198
goto end;
199
199
}
200
200
201
-
set_irq_chained_handler(cascade_irq, cpld_pic_cascade);
201
+
irq_set_chained_handler(cascade_irq, cpld_pic_cascade);
202
202
end:
203
203
of_node_put(np);
204
204
}
+7
-12
arch/powerpc/platforms/52xx/media5200.c
+7
-12
arch/powerpc/platforms/52xx/media5200.c
···
82
82
83
83
void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
84
84
{
85
-
struct irq_chip *chip = get_irq_desc_chip(desc);
85
+
struct irq_chip *chip = irq_desc_get_chip(desc);
86
86
int sub_virq, val;
87
87
u32 status, enable;
88
88
···
107
107
/* Processing done; can reenable the cascade now */
108
108
raw_spin_lock(&desc->lock);
109
109
chip->irq_ack(&desc->irq_data);
110
-
if (!(desc->status & IRQ_DISABLED))
110
+
if (!irqd_irq_disabled(&desc->irq_data))
111
111
chip->irq_unmask(&desc->irq_data);
112
112
raw_spin_unlock(&desc->lock);
113
113
}
···
115
115
static int media5200_irq_map(struct irq_host *h, unsigned int virq,
116
116
irq_hw_number_t hw)
117
117
{
118
-
struct irq_desc *desc = irq_to_desc(virq);
119
-
120
118
pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
121
-
set_irq_chip_data(virq, &media5200_irq);
122
-
set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
123
-
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
124
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
125
-
desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
126
-
119
+
irq_set_chip_data(virq, &media5200_irq);
120
+
irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
121
+
irq_set_status_flags(virq, IRQ_LEVEL);
127
122
return 0;
128
123
}
129
124
···
182
187
183
188
media5200_irq.irqhost->host_data = &media5200_irq;
184
189
185
-
set_irq_data(cascade_virq, &media5200_irq);
186
-
set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
190
+
irq_set_handler_data(cascade_virq, &media5200_irq);
191
+
irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
187
192
188
193
return;
189
194
+5
-5
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+5
-5
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
···
192
192
193
193
void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
194
194
{
195
-
struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
195
+
struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq);
196
196
int sub_virq;
197
197
u32 status;
198
198
···
209
209
struct mpc52xx_gpt_priv *gpt = h->host_data;
210
210
211
211
dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
212
-
set_irq_chip_data(virq, gpt);
213
-
set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
212
+
irq_set_chip_data(virq, gpt);
213
+
irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
214
214
215
215
return 0;
216
216
}
···
259
259
}
260
260
261
261
gpt->irqhost->host_data = gpt;
262
-
set_irq_data(cascade_virq, gpt);
263
-
set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
262
+
irq_set_handler_data(cascade_virq, gpt);
263
+
irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
264
264
265
265
/* If the GPT is currently disabled, then change it to be in Input
266
266
* Capture mode. If the mode is non-zero, then the pin could be
+3
-3
arch/powerpc/platforms/52xx/mpc52xx_pic.c
+3
-3
arch/powerpc/platforms/52xx/mpc52xx_pic.c
···
214
214
ctrl_reg |= (type << (22 - (l2irq * 2)));
215
215
out_be32(&intr->ctrl, ctrl_reg);
216
216
217
-
__set_irq_handler_unlocked(d->irq, handler);
217
+
__irq_set_handler_locked(d->irq, handler);
218
218
219
219
return 0;
220
220
}
···
414
414
else
415
415
hndlr = handle_level_irq;
416
416
417
-
set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
417
+
irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
418
418
pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
419
419
__func__, l2irq, virq, (int)irq, type);
420
420
return 0;
···
431
431
return -EINVAL;
432
432
}
433
433
434
-
set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
434
+
irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
435
435
pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
436
436
437
437
return 0;
+8
-8
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+8
-8
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
···
81
81
82
82
static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
83
83
{
84
-
struct pq2ads_pci_pic *priv = get_irq_desc_data(desc);
84
+
struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
85
85
u32 stat, mask, pend;
86
86
int bit;
87
87
···
106
106
static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
107
107
irq_hw_number_t hw)
108
108
{
109
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
110
-
set_irq_chip_data(virq, h->host_data);
111
-
set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
109
+
irq_set_status_flags(virq, IRQ_LEVEL);
110
+
irq_set_chip_data(virq, h->host_data);
111
+
irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
112
112
return 0;
113
113
}
114
114
115
115
static void pci_host_unmap(struct irq_host *h, unsigned int virq)
116
116
{
117
117
/* remove chip and handler */
118
-
set_irq_chip_data(virq, NULL);
119
-
set_irq_chip(virq, NULL);
118
+
irq_set_chip_data(virq, NULL);
119
+
irq_set_chip(virq, NULL);
120
120
}
121
121
122
122
static struct irq_host_ops pci_pic_host_ops = {
···
175
175
176
176
priv->host = host;
177
177
host->host_data = priv;
178
-
set_irq_data(irq, priv);
179
-
set_irq_chained_handler(irq, pq2ads_pci_irq_demux);
178
+
irq_set_handler_data(irq, priv);
179
+
irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
180
180
181
181
of_node_put(np);
182
182
return 0;
+2
-2
arch/powerpc/platforms/85xx/ksi8560.c
+2
-2
arch/powerpc/platforms/85xx/ksi8560.c
···
56
56
57
57
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
58
58
{
59
-
struct irq_chip *chip = get_irq_desc_chip(desc);
59
+
struct irq_chip *chip = irq_desc_get_chip(desc);
60
60
int cascade_irq;
61
61
62
62
while ((cascade_irq = cpm2_get_irq()) >= 0)
···
106
106
107
107
cpm2_pic_init(np);
108
108
of_node_put(np);
109
-
set_irq_chained_handler(irq, cpm2_cascade);
109
+
irq_set_chained_handler(irq, cpm2_cascade);
110
110
#endif
111
111
}
112
112
+2
-2
arch/powerpc/platforms/85xx/mpc85xx_ads.c
+2
-2
arch/powerpc/platforms/85xx/mpc85xx_ads.c
···
50
50
51
51
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
52
52
{
53
-
struct irq_chip *chip = get_irq_desc_chip(desc);
53
+
struct irq_chip *chip = irq_desc_get_chip(desc);
54
54
int cascade_irq;
55
55
56
56
while ((cascade_irq = cpm2_get_irq()) >= 0)
···
101
101
102
102
cpm2_pic_init(np);
103
103
of_node_put(np);
104
-
set_irq_chained_handler(irq, cpm2_cascade);
104
+
irq_set_chained_handler(irq, cpm2_cascade);
105
105
#endif
106
106
}
107
107
+1
-1
arch/powerpc/platforms/85xx/mpc85xx_cds.c
+1
-1
arch/powerpc/platforms/85xx/mpc85xx_cds.c
+2
-2
arch/powerpc/platforms/85xx/mpc85xx_ds.c
+2
-2
arch/powerpc/platforms/85xx/mpc85xx_ds.c
···
47
47
#ifdef CONFIG_PPC_I8259
48
48
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
49
49
{
50
-
struct irq_chip *chip = get_irq_desc_chip(desc);
50
+
struct irq_chip *chip = irq_desc_get_chip(desc);
51
51
unsigned int cascade_irq = i8259_irq();
52
52
53
53
if (cascade_irq != NO_IRQ) {
···
122
122
i8259_init(cascade_node, 0);
123
123
of_node_put(cascade_node);
124
124
125
-
set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
125
+
irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
126
126
#endif /* CONFIG_PPC_I8259 */
127
127
}
128
128
+2
-2
arch/powerpc/platforms/85xx/sbc8560.c
+2
-2
arch/powerpc/platforms/85xx/sbc8560.c
···
41
41
42
42
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
43
43
{
44
-
struct irq_chip *chip = get_irq_desc_chip(desc);
44
+
struct irq_chip *chip = irq_desc_get_chip(desc);
45
45
int cascade_irq;
46
46
47
47
while ((cascade_irq = cpm2_get_irq()) >= 0)
···
92
92
93
93
cpm2_pic_init(np);
94
94
of_node_put(np);
95
-
set_irq_chained_handler(irq, cpm2_cascade);
95
+
irq_set_chained_handler(irq, cpm2_cascade);
96
96
#endif
97
97
}
98
98
+6
-6
arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+6
-6
arch/powerpc/platforms/85xx/socrates_fpga_pic.c
···
93
93
94
94
void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
95
95
{
96
-
struct irq_chip *chip = get_irq_desc_chip(desc);
96
+
struct irq_chip *chip = irq_desc_get_chip(desc);
97
97
unsigned int cascade_irq;
98
98
99
99
/*
···
245
245
irq_hw_number_t hwirq)
246
246
{
247
247
/* All interrupts are LEVEL sensitive */
248
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
249
-
set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip,
250
-
handle_fasteoi_irq);
248
+
irq_set_status_flags(virq, IRQ_LEVEL);
249
+
irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip,
250
+
handle_fasteoi_irq);
251
251
252
252
return 0;
253
253
}
···
308
308
pr_warning("FPGA PIC: can't get irq%d.\n", i);
309
309
continue;
310
310
}
311
-
set_irq_chained_handler(socrates_fpga_irqs[i],
312
-
socrates_fpga_pic_cascade);
311
+
irq_set_chained_handler(socrates_fpga_irqs[i],
312
+
socrates_fpga_pic_cascade);
313
313
}
314
314
315
315
socrates_fpga_pic_iobase = of_iomap(pic, 0);
+2
-2
arch/powerpc/platforms/85xx/stx_gp3.c
+2
-2
arch/powerpc/platforms/85xx/stx_gp3.c
···
46
46
47
47
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
48
48
{
49
-
struct irq_chip *chip = get_irq_desc_chip(desc);
49
+
struct irq_chip *chip = irq_desc_get_chip(desc);
50
50
int cascade_irq;
51
51
52
52
while ((cascade_irq = cpm2_get_irq()) >= 0)
···
102
102
103
103
cpm2_pic_init(np);
104
104
of_node_put(np);
105
-
set_irq_chained_handler(irq, cpm2_cascade);
105
+
irq_set_chained_handler(irq, cpm2_cascade);
106
106
#endif
107
107
}
108
108
+2
-2
arch/powerpc/platforms/85xx/tqm85xx.c
+2
-2
arch/powerpc/platforms/85xx/tqm85xx.c
···
44
44
45
45
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
46
46
{
47
-
struct irq_chip *chip = get_irq_desc_chip(desc);
47
+
struct irq_chip *chip = irq_desc_get_chip(desc);
48
48
int cascade_irq;
49
49
50
50
while ((cascade_irq = cpm2_get_irq()) >= 0)
···
100
100
101
101
cpm2_pic_init(np);
102
102
of_node_put(np);
103
-
set_irq_chained_handler(irq, cpm2_cascade);
103
+
irq_set_chained_handler(irq, cpm2_cascade);
104
104
#endif
105
105
}
106
106
+4
-4
arch/powerpc/platforms/86xx/gef_pic.c
+4
-4
arch/powerpc/platforms/86xx/gef_pic.c
···
95
95
96
96
void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
97
97
{
98
-
struct irq_chip *chip = get_irq_desc_chip(desc);
98
+
struct irq_chip *chip = irq_desc_get_chip(desc);
99
99
unsigned int cascade_irq;
100
100
101
101
/*
···
163
163
irq_hw_number_t hwirq)
164
164
{
165
165
/* All interrupts are LEVEL sensitive */
166
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
167
-
set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
166
+
irq_set_status_flags(virq, IRQ_LEVEL);
167
+
irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
168
168
169
169
return 0;
170
170
}
···
225
225
return;
226
226
227
227
/* Chain with parent controller */
228
-
set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
228
+
irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
229
229
}
230
230
231
231
/*
+2
-2
arch/powerpc/platforms/86xx/pic.c
+2
-2
arch/powerpc/platforms/86xx/pic.c
···
19
19
#ifdef CONFIG_PPC_I8259
20
20
static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
21
21
{
22
-
struct irq_chip *chip = get_irq_desc_chip(desc);
22
+
struct irq_chip *chip = irq_desc_get_chip(desc);
23
23
unsigned int cascade_irq = i8259_irq();
24
24
25
25
if (cascade_irq != NO_IRQ)
···
77
77
i8259_init(cascade_node, 0);
78
78
of_node_put(cascade_node);
79
79
80
-
set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
80
+
irq_set_chained_handler(cascade_irq, mpc86xx_8259_cascade);
81
81
#endif
82
82
}
+3
-3
arch/powerpc/platforms/8xx/m8xx_setup.c
+3
-3
arch/powerpc/platforms/8xx/m8xx_setup.c
···
226
226
227
227
generic_handle_irq(cascade_irq);
228
228
229
-
chip = get_irq_desc_chip(cdesc);
229
+
chip = irq_desc_get_chip(cdesc);
230
230
chip->irq_eoi(&cdesc->irq_data);
231
231
}
232
232
233
-
chip = get_irq_desc_chip(desc);
233
+
chip = irq_desc_get_chip(desc);
234
234
chip->irq_eoi(&desc->irq_data);
235
235
}
236
236
···
251
251
252
252
irq = cpm_pic_init();
253
253
if (irq != NO_IRQ)
254
-
set_irq_chained_handler(irq, cpm_cascade);
254
+
irq_set_chained_handler(irq, cpm_cascade);
255
255
}
+7
-7
arch/powerpc/platforms/cell/axon_msi.c
+7
-7
arch/powerpc/platforms/cell/axon_msi.c
···
93
93
94
94
static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
95
95
{
96
-
struct irq_chip *chip = get_irq_desc_chip(desc);
97
-
struct axon_msic *msic = get_irq_data(irq);
96
+
struct irq_chip *chip = irq_desc_get_chip(desc);
97
+
struct axon_msic *msic = irq_get_handler_data(irq);
98
98
u32 write_offset, msi;
99
99
int idx;
100
100
int retry = 0;
···
287
287
}
288
288
dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
289
289
290
-
set_irq_msi(virq, entry);
290
+
irq_set_msi_desc(virq, entry);
291
291
msg.data = virq;
292
292
write_msi_msg(virq, &msg);
293
293
}
···
305
305
if (entry->irq == NO_IRQ)
306
306
continue;
307
307
308
-
set_irq_msi(entry->irq, NULL);
308
+
irq_set_msi_desc(entry->irq, NULL);
309
309
irq_dispose_mapping(entry->irq);
310
310
}
311
311
}
···
320
320
static int msic_host_map(struct irq_host *h, unsigned int virq,
321
321
irq_hw_number_t hw)
322
322
{
323
-
set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
323
+
irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
324
324
325
325
return 0;
326
326
}
···
400
400
401
401
msic->irq_host->host_data = msic;
402
402
403
-
set_irq_data(virq, msic);
404
-
set_irq_chained_handler(virq, axon_msi_cascade);
403
+
irq_set_handler_data(virq, msic);
404
+
irq_set_chained_handler(virq, axon_msi_cascade);
405
405
pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
406
406
407
407
/* Enable the MSIC hardware */
+2
-3
arch/powerpc/platforms/cell/beat_interrupt.c
+2
-3
arch/powerpc/platforms/cell/beat_interrupt.c
···
136
136
static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
137
137
irq_hw_number_t hw)
138
138
{
139
-
struct irq_desc *desc = irq_to_desc(virq);
140
139
int64_t err;
141
140
142
141
err = beat_construct_and_connect_irq_plug(virq, hw);
143
142
if (err < 0)
144
143
return -EIO;
145
144
146
-
desc->status |= IRQ_LEVEL;
147
-
set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
145
+
irq_set_status_flags(virq, IRQ_LEVEL);
146
+
irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
148
147
return 0;
149
148
}
150
149
+7
-7
arch/powerpc/platforms/cell/interrupt.c
+7
-7
arch/powerpc/platforms/cell/interrupt.c
···
101
101
102
102
static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
103
103
{
104
-
struct irq_chip *chip = get_irq_desc_chip(desc);
104
+
struct irq_chip *chip = irq_desc_get_chip(desc);
105
105
struct cbe_iic_regs __iomem *node_iic =
106
-
(void __iomem *)get_irq_desc_data(desc);
106
+
(void __iomem *)irq_desc_get_handler_data(desc);
107
107
unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
108
108
unsigned long bits, ack;
109
109
int cascade;
···
240
240
{
241
241
switch (hw & IIC_IRQ_TYPE_MASK) {
242
242
case IIC_IRQ_TYPE_IPI:
243
-
set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
243
+
irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
244
244
break;
245
245
case IIC_IRQ_TYPE_IOEXC:
246
-
set_irq_chip_and_handler(virq, &iic_ioexc_chip,
246
+
irq_set_chip_and_handler(virq, &iic_ioexc_chip,
247
247
handle_iic_irq);
248
248
break;
249
249
default:
250
-
set_irq_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
250
+
irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
251
251
}
252
252
return 0;
253
253
}
···
364
364
* irq_data is a generic pointer that gets passed back
365
365
* to us later, so the forced cast is fine.
366
366
*/
367
-
set_irq_data(cascade, (void __force *)node_iic);
368
-
set_irq_chained_handler(cascade , iic_ioexc_cascade);
367
+
irq_set_handler_data(cascade, (void __force *)node_iic);
368
+
irq_set_chained_handler(cascade, iic_ioexc_cascade);
369
369
out_be64(&node_iic->iic_ir,
370
370
(1 << 12) /* priority */ |
371
371
(node << 4) /* dest node */ |
+4
-4
arch/powerpc/platforms/cell/setup.c
+4
-4
arch/powerpc/platforms/cell/setup.c
···
187
187
188
188
static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
189
189
{
190
-
struct irq_chip *chip = get_irq_desc_chip(desc);
191
-
struct mpic *mpic = get_irq_desc_data(desc);
190
+
struct irq_chip *chip = irq_desc_get_chip(desc);
191
+
struct mpic *mpic = irq_desc_get_handler_data(desc);
192
192
unsigned int virq;
193
193
194
194
virq = mpic_get_one_irq(mpic);
···
223
223
224
224
printk(KERN_INFO "%s : hooking up to IRQ %d\n",
225
225
dn->full_name, virq);
226
-
set_irq_data(virq, mpic);
227
-
set_irq_chained_handler(virq, cell_mpic_cascade);
226
+
irq_set_handler_data(virq, mpic);
227
+
irq_set_chained_handler(virq, cell_mpic_cascade);
228
228
}
229
229
}
230
230
+7
-14
arch/powerpc/platforms/cell/spider-pic.c
+7
-14
arch/powerpc/platforms/cell/spider-pic.c
···
102
102
103
103
/* Reset edge detection logic if necessary
104
104
*/
105
-
if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
105
+
if (irqd_is_level_type(d))
106
106
return;
107
107
108
108
/* Only interrupts 47 to 50 can be set to edge */
···
119
119
struct spider_pic *pic = spider_virq_to_pic(d->irq);
120
120
unsigned int hw = irq_map[d->irq].hwirq;
121
121
void __iomem *cfg = spider_get_irq_config(pic, hw);
122
-
struct irq_desc *desc = irq_to_desc(d->irq);
123
122
u32 old_mask;
124
123
u32 ic;
125
124
···
146
147
return -EINVAL;
147
148
}
148
149
149
-
/* Update irq_desc */
150
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
151
-
desc->status |= type & IRQ_TYPE_SENSE_MASK;
152
-
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
153
-
desc->status |= IRQ_LEVEL;
154
-
155
150
/* Configure the source. One gross hack that was there before and
156
151
* that I've kept around is the priority to the BE which I set to
157
152
* be the same as the interrupt source number. I don't know wether
···
171
178
static int spider_host_map(struct irq_host *h, unsigned int virq,
172
179
irq_hw_number_t hw)
173
180
{
174
-
set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq);
181
+
irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq);
175
182
176
183
/* Set default irq type */
177
-
set_irq_type(virq, IRQ_TYPE_NONE);
184
+
irq_set_irq_type(virq, IRQ_TYPE_NONE);
178
185
179
186
return 0;
180
187
}
···
200
207
201
208
static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc)
202
209
{
203
-
struct irq_chip *chip = get_irq_desc_chip(desc);
204
-
struct spider_pic *pic = get_irq_desc_data(desc);
210
+
struct irq_chip *chip = irq_desc_get_chip(desc);
211
+
struct spider_pic *pic = irq_desc_get_handler_data(desc);
205
212
unsigned int cs, virq;
206
213
207
214
cs = in_be32(pic->regs + TIR_CS) >> 24;
···
321
328
virq = spider_find_cascade_and_node(pic);
322
329
if (virq == NO_IRQ)
323
330
return;
324
-
set_irq_data(virq, pic);
325
-
set_irq_chained_handler(virq, spider_irq_cascade);
331
+
irq_set_handler_data(virq, pic);
332
+
irq_set_chained_handler(virq, spider_irq_cascade);
326
333
327
334
printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n",
328
335
pic->node_id, addr, of_node->full_name);
+2
-2
arch/powerpc/platforms/chrp/setup.c
+2
-2
arch/powerpc/platforms/chrp/setup.c
···
365
365
366
366
static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
367
367
{
368
-
struct irq_chip *chip = get_irq_desc_chip(desc);
368
+
struct irq_chip *chip = irq_desc_get_chip(desc);
369
369
unsigned int cascade_irq = i8259_irq();
370
370
371
371
if (cascade_irq != NO_IRQ)
···
517
517
if (cascade_irq == NO_IRQ)
518
518
printk(KERN_ERR "i8259: failed to map cascade irq\n");
519
519
else
520
-
set_irq_chained_handler(cascade_irq,
520
+
irq_set_chained_handler(cascade_irq,
521
521
chrp_8259_cascade);
522
522
}
523
523
}
+5
-5
arch/powerpc/platforms/embedded6xx/flipper-pic.c
+5
-5
arch/powerpc/platforms/embedded6xx/flipper-pic.c
···
101
101
static int flipper_pic_map(struct irq_host *h, unsigned int virq,
102
102
irq_hw_number_t hwirq)
103
103
{
104
-
set_irq_chip_data(virq, h->host_data);
105
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
106
-
set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
104
+
irq_set_chip_data(virq, h->host_data);
105
+
irq_set_status_flags(virq, IRQ_LEVEL);
106
+
irq_set_chip_and_handler(virq, &flipper_pic, handle_level_irq);
107
107
return 0;
108
108
}
109
109
110
110
static void flipper_pic_unmap(struct irq_host *h, unsigned int irq)
111
111
{
112
-
set_irq_chip_data(irq, NULL);
113
-
set_irq_chip(irq, NULL);
112
+
irq_set_chip_data(irq, NULL);
113
+
irq_set_chip(irq, NULL);
114
114
}
115
115
116
116
static int flipper_pic_match(struct irq_host *h, struct device_node *np)
+10
-10
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+10
-10
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
···
94
94
static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
95
95
irq_hw_number_t hwirq)
96
96
{
97
-
set_irq_chip_data(virq, h->host_data);
98
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
99
-
set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
97
+
irq_set_chip_data(virq, h->host_data);
98
+
irq_set_status_flags(virq, IRQ_LEVEL);
99
+
irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
100
100
return 0;
101
101
}
102
102
103
103
static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq)
104
104
{
105
-
set_irq_chip_data(irq, NULL);
106
-
set_irq_chip(irq, NULL);
105
+
irq_set_chip_data(irq, NULL);
106
+
irq_set_chip(irq, NULL);
107
107
}
108
108
109
109
static struct irq_host_ops hlwd_irq_host_ops = {
···
129
129
static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
130
130
struct irq_desc *desc)
131
131
{
132
-
struct irq_chip *chip = get_irq_desc_chip(desc);
133
-
struct irq_host *irq_host = get_irq_data(cascade_virq);
132
+
struct irq_chip *chip = irq_desc_get_chip(desc);
133
+
struct irq_host *irq_host = irq_get_handler_data(cascade_virq);
134
134
unsigned int virq;
135
135
136
136
raw_spin_lock(&desc->lock);
···
145
145
146
146
raw_spin_lock(&desc->lock);
147
147
chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
148
-
if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
148
+
if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
149
149
chip->irq_unmask(&desc->irq_data);
150
150
raw_spin_unlock(&desc->lock);
151
151
}
···
218
218
host = hlwd_pic_init(np);
219
219
BUG_ON(!host);
220
220
cascade_virq = irq_of_parse_and_map(np, 0);
221
-
set_irq_data(cascade_virq, host);
222
-
set_irq_chained_handler(cascade_virq,
221
+
irq_set_handler_data(cascade_virq, host);
222
+
irq_set_chained_handler(cascade_virq,
223
223
hlwd_pic_irq_cascade);
224
224
hlwd_irq_host = host;
225
225
break;
+2
-2
arch/powerpc/platforms/embedded6xx/holly.c
+2
-2
arch/powerpc/platforms/embedded6xx/holly.c
···
198
198
cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
199
199
pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq);
200
200
tsi108_pci_int_init(cascade_node);
201
-
set_irq_data(cascade_pci_irq, mpic);
202
-
set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
201
+
irq_set_handler_data(cascade_pci_irq, mpic);
202
+
irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
203
203
#endif
204
204
/* Configure MPIC outputs to CPU0 */
205
205
tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
+2
-2
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+2
-2
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
···
153
153
DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
154
154
(u32) cascade_pci_irq);
155
155
tsi108_pci_int_init(cascade_node);
156
-
set_irq_data(cascade_pci_irq, mpic);
157
-
set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
156
+
irq_set_handler_data(cascade_pci_irq, mpic);
157
+
irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
158
158
#endif
159
159
/* Configure MPIC outputs to CPU0 */
160
160
tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
+2
-2
arch/powerpc/platforms/iseries/irq.c
+2
-2
arch/powerpc/platforms/iseries/irq.c
···
220
220
if (!desc)
221
221
continue;
222
222
223
-
chip = get_irq_desc_chip(desc);
223
+
chip = irq_desc_get_chip(desc);
224
224
if (chip && chip->irq_startup) {
225
225
raw_spin_lock_irqsave(&desc->lock, flags);
226
226
chip->irq_startup(&desc->irq_data);
···
346
346
static int iseries_irq_host_map(struct irq_host *h, unsigned int virq,
347
347
irq_hw_number_t hw)
348
348
{
349
-
set_irq_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq);
349
+
irq_set_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq);
350
350
351
351
return 0;
352
352
}
+1
-1
arch/powerpc/platforms/maple/pci.c
+1
-1
arch/powerpc/platforms/maple/pci.c
···
498
498
printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
499
499
dev->irq = irq_create_mapping(NULL, 1);
500
500
if (dev->irq != NO_IRQ)
501
-
set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
501
+
irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
502
502
}
503
503
504
504
/* Hide AMD8111 IDE interrupt when in legacy mode so
+1
-1
arch/powerpc/platforms/pasemi/setup.c
+1
-1
arch/powerpc/platforms/pasemi/setup.c
···
239
239
if (nmiprop) {
240
240
nmi_virq = irq_create_mapping(NULL, *nmiprop);
241
241
mpic_irq_set_priority(nmi_virq, 15);
242
-
set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
242
+
irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
243
243
mpic_unmask_irq(irq_get_irq_data(nmi_virq));
244
244
}
245
245
+1
-1
arch/powerpc/platforms/powermac/pci.c
+1
-1
arch/powerpc/platforms/powermac/pci.c
···
988
988
dev->vendor == PCI_VENDOR_ID_DEC &&
989
989
dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
990
990
dev->irq = irq_create_mapping(NULL, 60);
991
-
set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
991
+
irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
992
992
}
993
993
#endif /* CONFIG_PPC32 */
994
994
}
+8
-9
arch/powerpc/platforms/powermac/pic.c
+8
-9
arch/powerpc/platforms/powermac/pic.c
···
157
157
int i = src >> 5;
158
158
159
159
raw_spin_lock_irqsave(&pmac_pic_lock, flags);
160
-
if ((irq_to_desc(d->irq)->status & IRQ_LEVEL) == 0)
160
+
if (!irqd_is_level_type(d))
161
161
out_le32(&pmac_irq_hw[i]->ack, bit);
162
162
__set_bit(src, ppc_cached_irq_mask);
163
163
__pmac_set_irq_mask(src, 0);
···
289
289
static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
290
290
irq_hw_number_t hw)
291
291
{
292
-
struct irq_desc *desc = irq_to_desc(virq);
293
292
int level;
294
293
295
294
if (hw >= max_irqs)
···
299
300
*/
300
301
level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
301
302
if (level)
302
-
desc->status |= IRQ_LEVEL;
303
-
set_irq_chip_and_handler(virq, &pmac_pic, level ?
304
-
handle_level_irq : handle_edge_irq);
303
+
irq_set_status_flags(virq, IRQ_LEVEL);
304
+
irq_set_chip_and_handler(virq, &pmac_pic,
305
+
level ? handle_level_irq : handle_edge_irq);
305
306
return 0;
306
307
}
307
308
···
471
472
472
473
static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
473
474
{
474
-
struct irq_chip *chip = get_irq_desc_chip(desc);
475
-
struct mpic *mpic = get_irq_desc_data(desc);
475
+
struct irq_chip *chip = irq_desc_get_chip(desc);
476
+
struct mpic *mpic = irq_desc_get_handler_data(desc);
476
477
unsigned int cascade_irq = mpic_get_one_irq(mpic);
477
478
478
479
if (cascade_irq != NO_IRQ)
···
590
591
of_node_put(slave);
591
592
return 0;
592
593
}
593
-
set_irq_data(cascade, mpic2);
594
-
set_irq_chained_handler(cascade, pmac_u3_cascade);
594
+
irq_set_handler_data(cascade, mpic2);
595
+
irq_set_chained_handler(cascade, pmac_u3_cascade);
595
596
596
597
of_node_put(slave);
597
598
return 0;
+7
-7
arch/powerpc/platforms/ps3/interrupt.c
+7
-7
arch/powerpc/platforms/ps3/interrupt.c
···
194
194
pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__,
195
195
outlet, cpu, *virq);
196
196
197
-
result = set_irq_chip_data(*virq, pd);
197
+
result = irq_set_chip_data(*virq, pd);
198
198
199
199
if (result) {
200
200
pr_debug("%s:%d: set_irq_chip_data failed\n",
···
221
221
222
222
static int ps3_virq_destroy(unsigned int virq)
223
223
{
224
-
const struct ps3_private *pd = get_irq_chip_data(virq);
224
+
const struct ps3_private *pd = irq_get_chip_data(virq);
225
225
226
226
pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
227
227
__LINE__, pd->ppe_id, pd->thread_id, virq);
228
228
229
-
set_irq_chip_data(virq, NULL);
229
+
irq_set_chip_data(virq, NULL);
230
230
irq_dispose_mapping(virq);
231
231
232
232
pr_debug("%s:%d <-\n", __func__, __LINE__);
···
256
256
goto fail_setup;
257
257
}
258
258
259
-
pd = get_irq_chip_data(*virq);
259
+
pd = irq_get_chip_data(*virq);
260
260
261
261
/* Binds outlet to cpu + virq. */
262
262
···
291
291
int ps3_irq_plug_destroy(unsigned int virq)
292
292
{
293
293
int result;
294
-
const struct ps3_private *pd = get_irq_chip_data(virq);
294
+
const struct ps3_private *pd = irq_get_chip_data(virq);
295
295
296
296
pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
297
297
__LINE__, pd->ppe_id, pd->thread_id, virq);
···
661
661
662
662
static void ps3_host_unmap(struct irq_host *h, unsigned int virq)
663
663
{
664
-
set_irq_chip_data(virq, NULL);
664
+
irq_set_chip_data(virq, NULL);
665
665
}
666
666
667
667
static int ps3_host_map(struct irq_host *h, unsigned int virq,
···
670
670
pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq,
671
671
virq);
672
672
673
-
set_irq_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq);
673
+
irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq);
674
674
675
675
return 0;
676
676
}
+2
-2
arch/powerpc/platforms/pseries/msi.c
+2
-2
arch/powerpc/platforms/pseries/msi.c
···
137
137
if (entry->irq == NO_IRQ)
138
138
continue;
139
139
140
-
set_irq_msi(entry->irq, NULL);
140
+
irq_set_msi_desc(entry->irq, NULL);
141
141
irq_dispose_mapping(entry->irq);
142
142
}
143
143
···
437
437
}
438
438
439
439
dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq);
440
-
set_irq_msi(virq, entry);
440
+
irq_set_msi_desc(virq, entry);
441
441
442
442
/* Read config space back so we can restore after reset */
443
443
read_msi_msg(virq, &msg);
+2
-2
arch/powerpc/platforms/pseries/setup.c
+2
-2
arch/powerpc/platforms/pseries/setup.c
···
114
114
115
115
static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
116
116
{
117
-
struct irq_chip *chip = get_irq_desc_chip(desc);
117
+
struct irq_chip *chip = irq_desc_get_chip(desc);
118
118
unsigned int cascade_irq = i8259_irq();
119
119
120
120
if (cascade_irq != NO_IRQ)
···
169
169
printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
170
170
i8259_init(found, intack);
171
171
of_node_put(found);
172
-
set_irq_chained_handler(cascade, pseries_8259_cascade);
172
+
irq_set_chained_handler(cascade, pseries_8259_cascade);
173
173
}
174
174
175
175
static void __init pseries_mpic_init_IRQ(void)
+4
-4
arch/powerpc/platforms/pseries/xics.c
+4
-4
arch/powerpc/platforms/pseries/xics.c
···
470
470
/* Insert the interrupt mapping into the radix tree for fast lookup */
471
471
irq_radix_revmap_insert(xics_host, virq, hw);
472
472
473
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
474
-
set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
473
+
irq_set_status_flags(virq, IRQ_LEVEL);
474
+
irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
475
475
return 0;
476
476
}
477
477
···
600
600
* IPIs are marked IRQF_DISABLED as they must run with irqs
601
601
* disabled
602
602
*/
603
-
set_irq_handler(ipi, handle_percpu_irq);
603
+
irq_set_handler(ipi, handle_percpu_irq);
604
604
if (firmware_has_feature(FW_FEATURE_LPAR))
605
605
rc = request_irq(ipi, xics_ipi_action_lpar,
606
606
IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
···
912
912
if (desc == NULL || desc->action == NULL)
913
913
continue;
914
914
915
-
chip = get_irq_desc_chip(desc);
915
+
chip = irq_desc_get_chip(desc);
916
916
if (chip == NULL || chip->irq_set_affinity == NULL)
917
917
continue;
918
918
+2
-2
arch/powerpc/sysdev/cpm1.c
+2
-2
arch/powerpc/sysdev/cpm1.c
···
103
103
{
104
104
pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
105
105
106
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
107
-
set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
106
+
irq_set_status_flags(virq, IRQ_LEVEL);
107
+
irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
108
108
return 0;
109
109
}
110
110
+20
-27
arch/powerpc/sysdev/cpm2_pic.c
+20
-27
arch/powerpc/sysdev/cpm2_pic.c
···
115
115
116
116
static void cpm2_end_irq(struct irq_data *d)
117
117
{
118
-
struct irq_desc *desc;
119
118
int bit, word;
120
119
unsigned int irq_nr = virq_to_hw(d->irq);
121
120
122
-
desc = irq_to_desc(irq_nr);
123
-
if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))
124
-
&& desc->action) {
121
+
bit = irq_to_siubit[irq_nr];
122
+
word = irq_to_siureg[irq_nr];
125
123
126
-
bit = irq_to_siubit[irq_nr];
127
-
word = irq_to_siureg[irq_nr];
124
+
ppc_cached_irq_mask[word] |= 1 << bit;
125
+
out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
128
126
129
-
ppc_cached_irq_mask[word] |= 1 << bit;
130
-
out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
131
-
132
-
/*
133
-
* Work around large numbers of spurious IRQs on PowerPC 82xx
134
-
* systems.
135
-
*/
136
-
mb();
137
-
}
127
+
/*
128
+
* Work around large numbers of spurious IRQs on PowerPC 82xx
129
+
* systems.
130
+
*/
131
+
mb();
138
132
}
139
133
140
134
static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
141
135
{
142
136
unsigned int src = virq_to_hw(d->irq);
143
-
struct irq_desc *desc = irq_to_desc(d->irq);
144
137
unsigned int vold, vnew, edibit;
145
138
146
139
/* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
···
155
162
goto err_sense;
156
163
}
157
164
158
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
159
-
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
160
-
if (flow_type & IRQ_TYPE_LEVEL_LOW) {
161
-
desc->status |= IRQ_LEVEL;
162
-
desc->handle_irq = handle_level_irq;
163
-
} else
164
-
desc->handle_irq = handle_edge_irq;
165
+
irqd_set_trigger_type(d, flow_type);
166
+
if (flow_type & IRQ_TYPE_LEVEL_LOW)
167
+
__irq_set_handler_locked(d->irq, handle_level_irq);
168
+
else
169
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
165
170
166
171
/* internal IRQ senses are LEVEL_LOW
167
172
* EXT IRQ and Port C IRQ senses are programmable
···
170
179
if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
171
180
edibit = (31 - (CPM2_IRQ_PORTC0 - src));
172
181
else
173
-
return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
182
+
return (flow_type & IRQ_TYPE_LEVEL_LOW) ?
183
+
IRQ_SET_MASK_OK_NOCOPY : -EINVAL;
174
184
175
185
vold = in_be32(&cpm2_intctl->ic_siexr);
176
186
···
182
190
183
191
if (vold != vnew)
184
192
out_be32(&cpm2_intctl->ic_siexr, vnew);
185
-
return 0;
193
+
return IRQ_SET_MASK_OK_NOCOPY;
186
194
187
195
err_sense:
188
196
pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
···
196
204
.irq_ack = cpm2_ack,
197
205
.irq_eoi = cpm2_end_irq,
198
206
.irq_set_type = cpm2_set_irq_type,
207
+
.flags = IRQCHIP_EOI_IF_HANDLED,
199
208
};
200
209
201
210
unsigned int cpm2_get_irq(void)
···
219
226
{
220
227
pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
221
228
222
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
223
-
set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
229
+
irq_set_status_flags(virq, IRQ_LEVEL);
230
+
irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
224
231
return 0;
225
232
}
226
233
+22
-21
arch/powerpc/sysdev/fsl_msi.c
+22
-21
arch/powerpc/sysdev/fsl_msi.c
···
64
64
struct fsl_msi *msi_data = h->host_data;
65
65
struct irq_chip *chip = &fsl_msi_chip;
66
66
67
-
irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
67
+
irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
68
68
69
-
set_irq_chip_data(virq, msi_data);
70
-
set_irq_chip_and_handler(virq, chip, handle_edge_irq);
69
+
irq_set_chip_data(virq, msi_data);
70
+
irq_set_chip_and_handler(virq, chip, handle_edge_irq);
71
71
72
72
return 0;
73
73
}
···
110
110
list_for_each_entry(entry, &pdev->msi_list, list) {
111
111
if (entry->irq == NO_IRQ)
112
112
continue;
113
-
msi_data = get_irq_data(entry->irq);
114
-
set_irq_msi(entry->irq, NULL);
113
+
msi_data = irq_get_handler_data(entry->irq);
114
+
irq_set_msi_desc(entry->irq, NULL);
115
115
msi_bitmap_free_hwirqs(&msi_data->bitmap,
116
116
virq_to_hw(entry->irq), 1);
117
117
irq_dispose_mapping(entry->irq);
···
168
168
rc = -ENOSPC;
169
169
goto out_free;
170
170
}
171
-
set_irq_data(virq, msi_data);
172
-
set_irq_msi(virq, entry);
171
+
irq_set_handler_data(virq, msi_data);
172
+
irq_set_msi_desc(virq, entry);
173
173
174
174
fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
175
175
write_msi_msg(virq, &msg);
···
183
183
184
184
static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
185
185
{
186
-
struct irq_chip *chip = get_irq_desc_chip(desc);
186
+
struct irq_chip *chip = irq_desc_get_chip(desc);
187
+
struct irq_data *idata = irq_desc_get_irq_data(desc);
187
188
unsigned int cascade_irq;
188
189
struct fsl_msi *msi_data;
189
190
int msir_index = -1;
···
193
192
u32 have_shift = 0;
194
193
struct fsl_msi_cascade_data *cascade_data;
195
194
196
-
cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
195
+
cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq);
197
196
msi_data = cascade_data->msi_data;
198
197
199
198
raw_spin_lock(&desc->lock);
200
199
if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
201
200
if (chip->irq_mask_ack)
202
-
chip->irq_mask_ack(&desc->irq_data);
201
+
chip->irq_mask_ack(idata);
203
202
else {
204
-
chip->irq_mask(&desc->irq_data);
205
-
chip->irq_ack(&desc->irq_data);
203
+
chip->irq_mask(idata);
204
+
chip->irq_ack(idata);
206
205
}
207
206
}
208
207
209
-
if (unlikely(desc->status & IRQ_INPROGRESS))
208
+
if (unlikely(irqd_irq_inprogress(idata)))
210
209
goto unlock;
211
210
212
211
msir_index = cascade_data->index;
···
214
213
if (msir_index >= NR_MSI_REG)
215
214
cascade_irq = NO_IRQ;
216
215
217
-
desc->status |= IRQ_INPROGRESS;
216
+
irqd_set_chained_irq_inprogress(idata);
218
217
switch (msi_data->feature & FSL_PIC_IP_MASK) {
219
218
case FSL_PIC_IP_MPIC:
220
219
msir_value = fsl_msi_read(msi_data->msi_regs,
···
236
235
have_shift += intr_index + 1;
237
236
msir_value = msir_value >> (intr_index + 1);
238
237
}
239
-
desc->status &= ~IRQ_INPROGRESS;
238
+
irqd_clr_chained_irq_inprogress(idata);
240
239
241
240
switch (msi_data->feature & FSL_PIC_IP_MASK) {
242
241
case FSL_PIC_IP_MPIC:
243
-
chip->irq_eoi(&desc->irq_data);
242
+
chip->irq_eoi(idata);
244
243
break;
245
244
case FSL_PIC_IP_IPIC:
246
-
if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
247
-
chip->irq_unmask(&desc->irq_data);
245
+
if (!irqd_irq_disabled(idata) && chip->irq_unmask)
246
+
chip->irq_unmask(idata);
248
247
break;
249
248
}
250
249
unlock:
···
262
261
for (i = 0; i < NR_MSI_REG; i++) {
263
262
virq = msi->msi_virqs[i];
264
263
if (virq != NO_IRQ) {
265
-
cascade_data = get_irq_data(virq);
264
+
cascade_data = irq_get_handler_data(virq);
266
265
kfree(cascade_data);
267
266
irq_dispose_mapping(virq);
268
267
}
···
298
297
msi->msi_virqs[irq_index] = virt_msir;
299
298
cascade_data->index = offset + irq_index;
300
299
cascade_data->msi_data = msi;
301
-
set_irq_data(virt_msir, cascade_data);
302
-
set_irq_chained_handler(virt_msir, fsl_msi_cascade);
300
+
irq_set_handler_data(virt_msir, cascade_data);
301
+
irq_set_chained_handler(virt_msir, fsl_msi_cascade);
303
302
304
303
return 0;
305
304
}
+4
-4
arch/powerpc/sysdev/i8259.c
+4
-4
arch/powerpc/sysdev/i8259.c
···
175
175
176
176
/* We block the internal cascade */
177
177
if (hw == 2)
178
-
irq_to_desc(virq)->status |= IRQ_NOREQUEST;
178
+
irq_set_status_flags(virq, IRQ_NOREQUEST);
179
179
180
180
/* We use the level handler only for now, we might want to
181
181
* be more cautious here but that works for now
182
182
*/
183
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
184
-
set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
183
+
irq_set_status_flags(virq, IRQ_LEVEL);
184
+
irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
185
185
return 0;
186
186
}
187
187
···
191
191
i8259_mask_irq(irq_get_irq_data(virq));
192
192
193
193
/* remove chip and handler */
194
-
set_irq_chip_and_handler(virq, NULL, NULL);
194
+
irq_set_chip_and_handler(virq, NULL, NULL);
195
195
196
196
/* Make sure it's completed */
197
197
synchronize_irq(virq);
+10
-12
arch/powerpc/sysdev/ipic.c
+10
-12
arch/powerpc/sysdev/ipic.c
···
605
605
{
606
606
struct ipic *ipic = ipic_from_irq(d->irq);
607
607
unsigned int src = ipic_irq_to_hw(d->irq);
608
-
struct irq_desc *desc = irq_to_desc(d->irq);
609
608
unsigned int vold, vnew, edibit;
610
609
611
610
if (flow_type == IRQ_TYPE_NONE)
···
622
623
printk(KERN_ERR "ipic: edge sense not supported on internal "
623
624
"interrupts\n");
624
625
return -EINVAL;
626
+
625
627
}
626
628
627
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
628
-
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
629
+
irqd_set_trigger_type(d, flow_type);
629
630
if (flow_type & IRQ_TYPE_LEVEL_LOW) {
630
-
desc->status |= IRQ_LEVEL;
631
-
desc->handle_irq = handle_level_irq;
632
-
desc->irq_data.chip = &ipic_level_irq_chip;
631
+
__irq_set_handler_locked(d->irq, handle_level_irq);
632
+
d->chip = &ipic_level_irq_chip;
633
633
} else {
634
-
desc->handle_irq = handle_edge_irq;
635
-
desc->irq_data.chip = &ipic_edge_irq_chip;
634
+
__irq_set_handler_locked(d->irq, handle_edge_irq);
635
+
d->chip = &ipic_edge_irq_chip;
636
636
}
637
637
638
638
/* only EXT IRQ senses are programmable on ipic
···
653
655
}
654
656
if (vold != vnew)
655
657
ipic_write(ipic->regs, IPIC_SECNR, vnew);
656
-
return 0;
658
+
return IRQ_SET_MASK_OK_NOCOPY;
657
659
}
658
660
659
661
/* level interrupts and edge interrupts have different ack operations */
···
685
687
{
686
688
struct ipic *ipic = h->host_data;
687
689
688
-
set_irq_chip_data(virq, ipic);
689
-
set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
690
+
irq_set_chip_data(virq, ipic);
691
+
irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
690
692
691
693
/* Set default irq type */
692
-
set_irq_type(virq, IRQ_TYPE_NONE);
694
+
irq_set_irq_type(virq, IRQ_TYPE_NONE);
693
695
694
696
return 0;
695
697
}
+2
-9
arch/powerpc/sysdev/mpc8xx_pic.c
+2
-9
arch/powerpc/sysdev/mpc8xx_pic.c
···
72
72
73
73
static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
74
74
{
75
-
struct irq_desc *desc = irq_to_desc(d->irq);
76
-
77
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
78
-
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
79
-
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
80
-
desc->status |= IRQ_LEVEL;
81
-
82
75
if (flow_type & IRQ_TYPE_EDGE_FALLING) {
83
76
irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq;
84
77
unsigned int siel = in_be32(&siu_reg->sc_siel);
···
80
87
if ((hw & 1) == 0) {
81
88
siel |= (0x80000000 >> hw);
82
89
out_be32(&siu_reg->sc_siel, siel);
83
-
desc->handle_irq = handle_edge_irq;
90
+
__irq_set_handler_locked(irq, handle_edge_irq);
84
91
}
85
92
}
86
93
return 0;
···
117
124
pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
118
125
119
126
/* Set default irq handle */
120
-
set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
127
+
irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
121
128
return 0;
122
129
}
123
130
+6
-6
arch/powerpc/sysdev/mpc8xxx_gpio.c
+6
-6
arch/powerpc/sysdev/mpc8xxx_gpio.c
···
145
145
146
146
static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
147
147
{
148
-
struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
148
+
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
149
149
struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
150
150
unsigned int mask;
151
151
···
278
278
if (mpc8xxx_gc->of_dev_id_data)
279
279
mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
280
280
281
-
set_irq_chip_data(virq, h->host_data);
282
-
set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
283
-
set_irq_type(virq, IRQ_TYPE_NONE);
281
+
irq_set_chip_data(virq, h->host_data);
282
+
irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
283
+
irq_set_irq_type(virq, IRQ_TYPE_NONE);
284
284
285
285
return 0;
286
286
}
···
369
369
out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
370
370
out_be32(mm_gc->regs + GPIO_IMR, 0);
371
371
372
-
set_irq_data(hwirq, mpc8xxx_gc);
373
-
set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
372
+
irq_set_handler_data(hwirq, mpc8xxx_gc);
373
+
irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
374
374
375
375
skip_irq:
376
376
return;
+19
-24
arch/powerpc/sysdev/mpic.c
+19
-24
arch/powerpc/sysdev/mpic.c
···
361
361
}
362
362
363
363
static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
364
-
unsigned int irqflags)
364
+
bool level)
365
365
{
366
366
struct mpic_irq_fixup *fixup = &mpic->fixups[source];
367
367
unsigned long flags;
···
370
370
if (fixup->base == NULL)
371
371
return;
372
372
373
-
DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
374
-
source, irqflags, fixup->index);
373
+
DBG("startup_ht_interrupt(0x%x) index: %d\n",
374
+
source, fixup->index);
375
375
raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
376
376
/* Enable and configure */
377
377
writeb(0x10 + 2 * fixup->index, fixup->base + 2);
378
378
tmp = readl(fixup->base + 4);
379
379
tmp &= ~(0x23U);
380
-
if (irqflags & IRQ_LEVEL)
380
+
if (level)
381
381
tmp |= 0x22;
382
382
writel(tmp, fixup->base + 4);
383
383
raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
···
389
389
#endif
390
390
}
391
391
392
-
static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
393
-
unsigned int irqflags)
392
+
static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
394
393
{
395
394
struct mpic_irq_fixup *fixup = &mpic->fixups[source];
396
395
unsigned long flags;
···
398
399
if (fixup->base == NULL)
399
400
return;
400
401
401
-
DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
402
+
DBG("shutdown_ht_interrupt(0x%x)\n", source);
402
403
403
404
/* Disable */
404
405
raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
···
615
616
if (irq < NUM_ISA_INTERRUPTS)
616
617
return NULL;
617
618
618
-
return get_irq_chip_data(irq);
619
+
return irq_get_chip_data(irq);
619
620
}
620
621
621
622
/* Determine if the linux irq is an IPI */
···
649
650
/* Get the mpic structure from the irq number */
650
651
static inline struct mpic * mpic_from_irq(unsigned int irq)
651
652
{
652
-
return get_irq_chip_data(irq);
653
+
return irq_get_chip_data(irq);
653
654
}
654
655
655
656
/* Get the mpic structure from the irq data */
···
737
738
738
739
mpic_unmask_irq(d);
739
740
740
-
if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
741
+
if (irqd_is_level_type(d))
741
742
mpic_ht_end_irq(mpic, src);
742
743
}
743
744
···
747
748
unsigned int src = mpic_irq_to_hw(d->irq);
748
749
749
750
mpic_unmask_irq(d);
750
-
mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
751
+
mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
751
752
752
753
return 0;
753
754
}
···
757
758
struct mpic *mpic = mpic_from_irq_data(d);
758
759
unsigned int src = mpic_irq_to_hw(d->irq);
759
760
760
-
mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
761
+
mpic_shutdown_ht_interrupt(mpic, src);
761
762
mpic_mask_irq(d);
762
763
}
763
764
···
774
775
* latched another edge interrupt coming in anyway
775
776
*/
776
777
777
-
if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
778
+
if (irqd_is_level_type(d))
778
779
mpic_ht_end_irq(mpic, src);
779
780
mpic_eoi(mpic);
780
781
}
···
863
864
{
864
865
struct mpic *mpic = mpic_from_irq_data(d);
865
866
unsigned int src = mpic_irq_to_hw(d->irq);
866
-
struct irq_desc *desc = irq_to_desc(d->irq);
867
867
unsigned int vecpri, vold, vnew;
868
868
869
869
DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
···
877
879
if (flow_type == IRQ_TYPE_NONE)
878
880
flow_type = IRQ_TYPE_LEVEL_LOW;
879
881
880
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
881
-
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
882
-
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
883
-
desc->status |= IRQ_LEVEL;
882
+
irqd_set_trigger_type(d, flow_type);
884
883
885
884
if (mpic_is_ht_interrupt(mpic, src))
886
885
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
···
892
897
if (vold != vnew)
893
898
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
894
899
895
-
return 0;
900
+
return IRQ_SET_MASK_OK_NOCOPY;;
896
901
}
897
902
898
903
void mpic_set_vector(unsigned int virq, unsigned int vector)
···
978
983
WARN_ON(!(mpic->flags & MPIC_PRIMARY));
979
984
980
985
DBG("mpic: mapping as IPI\n");
981
-
set_irq_chip_data(virq, mpic);
982
-
set_irq_chip_and_handler(virq, &mpic->hc_ipi,
986
+
irq_set_chip_data(virq, mpic);
987
+
irq_set_chip_and_handler(virq, &mpic->hc_ipi,
983
988
handle_percpu_irq);
984
989
return 0;
985
990
}
···
1001
1006
1002
1007
DBG("mpic: mapping to irq chip @%p\n", chip);
1003
1008
1004
-
set_irq_chip_data(virq, mpic);
1005
-
set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
1009
+
irq_set_chip_data(virq, mpic);
1010
+
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1006
1011
1007
1012
/* Set default irq type */
1008
-
set_irq_type(virq, IRQ_TYPE_NONE);
1013
+
irq_set_irq_type(virq, IRQ_TYPE_NONE);
1009
1014
1010
1015
/* If the MPIC was reset, then all vectors have already been
1011
1016
* initialized. Otherwise, a per source lazy initialization
+4
-4
arch/powerpc/sysdev/mpic_pasemi_msi.c
+4
-4
arch/powerpc/sysdev/mpic_pasemi_msi.c
···
81
81
if (entry->irq == NO_IRQ)
82
82
continue;
83
83
84
-
set_irq_msi(entry->irq, NULL);
84
+
irq_set_msi_desc(entry->irq, NULL);
85
85
msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
86
86
virq_to_hw(entry->irq), ALLOC_CHUNK);
87
87
irq_dispose_mapping(entry->irq);
···
131
131
*/
132
132
mpic_set_vector(virq, 0);
133
133
134
-
set_irq_msi(virq, entry);
135
-
set_irq_chip(virq, &mpic_pasemi_msi_chip);
136
-
set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
134
+
irq_set_msi_desc(virq, entry);
135
+
irq_set_chip(virq, &mpic_pasemi_msi_chip);
136
+
irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
137
137
138
138
pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
139
139
"addr 0x%x\n", virq, hwirq, msg.address_lo);
+4
-4
arch/powerpc/sysdev/mpic_u3msi.c
+4
-4
arch/powerpc/sysdev/mpic_u3msi.c
···
129
129
if (entry->irq == NO_IRQ)
130
130
continue;
131
131
132
-
set_irq_msi(entry->irq, NULL);
132
+
irq_set_msi_desc(entry->irq, NULL);
133
133
msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
134
134
virq_to_hw(entry->irq), 1);
135
135
irq_dispose_mapping(entry->irq);
···
166
166
return -ENOSPC;
167
167
}
168
168
169
-
set_irq_msi(virq, entry);
170
-
set_irq_chip(virq, &mpic_u3msi_chip);
171
-
set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
169
+
irq_set_msi_desc(virq, entry);
170
+
irq_set_chip(virq, &mpic_u3msi_chip);
171
+
irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
172
172
173
173
pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
174
174
virq, hwirq, (unsigned long)addr);
+3
-2
arch/powerpc/sysdev/mv64x60_pic.c
+3
-2
arch/powerpc/sysdev/mv64x60_pic.c
···
213
213
{
214
214
int level1;
215
215
216
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
216
+
irq_set_status_flags(virq, IRQ_LEVEL);
217
217
218
218
level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
219
219
BUG_ON(level1 > MV64x60_LEVEL1_GPP);
220
-
set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq);
220
+
irq_set_chip_and_handler(virq, mv64x60_chips[level1],
221
+
handle_level_irq);
221
222
222
223
return 0;
223
224
}
+8
-8
arch/powerpc/sysdev/qe_lib/qe_ic.c
+8
-8
arch/powerpc/sysdev/qe_lib/qe_ic.c
···
189
189
190
190
static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
191
191
{
192
-
return get_irq_chip_data(virq);
192
+
return irq_get_chip_data(virq);
193
193
}
194
194
195
195
static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
···
267
267
/* Default chip */
268
268
chip = &qe_ic->hc_irq;
269
269
270
-
set_irq_chip_data(virq, qe_ic);
271
-
irq_to_desc(virq)->status |= IRQ_LEVEL;
270
+
irq_set_chip_data(virq, qe_ic);
271
+
irq_set_status_flags(virq, IRQ_LEVEL);
272
272
273
-
set_irq_chip_and_handler(virq, chip, handle_level_irq);
273
+
irq_set_chip_and_handler(virq, chip, handle_level_irq);
274
274
275
275
return 0;
276
276
}
···
386
386
387
387
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
388
388
389
-
set_irq_data(qe_ic->virq_low, qe_ic);
390
-
set_irq_chained_handler(qe_ic->virq_low, low_handler);
389
+
irq_set_handler_data(qe_ic->virq_low, qe_ic);
390
+
irq_set_chained_handler(qe_ic->virq_low, low_handler);
391
391
392
392
if (qe_ic->virq_high != NO_IRQ &&
393
393
qe_ic->virq_high != qe_ic->virq_low) {
394
-
set_irq_data(qe_ic->virq_high, qe_ic);
395
-
set_irq_chained_handler(qe_ic->virq_high, high_handler);
394
+
irq_set_handler_data(qe_ic->virq_high, qe_ic);
395
+
irq_set_chained_handler(qe_ic->virq_high, high_handler);
396
396
}
397
397
}
398
398
+3
-3
arch/powerpc/sysdev/tsi108_pci.c
+3
-3
arch/powerpc/sysdev/tsi108_pci.c
···
391
391
DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
392
392
if ((virq >= 1) && (virq <= 4)){
393
393
irq = virq + IRQ_PCI_INTAD_BASE - 1;
394
-
irq_to_desc(irq)->status |= IRQ_LEVEL;
395
-
set_irq_chip(irq, &tsi108_pci_irq);
394
+
irq_set_status_flags(irq, IRQ_LEVEL);
395
+
irq_set_chip(irq, &tsi108_pci_irq);
396
396
}
397
397
return 0;
398
398
}
···
431
431
432
432
void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
433
433
{
434
-
struct irq_chip *chip = get_irq_desc_chip(desc);
434
+
struct irq_chip *chip = irq_desc_get_chip(desc);
435
435
unsigned int cascade_irq = get_pci_source();
436
436
437
437
if (cascade_irq != NO_IRQ)
+17
-24
arch/powerpc/sysdev/uic.c
+17
-24
arch/powerpc/sysdev/uic.c
···
57
57
58
58
static void uic_unmask_irq(struct irq_data *d)
59
59
{
60
-
struct irq_desc *desc = irq_to_desc(d->irq);
61
60
struct uic *uic = irq_data_get_irq_chip_data(d);
62
61
unsigned int src = uic_irq_to_hw(d->irq);
63
62
unsigned long flags;
···
65
66
sr = 1 << (31-src);
66
67
spin_lock_irqsave(&uic->lock, flags);
67
68
/* ack level-triggered interrupts here */
68
-
if (desc->status & IRQ_LEVEL)
69
+
if (irqd_is_level_type(d))
69
70
mtdcr(uic->dcrbase + UIC_SR, sr);
70
71
er = mfdcr(uic->dcrbase + UIC_ER);
71
72
er |= sr;
···
100
101
101
102
static void uic_mask_ack_irq(struct irq_data *d)
102
103
{
103
-
struct irq_desc *desc = irq_to_desc(d->irq);
104
104
struct uic *uic = irq_data_get_irq_chip_data(d);
105
105
unsigned int src = uic_irq_to_hw(d->irq);
106
106
unsigned long flags;
···
118
120
* level interrupts are ack'ed after the actual
119
121
* isr call in the uic_unmask_irq()
120
122
*/
121
-
if (!(desc->status & IRQ_LEVEL))
123
+
if (!irqd_is_level_type(d))
122
124
mtdcr(uic->dcrbase + UIC_SR, sr);
123
125
spin_unlock_irqrestore(&uic->lock, flags);
124
126
}
···
127
129
{
128
130
struct uic *uic = irq_data_get_irq_chip_data(d);
129
131
unsigned int src = uic_irq_to_hw(d->irq);
130
-
struct irq_desc *desc = irq_to_desc(d->irq);
131
132
unsigned long flags;
132
133
int trigger, polarity;
133
134
u32 tr, pr, mask;
···
163
166
mtdcr(uic->dcrbase + UIC_PR, pr);
164
167
mtdcr(uic->dcrbase + UIC_TR, tr);
165
168
166
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
167
-
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
168
-
if (!trigger)
169
-
desc->status |= IRQ_LEVEL;
170
-
171
169
spin_unlock_irqrestore(&uic->lock, flags);
172
170
173
171
return 0;
···
182
190
{
183
191
struct uic *uic = h->host_data;
184
192
185
-
set_irq_chip_data(virq, uic);
193
+
irq_set_chip_data(virq, uic);
186
194
/* Despite the name, handle_level_irq() works for both level
187
195
* and edge irqs on UIC. FIXME: check this is correct */
188
-
set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
196
+
irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
189
197
190
198
/* Set default irq type */
191
-
set_irq_type(virq, IRQ_TYPE_NONE);
199
+
irq_set_irq_type(virq, IRQ_TYPE_NONE);
192
200
193
201
return 0;
194
202
}
···
212
220
213
221
void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
214
222
{
215
-
struct irq_chip *chip = get_irq_desc_chip(desc);
216
-
struct uic *uic = get_irq_data(virq);
223
+
struct irq_chip *chip = irq_desc_get_chip(desc);
224
+
struct irq_data *idata = irq_desc_get_irq_data(desc);
225
+
struct uic *uic = irq_get_handler_data(virq);
217
226
u32 msr;
218
227
int src;
219
228
int subvirq;
220
229
221
230
raw_spin_lock(&desc->lock);
222
-
if (desc->status & IRQ_LEVEL)
223
-
chip->irq_mask(&desc->irq_data);
231
+
if (irqd_is_level_type(idata))
232
+
chip->irq_mask(idata);
224
233
else
225
-
chip->irq_mask_ack(&desc->irq_data);
234
+
chip->irq_mask_ack(idata);
226
235
raw_spin_unlock(&desc->lock);
227
236
228
237
msr = mfdcr(uic->dcrbase + UIC_MSR);
···
237
244
238
245
uic_irq_ret:
239
246
raw_spin_lock(&desc->lock);
240
-
if (desc->status & IRQ_LEVEL)
241
-
chip->irq_ack(&desc->irq_data);
242
-
if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
243
-
chip->irq_unmask(&desc->irq_data);
247
+
if (irqd_is_level_type(idata))
248
+
chip->irq_ack(idata);
249
+
if (!irqd_irq_disabled(idata) && chip->irq_unmask)
250
+
chip->irq_unmask(idata);
244
251
raw_spin_unlock(&desc->lock);
245
252
}
246
253
···
329
336
330
337
cascade_virq = irq_of_parse_and_map(np, 0);
331
338
332
-
set_irq_data(cascade_virq, uic);
333
-
set_irq_chained_handler(cascade_virq, uic_irq_cascade);
339
+
irq_set_handler_data(cascade_virq, uic);
340
+
irq_set_chained_handler(cascade_virq, uic_irq_cascade);
334
341
335
342
/* FIXME: setup critical cascade?? */
336
343
}
+7
-13
arch/powerpc/sysdev/xilinx_intc.c
+7
-13
arch/powerpc/sysdev/xilinx_intc.c
···
79
79
80
80
static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
81
81
{
82
-
struct irq_desc *desc = irq_to_desc(d->irq);
83
-
84
-
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
85
-
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
86
-
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
87
-
desc->status |= IRQ_LEVEL;
88
82
return 0;
89
83
}
90
84
···
164
170
static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
165
171
irq_hw_number_t irq)
166
172
{
167
-
set_irq_chip_data(virq, h->host_data);
173
+
irq_set_chip_data(virq, h->host_data);
168
174
169
175
if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
170
176
xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
171
-
set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip,
172
-
handle_level_irq);
177
+
irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip,
178
+
handle_level_irq);
173
179
} else {
174
-
set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
175
-
handle_edge_irq);
180
+
irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
181
+
handle_edge_irq);
176
182
}
177
183
return 0;
178
184
}
···
223
229
*/
224
230
static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
225
231
{
226
-
struct irq_chip *chip = get_irq_desc_chip(desc);
232
+
struct irq_chip *chip = irq_desc_get_chip(desc);
227
233
unsigned int cascade_irq = i8259_irq();
228
234
229
235
if (cascade_irq)
···
250
256
}
251
257
252
258
i8259_init(cascade_node, 0);
253
-
set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
259
+
irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
254
260
255
261
/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
256
262
/* This looks like a dirty hack to me --gcl */
+6
-6
arch/sh/boards/board-magicpanelr2.c
+6
-6
arch/sh/boards/board-magicpanelr2.c
···
388
388
{
389
389
plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
390
390
391
-
set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
392
-
set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
393
-
set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
394
-
set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
395
-
set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
396
-
set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
391
+
irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
392
+
irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
393
+
irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
394
+
irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
395
+
irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
396
+
irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
397
397
398
398
intc_set_priority(32, 13); /* IRQ0 CAN1 */
399
399
intc_set_priority(33, 13); /* IRQ0 CAN2 */
+2
-2
arch/sh/boards/mach-cayman/irq.c
+2
-2
arch/sh/boards/mach-cayman/irq.c
···
149
149
}
150
150
151
151
for (i = 0; i < NR_EXT_IRQS; i++) {
152
-
set_irq_chip_and_handler(START_EXT_IRQS + i, &cayman_irq_type,
153
-
handle_level_irq);
152
+
irq_set_chip_and_handler(START_EXT_IRQS + i,
153
+
&cayman_irq_type, handle_level_irq);
154
154
}
155
155
156
156
/* Setup the SMSC interrupt */
+1
-2
arch/sh/boards/mach-dreamcast/irq.c
+1
-2
arch/sh/boards/mach-dreamcast/irq.c
+1
-1
arch/sh/boards/mach-ecovec24/setup.c
+1
-1
arch/sh/boards/mach-ecovec24/setup.c
+1
-1
arch/sh/boards/mach-microdev/irq.c
+1
-1
arch/sh/boards/mach-microdev/irq.c
···
117
117
static void __init make_microdev_irq(unsigned int irq)
118
118
{
119
119
disable_irq_nosync(irq);
120
-
set_irq_chip_and_handler(irq, µdev_irq_type, handle_level_irq);
120
+
irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq);
121
121
disable_microdev_irq(irq_get_irq_data(irq));
122
122
}
123
123
+2
-3
arch/sh/boards/mach-se/7206/irq.c
+2
-3
arch/sh/boards/mach-se/7206/irq.c
···
92
92
{
93
93
unsigned short sts0,sts1;
94
94
unsigned int irq = data->irq;
95
-
struct irq_desc *desc = irq_to_desc(irq);
96
95
97
-
if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
96
+
if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
98
97
enable_se7206_irq(data);
99
98
/* FPGA isr clear */
100
99
sts0 = __raw_readw(INTSTS0);
···
125
126
static void make_se7206_irq(unsigned int irq)
126
127
{
127
128
disable_irq_nosync(irq);
128
-
set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
129
+
irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
129
130
handle_level_irq, "level");
130
131
disable_se7206_irq(irq_get_irq_data(irq));
131
132
}
+12
-11
arch/sh/boards/mach-se/7343/irq.c
+12
-11
arch/sh/boards/mach-se/7343/irq.c
···
67
67
return;
68
68
se7343_fpga_irq[i] = irq;
69
69
70
-
set_irq_chip_and_handler_name(se7343_fpga_irq[i],
70
+
irq_set_chip_and_handler_name(se7343_fpga_irq[i],
71
71
&se7343_irq_chip,
72
-
handle_level_irq, "level");
72
+
handle_level_irq,
73
+
"level");
73
74
74
-
set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
75
+
irq_set_chip_data(se7343_fpga_irq[i], (void *)i);
75
76
}
76
77
77
-
set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
78
-
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
79
-
set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
80
-
set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
81
-
set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
82
-
set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
83
-
set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
84
-
set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
78
+
irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
79
+
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
80
+
irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
81
+
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
82
+
irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
83
+
irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
84
+
irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
85
+
irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
85
86
}
+8
-7
arch/sh/boards/mach-se/7722/irq.c
+8
-7
arch/sh/boards/mach-se/7722/irq.c
···
67
67
return;
68
68
se7722_fpga_irq[i] = irq;
69
69
70
-
set_irq_chip_and_handler_name(se7722_fpga_irq[i],
70
+
irq_set_chip_and_handler_name(se7722_fpga_irq[i],
71
71
&se7722_irq_chip,
72
-
handle_level_irq, "level");
72
+
handle_level_irq,
73
+
"level");
73
74
74
-
set_irq_chip_data(se7722_fpga_irq[i], (void *)i);
75
+
irq_set_chip_data(se7722_fpga_irq[i], (void *)i);
75
76
}
76
77
77
-
set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux);
78
-
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
78
+
irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
79
+
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
79
80
80
-
set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux);
81
-
set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
81
+
irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
82
+
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
82
83
}
+7
-8
arch/sh/boards/mach-se/7724/irq.c
+7
-8
arch/sh/boards/mach-se/7724/irq.c
···
140
140
return;
141
141
}
142
142
143
-
set_irq_chip_and_handler_name(irq,
144
-
&se7724_irq_chip,
143
+
irq_set_chip_and_handler_name(irq, &se7724_irq_chip,
145
144
handle_level_irq, "level");
146
145
}
147
146
148
-
set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
149
-
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
147
+
irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
148
+
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
150
149
151
-
set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
152
-
set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
150
+
irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux);
151
+
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
153
152
154
-
set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
155
-
set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
153
+
irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux);
154
+
irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
156
155
}
+4
-4
arch/sh/boards/mach-x3proto/gpio.c
+4
-4
arch/sh/boards/mach-x3proto/gpio.c
···
102
102
103
103
spin_lock_irqsave(&x3proto_gpio_lock, flags);
104
104
x3proto_gpio_irq_map[i] = irq;
105
-
set_irq_chip_and_handler_name(irq, &dummy_irq_chip,
106
-
handle_simple_irq, "gpio");
105
+
irq_set_chip_and_handler_name(irq, &dummy_irq_chip,
106
+
handle_simple_irq, "gpio");
107
107
spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
108
108
}
109
109
···
113
113
x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio,
114
114
ilsel);
115
115
116
-
set_irq_chained_handler(ilsel, x3proto_gpio_irq_handler);
117
-
set_irq_wake(ilsel, 1);
116
+
irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler);
117
+
irq_set_irq_wake(ilsel, 1);
118
118
119
119
return 0;
120
120
+3
-3
arch/sh/cchips/hd6446x/hd64461.c
+3
-3
arch/sh/cchips/hd6446x/hd64461.c
···
107
107
return -EINVAL;
108
108
}
109
109
110
-
set_irq_chip_and_handler(i, &hd64461_irq_chip,
110
+
irq_set_chip_and_handler(i, &hd64461_irq_chip,
111
111
handle_level_irq);
112
112
}
113
113
114
-
set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
115
-
set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
114
+
irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
115
+
irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
116
116
117
117
#ifdef CONFIG_HD64461_ENABLER
118
118
printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
+2
-2
arch/sh/kernel/cpu/irq/imask.c
+2
-2
arch/sh/kernel/cpu/irq/imask.c
+1
-1
arch/sh/kernel/cpu/irq/intc-sh5.c
+1
-1
arch/sh/kernel/cpu/irq/intc-sh5.c
···
135
135
136
136
/* Set default: per-line enable/disable, priority driven ack/eoi */
137
137
for (i = 0; i < NR_INTC_IRQS; i++)
138
-
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
138
+
irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
139
139
140
140
141
141
/* Disable all interrupts and set all priorities to 0 to avoid trouble */
+3
-3
arch/sh/kernel/cpu/irq/ipr.c
+3
-3
arch/sh/kernel/cpu/irq/ipr.c
···
74
74
}
75
75
76
76
disable_irq_nosync(p->irq);
77
-
set_irq_chip_and_handler_name(p->irq, &desc->chip,
78
-
handle_level_irq, "level");
79
-
set_irq_chip_data(p->irq, p);
77
+
irq_set_chip_and_handler_name(p->irq, &desc->chip,
78
+
handle_level_irq, "level");
79
+
irq_set_chip_data(p->irq, p);
80
80
disable_ipr_irq(irq_get_irq_data(p->irq));
81
81
}
82
82
}
+2
arch/sparc/Kconfig
+2
arch/sparc/Kconfig
+33
-90
arch/sparc/kernel/irq_64.c
+33
-90
arch/sparc/kernel/irq_64.c
···
162
162
/*
163
163
* /proc/interrupts printing:
164
164
*/
165
-
166
-
int show_interrupts(struct seq_file *p, void *v)
165
+
int arch_show_interrupts(struct seq_file *p, int prec)
167
166
{
168
-
int i = *(loff_t *) v, j;
169
-
struct irqaction * action;
170
-
unsigned long flags;
167
+
int j;
171
168
172
-
if (i == 0) {
173
-
seq_printf(p, " ");
174
-
for_each_online_cpu(j)
175
-
seq_printf(p, "CPU%d ",j);
176
-
seq_putc(p, '\n');
177
-
}
178
-
179
-
if (i < NR_IRQS) {
180
-
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
181
-
action = irq_desc[i].action;
182
-
if (!action)
183
-
goto skip;
184
-
seq_printf(p, "%3d: ",i);
185
-
#ifndef CONFIG_SMP
186
-
seq_printf(p, "%10u ", kstat_irqs(i));
187
-
#else
188
-
for_each_online_cpu(j)
189
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
190
-
#endif
191
-
seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name);
192
-
seq_printf(p, " %s", action->name);
193
-
194
-
for (action=action->next; action; action = action->next)
195
-
seq_printf(p, ", %s", action->name);
196
-
197
-
seq_putc(p, '\n');
198
-
skip:
199
-
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
200
-
} else if (i == NR_IRQS) {
201
-
seq_printf(p, "NMI: ");
202
-
for_each_online_cpu(j)
203
-
seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
204
-
seq_printf(p, " Non-maskable interrupts\n");
205
-
}
169
+
seq_printf(p, "NMI: ");
170
+
for_each_online_cpu(j)
171
+
seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
172
+
seq_printf(p, " Non-maskable interrupts\n");
206
173
return 0;
207
174
}
208
175
···
311
344
static void sun4u_irq_eoi(struct irq_data *data)
312
345
{
313
346
struct irq_handler_data *handler_data = data->handler_data;
314
-
struct irq_desc *desc = irq_desc + data->irq;
315
-
316
-
if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
317
-
return;
318
347
319
348
if (likely(handler_data))
320
349
upa_writeq(ICLR_IDLE, handler_data->iclr);
···
365
402
static void sun4v_irq_eoi(struct irq_data *data)
366
403
{
367
404
unsigned int ino = irq_table[data->irq].dev_ino;
368
-
struct irq_desc *desc = irq_desc + data->irq;
369
405
int err;
370
-
371
-
if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
372
-
return;
373
406
374
407
err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
375
408
if (err != HV_EOK)
···
440
481
441
482
static void sun4v_virq_eoi(struct irq_data *data)
442
483
{
443
-
struct irq_desc *desc = irq_desc + data->irq;
444
484
unsigned long dev_handle, dev_ino;
445
485
int err;
446
-
447
-
if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
448
-
return;
449
486
450
487
dev_handle = irq_table[data->irq].dev_handle;
451
488
dev_ino = irq_table[data->irq].dev_ino;
···
460
505
.irq_disable = sun4u_irq_disable,
461
506
.irq_eoi = sun4u_irq_eoi,
462
507
.irq_set_affinity = sun4u_set_affinity,
508
+
.flags = IRQCHIP_EOI_IF_HANDLED,
463
509
};
464
510
465
511
static struct irq_chip sun4v_irq = {
···
469
513
.irq_disable = sun4v_irq_disable,
470
514
.irq_eoi = sun4v_irq_eoi,
471
515
.irq_set_affinity = sun4v_set_affinity,
516
+
.flags = IRQCHIP_EOI_IF_HANDLED,
472
517
};
473
518
474
519
static struct irq_chip sun4v_virq = {
···
478
521
.irq_disable = sun4v_virq_disable,
479
522
.irq_eoi = sun4v_virq_eoi,
480
523
.irq_set_affinity = sun4v_virt_set_affinity,
524
+
.flags = IRQCHIP_EOI_IF_HANDLED,
481
525
};
482
526
483
-
static void pre_flow_handler(unsigned int irq, struct irq_desc *desc)
527
+
static void pre_flow_handler(struct irq_data *d)
484
528
{
485
-
struct irq_handler_data *handler_data = get_irq_data(irq);
486
-
unsigned int ino = irq_table[irq].dev_ino;
529
+
struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d);
530
+
unsigned int ino = irq_table[d->irq].dev_ino;
487
531
488
532
handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2);
489
-
490
-
handle_fasteoi_irq(irq, desc);
491
533
}
492
534
493
535
void irq_install_pre_handler(int irq,
494
536
void (*func)(unsigned int, void *, void *),
495
537
void *arg1, void *arg2)
496
538
{
497
-
struct irq_handler_data *handler_data = get_irq_data(irq);
498
-
struct irq_desc *desc = irq_desc + irq;
539
+
struct irq_handler_data *handler_data = irq_get_handler_data(irq);
499
540
500
541
handler_data->pre_handler = func;
501
542
handler_data->arg1 = arg1;
502
543
handler_data->arg2 = arg2;
503
544
504
-
desc->handle_irq = pre_flow_handler;
545
+
__irq_set_preflow_handler(irq, pre_flow_handler);
505
546
}
506
547
507
548
unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
···
517
562
if (!irq) {
518
563
irq = irq_alloc(0, ino);
519
564
bucket_set_irq(__pa(bucket), irq);
520
-
set_irq_chip_and_handler_name(irq,
521
-
&sun4u_irq,
522
-
handle_fasteoi_irq,
523
-
"IVEC");
565
+
irq_set_chip_and_handler_name(irq, &sun4u_irq,
566
+
handle_fasteoi_irq, "IVEC");
524
567
}
525
568
526
-
handler_data = get_irq_data(irq);
569
+
handler_data = irq_get_handler_data(irq);
527
570
if (unlikely(handler_data))
528
571
goto out;
529
572
···
530
577
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
531
578
prom_halt();
532
579
}
533
-
set_irq_data(irq, handler_data);
580
+
irq_set_handler_data(irq, handler_data);
534
581
535
582
handler_data->imap = imap;
536
583
handler_data->iclr = iclr;
···
553
600
if (!irq) {
554
601
irq = irq_alloc(0, sysino);
555
602
bucket_set_irq(__pa(bucket), irq);
556
-
set_irq_chip_and_handler_name(irq, chip,
557
-
handle_fasteoi_irq,
603
+
irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
558
604
"IVEC");
559
605
}
560
606
561
-
handler_data = get_irq_data(irq);
607
+
handler_data = irq_get_handler_data(irq);
562
608
if (unlikely(handler_data))
563
609
goto out;
564
610
···
566
614
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
567
615
prom_halt();
568
616
}
569
-
set_irq_data(irq, handler_data);
617
+
irq_set_handler_data(irq, handler_data);
570
618
571
619
/* Catch accidental accesses to these things. IMAP/ICLR handling
572
620
* is done by hypervisor calls on sun4v platforms, not by direct
···
591
639
struct irq_handler_data *handler_data;
592
640
unsigned long hv_err, cookie;
593
641
struct ino_bucket *bucket;
594
-
struct irq_desc *desc;
595
642
unsigned int irq;
596
643
597
644
bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
···
611
660
irq = irq_alloc(devhandle, devino);
612
661
bucket_set_irq(__pa(bucket), irq);
613
662
614
-
set_irq_chip_and_handler_name(irq, &sun4v_virq,
615
-
handle_fasteoi_irq,
663
+
irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq,
616
664
"IVEC");
617
665
618
666
handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
···
622
672
* especially wrt. locking, we do not let request_irq() enable
623
673
* the interrupt.
624
674
*/
625
-
desc = irq_desc + irq;
626
-
desc->status |= IRQ_NOAUTOEN;
627
-
628
-
set_irq_data(irq, handler_data);
675
+
irq_set_status_flags(irq, IRQ_NOAUTOEN);
676
+
irq_set_handler_data(irq, handler_data);
629
677
630
678
/* Catch accidental accesses to these things. IMAP/ICLR handling
631
679
* is done by hypervisor calls on sun4v platforms, not by direct
···
682
734
orig_sp = set_hardirq_stack();
683
735
684
736
while (bucket_pa) {
685
-
struct irq_desc *desc;
686
737
unsigned long next_pa;
687
738
unsigned int irq;
688
739
···
689
742
irq = bucket_get_irq(bucket_pa);
690
743
bucket_clear_chain_pa(bucket_pa);
691
744
692
-
desc = irq_desc + irq;
693
-
694
-
if (!(desc->status & IRQ_DISABLED))
695
-
desc->handle_irq(irq, desc);
745
+
generic_handle_irq(irq);
696
746
697
747
bucket_pa = next_pa;
698
748
}
···
732
788
unsigned int irq;
733
789
734
790
for (irq = 0; irq < NR_IRQS; irq++) {
791
+
struct irq_desc *desc = irq_to_desc(irq);
792
+
struct irq_data *data = irq_desc_get_irq_data(desc);
735
793
unsigned long flags;
736
794
737
-
raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
738
-
if (irq_desc[irq].action &&
739
-
!(irq_desc[irq].status & IRQ_PER_CPU)) {
740
-
struct irq_data *data = irq_get_irq_data(irq);
741
-
795
+
raw_spin_lock_irqsave(&desc->lock, flags);
796
+
if (desc->action && !irqd_is_per_cpu(data)) {
742
797
if (data->chip->irq_set_affinity)
743
798
data->chip->irq_set_affinity(data,
744
-
data->affinity,
745
-
false);
799
+
data->affinity,
800
+
false);
746
801
}
747
-
raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
802
+
raw_spin_unlock_irqrestore(&desc->lock, flags);
748
803
}
749
804
750
805
tick_ops->disable_irq();
···
981
1038
: "i" (PSTATE_IE)
982
1039
: "g1");
983
1040
984
-
irq_desc[0].action = &timer_irq_action;
1041
+
irq_to_desc(0)->action = &timer_irq_action;
985
1042
}
+1
-1
arch/sparc/kernel/pci.c
+1
-1
arch/sparc/kernel/pci.c
···
1012
1012
1013
1013
void arch_teardown_msi_irq(unsigned int irq)
1014
1014
{
1015
-
struct msi_desc *entry = get_irq_msi(irq);
1015
+
struct msi_desc *entry = irq_get_msi_desc(irq);
1016
1016
struct pci_dev *pdev = entry->dev;
1017
1017
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1018
1018
+6
-9
arch/sparc/kernel/pci_msi.c
+6
-9
arch/sparc/kernel/pci_msi.c
···
30
30
31
31
err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
32
32
if (likely(err > 0)) {
33
-
struct irq_desc *desc;
34
33
unsigned int irq;
35
34
36
35
irq = pbm->msi_irq_table[msi - pbm->msi_first];
37
-
desc = irq_desc + irq;
38
-
39
-
desc->handle_irq(irq, desc);
36
+
generic_handle_irq(irq);
40
37
}
41
38
42
39
if (unlikely(err < 0))
···
133
136
if (!*irq_p)
134
137
goto out_err;
135
138
136
-
set_irq_chip_and_handler_name(*irq_p, &msi_irq,
137
-
handle_simple_irq, "MSI");
139
+
irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
140
+
"MSI");
138
141
139
142
err = alloc_msi(pbm);
140
143
if (unlikely(err < 0))
···
160
163
}
161
164
msg.data = msi;
162
165
163
-
set_irq_msi(*irq_p, entry);
166
+
irq_set_msi_desc(*irq_p, entry);
164
167
write_msi_msg(*irq_p, &msg);
165
168
166
169
return 0;
···
169
172
free_msi(pbm, msi);
170
173
171
174
out_irq_free:
172
-
set_irq_chip(*irq_p, NULL);
175
+
irq_set_chip(*irq_p, NULL);
173
176
irq_free(*irq_p);
174
177
*irq_p = 0;
175
178
···
208
211
209
212
free_msi(pbm, msi_num);
210
213
211
-
set_irq_chip(irq, NULL);
214
+
irq_set_chip(irq, NULL);
212
215
irq_free(irq);
213
216
}
214
217
+1
arch/unicore32/Kconfig
+1
arch/unicore32/Kconfig
+8
-50
arch/unicore32/kernel/irq.c
+8
-50
arch/unicore32/kernel/irq.c
···
321
321
writel(1, INTC_ICCR);
322
322
323
323
for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
324
-
set_irq_chip(irq, &puv3_low_gpio_chip);
325
-
set_irq_handler(irq, handle_edge_irq);
324
+
irq_set_chip(irq, &puv3_low_gpio_chip);
325
+
irq_set_handler(irq, handle_edge_irq);
326
326
irq_modify_status(irq,
327
327
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
328
328
0);
329
329
}
330
330
331
331
for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
332
-
set_irq_chip(irq, &puv3_normal_chip);
333
-
set_irq_handler(irq, handle_level_irq);
332
+
irq_set_chip(irq, &puv3_normal_chip);
333
+
irq_set_handler(irq, handle_level_irq);
334
334
irq_modify_status(irq,
335
335
IRQ_NOREQUEST | IRQ_NOAUTOEN,
336
336
IRQ_NOPROBE);
337
337
}
338
338
339
339
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
340
-
set_irq_chip(irq, &puv3_high_gpio_chip);
341
-
set_irq_handler(irq, handle_edge_irq);
340
+
irq_set_chip(irq, &puv3_high_gpio_chip);
341
+
irq_set_handler(irq, handle_edge_irq);
342
342
irq_modify_status(irq,
343
343
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
344
344
0);
···
347
347
/*
348
348
* Install handler for GPIO 0-27 edge detect interrupts
349
349
*/
350
-
set_irq_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
351
-
set_irq_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
350
+
irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
351
+
irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
352
352
353
353
#ifdef CONFIG_PUV3_GPIO
354
354
puv3_init_gpio();
355
355
#endif
356
-
}
357
-
358
-
int show_interrupts(struct seq_file *p, void *v)
359
-
{
360
-
int i = *(loff_t *) v, cpu;
361
-
struct irq_desc *desc;
362
-
struct irqaction *action;
363
-
unsigned long flags;
364
-
365
-
if (i == 0) {
366
-
char cpuname[12];
367
-
368
-
seq_printf(p, " ");
369
-
for_each_present_cpu(cpu) {
370
-
sprintf(cpuname, "CPU%d", cpu);
371
-
seq_printf(p, " %10s", cpuname);
372
-
}
373
-
seq_putc(p, '\n');
374
-
}
375
-
376
-
if (i < nr_irqs) {
377
-
desc = irq_to_desc(i);
378
-
raw_spin_lock_irqsave(&desc->lock, flags);
379
-
action = desc->action;
380
-
if (!action)
381
-
goto unlock;
382
-
383
-
seq_printf(p, "%3d: ", i);
384
-
for_each_present_cpu(cpu)
385
-
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
386
-
seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
387
-
seq_printf(p, " %s", action->name);
388
-
for (action = action->next; action; action = action->next)
389
-
seq_printf(p, ", %s", action->name);
390
-
391
-
seq_putc(p, '\n');
392
-
unlock:
393
-
raw_spin_unlock_irqrestore(&desc->lock, flags);
394
-
} else if (i == nr_irqs) {
395
-
seq_printf(p, "Error in interrupt!\n");
396
-
}
397
-
return 0;
398
356
}
399
357
400
358
/*
+1
-1
drivers/ata/pata_ixp4xx_cf.c
+1
-1
drivers/ata/pata_ixp4xx_cf.c
+2
-2
drivers/ata/pata_rb532_cf.c
+2
-2
drivers/ata/pata_rb532_cf.c
···
60
60
struct rb532_cf_info *info = ah->private_data;
61
61
62
62
if (gpio_get_value(info->gpio_line)) {
63
-
set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
63
+
irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
64
64
ata_sff_interrupt(info->irq, dev_instance);
65
65
} else {
66
-
set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
66
+
irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
67
67
}
68
68
69
69
return IRQ_HANDLED;
+1
-1
drivers/gpio/Kconfig
+1
-1
drivers/gpio/Kconfig
+1
-1
drivers/hwmon/gpio-fan.c
+1
-1
drivers/hwmon/gpio-fan.c
···
116
116
return 0;
117
117
118
118
INIT_WORK(&fan_data->alarm_work, fan_alarm_notify);
119
-
set_irq_type(alarm_irq, IRQ_TYPE_EDGE_BOTH);
119
+
irq_set_irq_type(alarm_irq, IRQ_TYPE_EDGE_BOTH);
120
120
err = request_irq(alarm_irq, fan_alarm_irq_handler, IRQF_SHARED,
121
121
"GPIO fan alarm", fan_data);
122
122
if (err)
+2
-2
drivers/input/keyboard/lm8323.c
+2
-2
drivers/input/keyboard/lm8323.c
···
809
809
struct lm8323_chip *lm = i2c_get_clientdata(client);
810
810
int i;
811
811
812
-
set_irq_wake(client->irq, 0);
812
+
irq_set_irq_wake(client->irq, 0);
813
813
disable_irq(client->irq);
814
814
815
815
mutex_lock(&lm->lock);
···
838
838
led_classdev_resume(&lm->pwm[i].cdev);
839
839
840
840
enable_irq(client->irq);
841
-
set_irq_wake(client->irq, 1);
841
+
irq_set_irq_wake(client->irq, 1);
842
842
843
843
return 0;
844
844
}
+1
-1
drivers/input/serio/ams_delta_serio.c
+1
-1
drivers/input/serio/ams_delta_serio.c
···
149
149
* at FIQ level, switch back from edge to simple interrupt handler
150
150
* to avoid bad interaction.
151
151
*/
152
-
set_irq_handler(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK),
152
+
irq_set_handler(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK),
153
153
handle_simple_irq);
154
154
155
155
serio_register_port(ams_delta_serio);
+1
-1
drivers/input/touchscreen/mainstone-wm97xx.c
+1
-1
drivers/input/touchscreen/mainstone-wm97xx.c
+1
-1
drivers/input/touchscreen/zylonite-wm97xx.c
+1
-1
drivers/input/touchscreen/zylonite-wm97xx.c
···
193
193
gpio_touch_irq = mfp_to_gpio(MFP_PIN_GPIO26);
194
194
195
195
wm->pen_irq = IRQ_GPIO(gpio_touch_irq);
196
-
set_irq_type(IRQ_GPIO(gpio_touch_irq), IRQ_TYPE_EDGE_BOTH);
196
+
irq_set_irq_type(IRQ_GPIO(gpio_touch_irq), IRQ_TYPE_EDGE_BOTH);
197
197
198
198
wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN,
199
199
WM97XX_GPIO_POL_HIGH,
+1
-1
drivers/misc/sgi-gru/grufile.c
+1
-1
drivers/misc/sgi-gru/grufile.c
···
373
373
374
374
if (gru_irq_count[chiplet] == 0) {
375
375
gru_chip[chiplet].name = irq_name;
376
-
ret = set_irq_chip(irq, &gru_chip[chiplet]);
376
+
ret = irq_set_chip(irq, &gru_chip[chiplet]);
377
377
if (ret) {
378
378
printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
379
379
GRU_DRIVER_ID_STR, -ret);
+1
-1
drivers/mmc/host/sdhci-spear.c
+1
-1
drivers/mmc/host/sdhci-spear.c
···
50
50
/* val == 1 -> card removed, val == 0 -> card inserted */
51
51
/* if card removed - set irq for low level, else vice versa */
52
52
gpio_irq_type = val ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH;
53
-
set_irq_type(irq, gpio_irq_type);
53
+
irq_set_irq_type(irq, gpio_irq_type);
54
54
55
55
if (sdhci->data->card_power_gpio >= 0) {
56
56
if (!sdhci->data->power_always_enb) {
+4
-4
drivers/net/dm9000.c
+4
-4
drivers/net/dm9000.c
···
621
621
/* change in wol state, update IRQ state */
622
622
623
623
if (!dm->wake_state)
624
-
set_irq_wake(dm->irq_wake, 1);
624
+
irq_set_irq_wake(dm->irq_wake, 1);
625
625
else if (dm->wake_state & !opts)
626
-
set_irq_wake(dm->irq_wake, 0);
626
+
irq_set_irq_wake(dm->irq_wake, 0);
627
627
}
628
628
629
629
dm->wake_state = opts;
···
1424
1424
} else {
1425
1425
1426
1426
/* test to see if irq is really wakeup capable */
1427
-
ret = set_irq_wake(db->irq_wake, 1);
1427
+
ret = irq_set_irq_wake(db->irq_wake, 1);
1428
1428
if (ret) {
1429
1429
dev_err(db->dev, "irq %d cannot set wakeup (%d)\n",
1430
1430
db->irq_wake, ret);
1431
1431
ret = 0;
1432
1432
} else {
1433
-
set_irq_wake(db->irq_wake, 0);
1433
+
irq_set_irq_wake(db->irq_wake, 0);
1434
1434
db->wake_supported = 1;
1435
1435
}
1436
1436
}
+1
-2
drivers/net/wireless/p54/p54spi.c
+1
-2
drivers/net/wireless/p54/p54spi.c
+1
-1
drivers/net/wireless/wl1251/sdio.c
+1
-1
drivers/net/wireless/wl1251/sdio.c
+1
-1
drivers/net/wireless/wl1251/spi.c
+1
-1
drivers/net/wireless/wl1251/spi.c
+1
-1
drivers/parisc/eisa.c
+1
-1
drivers/parisc/eisa.c
+2
-2
drivers/parisc/gsc.c
+2
-2
drivers/parisc/gsc.c
···
152
152
if (irq > GSC_IRQ_MAX)
153
153
return NO_IRQ;
154
154
155
-
set_irq_chip_and_handler(irq, type, handle_simple_irq);
156
-
set_irq_chip_data(irq, data);
155
+
irq_set_chip_and_handler(irq, type, handle_simple_irq);
156
+
irq_set_chip_data(irq, data);
157
157
158
158
return irq++;
159
159
}
+2
-1
drivers/parisc/superio.c
+2
-1
drivers/parisc/superio.c
+6
-6
drivers/pci/dmar.c
+6
-6
drivers/pci/dmar.c
···
1226
1226
1227
1227
void dmar_msi_unmask(struct irq_data *data)
1228
1228
{
1229
-
struct intel_iommu *iommu = irq_data_get_irq_data(data);
1229
+
struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1230
1230
unsigned long flag;
1231
1231
1232
1232
/* unmask it */
···
1240
1240
void dmar_msi_mask(struct irq_data *data)
1241
1241
{
1242
1242
unsigned long flag;
1243
-
struct intel_iommu *iommu = irq_data_get_irq_data(data);
1243
+
struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1244
1244
1245
1245
/* mask it */
1246
1246
spin_lock_irqsave(&iommu->register_lock, flag);
···
1252
1252
1253
1253
void dmar_msi_write(int irq, struct msi_msg *msg)
1254
1254
{
1255
-
struct intel_iommu *iommu = get_irq_data(irq);
1255
+
struct intel_iommu *iommu = irq_get_handler_data(irq);
1256
1256
unsigned long flag;
1257
1257
1258
1258
spin_lock_irqsave(&iommu->register_lock, flag);
···
1264
1264
1265
1265
void dmar_msi_read(int irq, struct msi_msg *msg)
1266
1266
{
1267
-
struct intel_iommu *iommu = get_irq_data(irq);
1267
+
struct intel_iommu *iommu = irq_get_handler_data(irq);
1268
1268
unsigned long flag;
1269
1269
1270
1270
spin_lock_irqsave(&iommu->register_lock, flag);
···
1382
1382
return -EINVAL;
1383
1383
}
1384
1384
1385
-
set_irq_data(irq, iommu);
1385
+
irq_set_handler_data(irq, iommu);
1386
1386
iommu->irq = irq;
1387
1387
1388
1388
ret = arch_setup_dmar_msi(irq);
1389
1389
if (ret) {
1390
-
set_irq_data(irq, NULL);
1390
+
irq_set_handler_data(irq, NULL);
1391
1391
iommu->irq = 0;
1392
1392
destroy_irq(irq);
1393
1393
return ret;
+8
-8
drivers/pci/htirq.c
+8
-8
drivers/pci/htirq.c
···
34
34
35
35
void write_ht_irq_msg(unsigned int irq, struct ht_irq_msg *msg)
36
36
{
37
-
struct ht_irq_cfg *cfg = get_irq_data(irq);
37
+
struct ht_irq_cfg *cfg = irq_get_handler_data(irq);
38
38
unsigned long flags;
39
39
spin_lock_irqsave(&ht_irq_lock, flags);
40
40
if (cfg->msg.address_lo != msg->address_lo) {
···
53
53
54
54
void fetch_ht_irq_msg(unsigned int irq, struct ht_irq_msg *msg)
55
55
{
56
-
struct ht_irq_cfg *cfg = get_irq_data(irq);
56
+
struct ht_irq_cfg *cfg = irq_get_handler_data(irq);
57
57
*msg = cfg->msg;
58
58
}
59
59
60
60
void mask_ht_irq(struct irq_data *data)
61
61
{
62
-
struct ht_irq_cfg *cfg = irq_data_get_irq_data(data);
62
+
struct ht_irq_cfg *cfg = irq_data_get_irq_handler_data(data);
63
63
struct ht_irq_msg msg = cfg->msg;
64
64
65
65
msg.address_lo |= 1;
···
68
68
69
69
void unmask_ht_irq(struct irq_data *data)
70
70
{
71
-
struct ht_irq_cfg *cfg = irq_data_get_irq_data(data);
71
+
struct ht_irq_cfg *cfg = irq_data_get_irq_handler_data(data);
72
72
struct ht_irq_msg msg = cfg->msg;
73
73
74
74
msg.address_lo &= ~1;
···
126
126
kfree(cfg);
127
127
return -EBUSY;
128
128
}
129
-
set_irq_data(irq, cfg);
129
+
irq_set_handler_data(irq, cfg);
130
130
131
131
if (arch_setup_ht_irq(irq, dev) < 0) {
132
132
ht_destroy_irq(irq);
···
162
162
{
163
163
struct ht_irq_cfg *cfg;
164
164
165
-
cfg = get_irq_data(irq);
166
-
set_irq_chip(irq, NULL);
167
-
set_irq_data(irq, NULL);
165
+
cfg = irq_get_handler_data(irq);
166
+
irq_set_chip(irq, NULL);
167
+
irq_set_handler_data(irq, NULL);
168
168
destroy_irq(irq);
169
169
170
170
kfree(cfg);
+1
-1
drivers/pci/intel-iommu.c
+1
-1
drivers/pci/intel-iommu.c
+1
-1
drivers/pci/intr_remapping.c
+1
-1
drivers/pci/intr_remapping.c
+5
-5
drivers/pci/msi.c
+5
-5
drivers/pci/msi.c
···
236
236
237
237
void read_msi_msg(unsigned int irq, struct msi_msg *msg)
238
238
{
239
-
struct msi_desc *entry = get_irq_msi(irq);
239
+
struct msi_desc *entry = irq_get_msi_desc(irq);
240
240
241
241
__read_msi_msg(entry, msg);
242
242
}
···
253
253
254
254
void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
255
255
{
256
-
struct msi_desc *entry = get_irq_msi(irq);
256
+
struct msi_desc *entry = irq_get_msi_desc(irq);
257
257
258
258
__get_cached_msi_msg(entry, msg);
259
259
}
···
297
297
298
298
void write_msi_msg(unsigned int irq, struct msi_msg *msg)
299
299
{
300
-
struct msi_desc *entry = get_irq_msi(irq);
300
+
struct msi_desc *entry = irq_get_msi_desc(irq);
301
301
302
302
__write_msi_msg(entry, msg);
303
303
}
···
354
354
if (!dev->msi_enabled)
355
355
return;
356
356
357
-
entry = get_irq_msi(dev->irq);
357
+
entry = irq_get_msi_desc(dev->irq);
358
358
pos = entry->msi_attrib.pos;
359
359
360
360
pci_intx_for_msi(dev, 0);
···
519
519
PCI_MSIX_ENTRY_VECTOR_CTRL;
520
520
521
521
entries[i].vector = entry->irq;
522
-
set_irq_msi(entry->irq, entry);
522
+
irq_set_msi_desc(entry->irq, entry);
523
523
entry->masked = readl(entry->mask_base + offset);
524
524
msix_mask_irq(entry, 1);
525
525
i++;
+1
-1
drivers/pcmcia/bfin_cf_pcmcia.c
+1
-1
drivers/pcmcia/bfin_cf_pcmcia.c
+1
-1
drivers/pcmcia/db1xxx_ss.c
+1
-1
drivers/pcmcia/db1xxx_ss.c
···
181
181
/* all other (older) Db1x00 boards use a GPIO to show
182
182
* card detection status: use both-edge triggers.
183
183
*/
184
-
set_irq_type(sock->insert_irq, IRQ_TYPE_EDGE_BOTH);
184
+
irq_set_irq_type(sock->insert_irq, IRQ_TYPE_EDGE_BOTH);
185
185
ret = request_irq(sock->insert_irq, db1000_pcmcia_cdirq,
186
186
0, "pcmcia_carddetect", sock);
187
187
+1
-1
drivers/pcmcia/sa1100_nanoengine.c
+1
-1
drivers/pcmcia/sa1100_nanoengine.c
···
86
86
GPDR &= ~nano_skts[i].input_pins;
87
87
GPDR |= nano_skts[i].output_pins;
88
88
GPCR = nano_skts[i].clear_outputs;
89
-
set_irq_type(nano_skts[i].transition_pins, IRQ_TYPE_EDGE_BOTH);
89
+
irq_set_irq_type(nano_skts[i].transition_pins, IRQ_TYPE_EDGE_BOTH);
90
90
skt->socket.pci_irq = nano_skts[i].pci_irq;
91
91
92
92
return soc_pcmcia_request_irqs(skt,
+7
-7
drivers/pcmcia/soc_common.c
+7
-7
drivers/pcmcia/soc_common.c
···
155
155
*/
156
156
if (skt->irq_state != 1 && state->io_irq) {
157
157
skt->irq_state = 1;
158
-
set_irq_type(skt->socket.pci_irq,
159
-
IRQ_TYPE_EDGE_FALLING);
158
+
irq_set_irq_type(skt->socket.pci_irq,
159
+
IRQ_TYPE_EDGE_FALLING);
160
160
} else if (skt->irq_state == 1 && state->io_irq == 0) {
161
161
skt->irq_state = 0;
162
-
set_irq_type(skt->socket.pci_irq, IRQ_TYPE_NONE);
162
+
irq_set_irq_type(skt->socket.pci_irq, IRQ_TYPE_NONE);
163
163
}
164
164
165
165
skt->cs_state = *state;
···
537
537
IRQF_DISABLED, irqs[i].str, skt);
538
538
if (res)
539
539
break;
540
-
set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
540
+
irq_set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
541
541
}
542
542
543
543
if (res) {
···
570
570
571
571
for (i = 0; i < nr; i++)
572
572
if (irqs[i].sock == skt->nr)
573
-
set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
573
+
irq_set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
574
574
}
575
575
EXPORT_SYMBOL(soc_pcmcia_disable_irqs);
576
576
···
581
581
582
582
for (i = 0; i < nr; i++)
583
583
if (irqs[i].sock == skt->nr) {
584
-
set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_RISING);
585
-
set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_BOTH);
584
+
irq_set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_RISING);
585
+
irq_set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_BOTH);
586
586
}
587
587
}
588
588
EXPORT_SYMBOL(soc_pcmcia_enable_irqs);
+1
-1
drivers/pcmcia/xxs1500_ss.c
+1
-1
drivers/pcmcia/xxs1500_ss.c
···
274
274
* edge detector.
275
275
*/
276
276
irq = gpio_to_irq(GPIO_CDA);
277
-
set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
277
+
irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
278
278
ret = request_irq(irq, cdirq, 0, "pcmcia_carddetect", sock);
279
279
if (ret) {
280
280
dev_err(&pdev->dev, "cannot setup cd irq\n");
+5
-3
drivers/platform/x86/intel_pmic_gpio.c
+5
-3
drivers/platform/x86/intel_pmic_gpio.c
···
257
257
}
258
258
259
259
for (i = 0; i < 8; i++) {
260
-
set_irq_chip_and_handler_name(i + pg->irq_base, &pmic_irqchip,
261
-
handle_simple_irq, "demux");
262
-
set_irq_chip_data(i + pg->irq_base, pg);
260
+
irq_set_chip_and_handler_name(i + pg->irq_base,
261
+
&pmic_irqchip,
262
+
handle_simple_irq,
263
+
"demux");
264
+
irq_set_chip_data(i + pg->irq_base, pg);
263
265
}
264
266
return 0;
265
267
err:
+2
-2
drivers/power/z2_battery.c
+2
-2
drivers/power/z2_battery.c
···
215
215
if (ret)
216
216
goto err2;
217
217
218
-
set_irq_type(gpio_to_irq(info->charge_gpio),
219
-
IRQ_TYPE_EDGE_BOTH);
218
+
irq_set_irq_type(gpio_to_irq(info->charge_gpio),
219
+
IRQ_TYPE_EDGE_BOTH);
220
220
ret = request_irq(gpio_to_irq(info->charge_gpio),
221
221
z2_charge_switch_irq, IRQF_DISABLED,
222
222
"AC Detect", charger);
+3
-3
drivers/rtc/rtc-sh.c
+3
-3
drivers/rtc/rtc-sh.c
···
782
782
struct platform_device *pdev = to_platform_device(dev);
783
783
struct sh_rtc *rtc = platform_get_drvdata(pdev);
784
784
785
-
set_irq_wake(rtc->periodic_irq, enabled);
785
+
irq_set_irq_wake(rtc->periodic_irq, enabled);
786
786
787
787
if (rtc->carry_irq > 0) {
788
-
set_irq_wake(rtc->carry_irq, enabled);
789
-
set_irq_wake(rtc->alarm_irq, enabled);
788
+
irq_set_irq_wake(rtc->carry_irq, enabled);
789
+
irq_set_irq_wake(rtc->alarm_irq, enabled);
790
790
}
791
791
}
792
792
+9
-14
drivers/sh/intc/core.c
+9
-14
drivers/sh/intc/core.c
···
63
63
64
64
static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
65
65
{
66
-
generic_handle_irq((unsigned int)get_irq_data(irq));
66
+
generic_handle_irq((unsigned int)irq_get_handler_data(irq));
67
67
}
68
68
69
69
static void __init intc_register_irq(struct intc_desc *desc,
···
116
116
irq_data = irq_get_irq_data(irq);
117
117
118
118
disable_irq_nosync(irq);
119
-
set_irq_chip_and_handler_name(irq, &d->chip,
120
-
handle_level_irq, "level");
121
-
set_irq_chip_data(irq, (void *)data[primary]);
119
+
irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
120
+
"level");
121
+
irq_set_chip_data(irq, (void *)data[primary]);
122
122
123
123
/*
124
124
* set priority level
···
340
340
vect2->enum_id = 0;
341
341
342
342
/* redirect this interrupts to the first one */
343
-
set_irq_chip(irq2, &dummy_irq_chip);
344
-
set_irq_chained_handler(irq2, intc_redirect_irq);
345
-
set_irq_data(irq2, (void *)irq);
343
+
irq_set_chip(irq2, &dummy_irq_chip);
344
+
irq_set_chained_handler(irq2, intc_redirect_irq);
345
+
irq_set_handler_data(irq2, (void *)irq);
346
346
}
347
347
}
348
348
···
387
387
/* enable wakeup irqs belonging to this intc controller */
388
388
for_each_active_irq(irq) {
389
389
struct irq_data *data;
390
-
struct irq_desc *desc;
391
390
struct irq_chip *chip;
392
391
393
392
data = irq_get_irq_data(irq);
394
393
chip = irq_data_get_irq_chip(data);
395
394
if (chip != &d->chip)
396
395
continue;
397
-
desc = irq_to_desc(irq);
398
-
if ((desc->status & IRQ_WAKEUP))
396
+
if (irqd_is_wakeup_set(data))
399
397
chip->irq_enable(data);
400
398
}
401
399
}
402
-
403
400
return 0;
404
401
}
405
402
···
409
412
410
413
for_each_active_irq(irq) {
411
414
struct irq_data *data;
412
-
struct irq_desc *desc;
413
415
struct irq_chip *chip;
414
416
415
417
data = irq_get_irq_data(irq);
···
419
423
*/
420
424
if (chip != &d->chip)
421
425
continue;
422
-
desc = irq_to_desc(irq);
423
-
if (desc->status & IRQ_DISABLED)
426
+
if (irqd_irq_disabled(data))
424
427
chip->irq_disable(data);
425
428
else
426
429
chip->irq_enable(data);
+6
-6
drivers/sh/intc/virq.c
+6
-6
drivers/sh/intc/virq.c
···
110
110
{
111
111
struct irq_data *data = irq_get_irq_data(irq);
112
112
struct irq_chip *chip = irq_data_get_irq_chip(data);
113
-
struct intc_virq_list *entry, *vlist = irq_data_get_irq_data(data);
113
+
struct intc_virq_list *entry, *vlist = irq_data_get_irq_handler_data(data);
114
114
struct intc_desc_int *d = get_intc_desc(irq);
115
115
116
116
chip->irq_mask_ack(data);
···
118
118
for_each_virq(entry, vlist) {
119
119
unsigned long addr, handle;
120
120
121
-
handle = (unsigned long)get_irq_data(entry->irq);
121
+
handle = (unsigned long)irq_get_handler_data(entry->irq);
122
122
addr = INTC_REG(d, _INTC_ADDR_E(handle), 0);
123
123
124
124
if (intc_reg_fns[_INTC_FN(handle)](addr, handle, 0))
···
229
229
230
230
intc_irq_xlate_set(irq, entry->enum_id, d);
231
231
232
-
set_irq_chip_and_handler_name(irq, get_irq_chip(entry->pirq),
232
+
irq_set_chip_and_handler_name(irq, irq_get_chip(entry->pirq),
233
233
handle_simple_irq, "virq");
234
-
set_irq_chip_data(irq, get_irq_chip_data(entry->pirq));
234
+
irq_set_chip_data(irq, irq_get_chip_data(entry->pirq));
235
235
236
-
set_irq_data(irq, (void *)entry->handle);
236
+
irq_set_handler_data(irq, (void *)entry->handle);
237
237
238
-
set_irq_chained_handler(entry->pirq, intc_virq_handler);
238
+
irq_set_chained_handler(entry->pirq, intc_virq_handler);
239
239
add_virq_to_pirq(entry->pirq, irq);
240
240
241
241
radix_tree_tag_clear(&d->tree, entry->enum_id,
+2
-2
drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
+2
-2
drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
···
341
341
if (error)
342
342
return -ENODEV;
343
343
344
-
set_irq_wake(sdhcinfo->oob_irq, 1);
344
+
irq_set_irq_wake(sdhcinfo->oob_irq, 1);
345
345
sdhcinfo->oob_irq_registered = true;
346
346
}
347
347
···
352
352
{
353
353
SDLX_MSG(("%s: Enter\n", __func__));
354
354
355
-
set_irq_wake(sdhcinfo->oob_irq, 0);
355
+
irq_set_irq_wake(sdhcinfo->oob_irq, 0);
356
356
disable_irq(sdhcinfo->oob_irq); /* just in case.. */
357
357
free_irq(sdhcinfo->oob_irq, NULL);
358
358
sdhcinfo->oob_irq_registered = false;
+1
-1
drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
+1
-1
drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
+1
-1
drivers/tty/hvc/hvc_xen.c
+1
-1
drivers/tty/hvc/hvc_xen.c
+2
-2
drivers/tty/serial/msm_serial_hs.c
+2
-2
drivers/tty/serial/msm_serial_hs.c
···
1644
1644
if (unlikely(uport->irq < 0))
1645
1645
return -ENXIO;
1646
1646
1647
-
if (unlikely(set_irq_wake(uport->irq, 1)))
1647
+
if (unlikely(irq_set_irq_wake(uport->irq, 1)))
1648
1648
return -ENXIO;
1649
1649
1650
1650
if (pdata == NULL || pdata->rx_wakeup_irq < 0)
···
1658
1658
if (unlikely(msm_uport->rx_wakeup.irq < 0))
1659
1659
return -ENXIO;
1660
1660
1661
-
if (unlikely(set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
1661
+
if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
1662
1662
return -ENXIO;
1663
1663
}
1664
1664
+1
-1
drivers/usb/host/oxu210hp-hcd.c
+1
-1
drivers/usb/host/oxu210hp-hcd.c
+1
-1
drivers/usb/musb/tusb6010.c
+1
-1
drivers/usb/musb/tusb6010.c
···
943
943
musb_writel(tbase, TUSB_INT_CTRL_CONF,
944
944
TUSB_INT_CTRL_CONF_INT_RELCYC(0));
945
945
946
-
set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
946
+
irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
947
947
948
948
/* maybe force into the Default-A OTG state machine */
949
949
if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
+2
-2
drivers/w1/masters/ds1wm.c
+2
-2
drivers/w1/masters/ds1wm.c
···
368
368
ds1wm_data->active_high = plat->active_high;
369
369
370
370
if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
371
-
set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
371
+
irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
372
372
if (res->flags & IORESOURCE_IRQ_LOWEDGE)
373
-
set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
373
+
irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
374
374
375
375
ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
376
376
"ds1wm", ds1wm_data);
+13
-13
drivers/xen/events.c
+13
-13
drivers/xen/events.c
···
122
122
/* Get info for IRQ */
123
123
static struct irq_info *info_for_irq(unsigned irq)
124
124
{
125
-
return get_irq_data(irq);
125
+
return irq_get_handler_data(irq);
126
126
}
127
127
128
128
/* Constructors for packed IRQ information. */
···
403
403
404
404
info->type = IRQT_UNBOUND;
405
405
406
-
set_irq_data(irq, info);
406
+
irq_set_handler_data(irq, info);
407
407
408
408
list_add_tail(&info->list, &xen_irq_list_head);
409
409
}
···
458
458
459
459
static void xen_free_irq(unsigned irq)
460
460
{
461
-
struct irq_info *info = get_irq_data(irq);
461
+
struct irq_info *info = irq_get_handler_data(irq);
462
462
463
463
list_del(&info->list);
464
464
465
-
set_irq_data(irq, NULL);
465
+
irq_set_handler_data(irq, NULL);
466
466
467
467
kfree(info);
468
468
···
585
585
{
586
586
int evtchn = evtchn_from_irq(data->irq);
587
587
588
-
move_native_irq(data->irq);
588
+
irq_move_irq(data);
589
589
590
590
if (VALID_EVTCHN(evtchn)) {
591
591
mask_evtchn(evtchn);
···
639
639
if (irq < 0)
640
640
goto out;
641
641
642
-
set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
643
-
handle_level_irq, name);
642
+
irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
643
+
name);
644
644
645
645
irq_op.irq = irq;
646
646
irq_op.vector = 0;
···
690
690
if (irq == -1)
691
691
goto out;
692
692
693
-
set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
694
-
handle_level_irq, name);
693
+
irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
694
+
name);
695
695
696
696
xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0);
697
697
ret = irq_set_msi_desc(irq, msidesc);
···
772
772
if (irq == -1)
773
773
goto out;
774
774
775
-
set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
775
+
irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
776
776
handle_fasteoi_irq, "event");
777
777
778
778
xen_irq_info_evtchn_init(irq, evtchn);
···
799
799
if (irq < 0)
800
800
goto out;
801
801
802
-
set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
802
+
irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
803
803
handle_percpu_irq, "ipi");
804
804
805
805
bind_ipi.vcpu = cpu;
···
848
848
if (irq == -1)
849
849
goto out;
850
850
851
-
set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
851
+
irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
852
852
handle_percpu_irq, "virq");
853
853
854
854
bind_virq.virq = virq;
···
1339
1339
{
1340
1340
int evtchn = evtchn_from_irq(data->irq);
1341
1341
1342
-
move_masked_irq(data->irq);
1342
+
irq_move_masked_irq(data);
1343
1343
1344
1344
if (VALID_EVTCHN(evtchn))
1345
1345
unmask_evtchn(evtchn);
-121
include/linux/irq.h
-121
include/linux/irq.h
···
92
92
IRQ_NO_BALANCING = (1 << 13),
93
93
IRQ_MOVE_PCNTXT = (1 << 14),
94
94
IRQ_NESTED_THREAD = (1 << 15),
95
-
96
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
97
-
IRQ_INPROGRESS = (1 << 16),
98
-
IRQ_REPLAY = (1 << 17),
99
-
IRQ_WAITING = (1 << 18),
100
-
IRQ_DISABLED = (1 << 19),
101
-
IRQ_PENDING = (1 << 20),
102
-
IRQ_MASKED = (1 << 21),
103
-
IRQ_MOVE_PENDING = (1 << 22),
104
-
IRQ_AFFINITY_SET = (1 << 23),
105
-
IRQ_WAKEUP = (1 << 24),
106
-
#endif
107
95
};
108
96
109
97
#define IRQF_MODIFY_MASK \
···
309
321
*/
310
322
struct irq_chip {
311
323
const char *name;
312
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
313
-
unsigned int (*startup)(unsigned int irq);
314
-
void (*shutdown)(unsigned int irq);
315
-
void (*enable)(unsigned int irq);
316
-
void (*disable)(unsigned int irq);
317
-
318
-
void (*ack)(unsigned int irq);
319
-
void (*mask)(unsigned int irq);
320
-
void (*mask_ack)(unsigned int irq);
321
-
void (*unmask)(unsigned int irq);
322
-
void (*eoi)(unsigned int irq);
323
-
324
-
void (*end)(unsigned int irq);
325
-
int (*set_affinity)(unsigned int irq,
326
-
const struct cpumask *dest);
327
-
int (*retrigger)(unsigned int irq);
328
-
int (*set_type)(unsigned int irq, unsigned int flow_type);
329
-
int (*set_wake)(unsigned int irq, unsigned int on);
330
-
331
-
void (*bus_lock)(unsigned int irq);
332
-
void (*bus_sync_unlock)(unsigned int irq);
333
-
#endif
334
324
unsigned int (*irq_startup)(struct irq_data *data);
335
325
void (*irq_shutdown)(struct irq_data *data);
336
326
void (*irq_enable)(struct irq_data *data);
···
386
420
#ifdef CONFIG_GENERIC_HARDIRQS
387
421
388
422
#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
389
-
void move_native_irq(int irq);
390
-
void move_masked_irq(int irq);
391
423
void irq_move_irq(struct irq_data *data);
392
424
void irq_move_masked_irq(struct irq_data *data);
393
425
#else
394
-
static inline void move_native_irq(int irq) { }
395
-
static inline void move_masked_irq(int irq) { }
396
426
static inline void irq_move_irq(struct irq_data *data) { }
397
427
static inline void irq_move_masked_irq(struct irq_data *data) { }
398
428
#endif
···
550
588
{
551
589
return d->msi_desc;
552
590
}
553
-
554
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
555
-
/* Please do not use: Use the replacement functions instead */
556
-
static inline int set_irq_chip(unsigned int irq, struct irq_chip *chip)
557
-
{
558
-
return irq_set_chip(irq, chip);
559
-
}
560
-
static inline int set_irq_data(unsigned int irq, void *data)
561
-
{
562
-
return irq_set_handler_data(irq, data);
563
-
}
564
-
static inline int set_irq_chip_data(unsigned int irq, void *data)
565
-
{
566
-
return irq_set_chip_data(irq, data);
567
-
}
568
-
static inline int set_irq_type(unsigned int irq, unsigned int type)
569
-
{
570
-
return irq_set_irq_type(irq, type);
571
-
}
572
-
static inline int set_irq_msi(unsigned int irq, struct msi_desc *entry)
573
-
{
574
-
return irq_set_msi_desc(irq, entry);
575
-
}
576
-
static inline struct irq_chip *get_irq_chip(unsigned int irq)
577
-
{
578
-
return irq_get_chip(irq);
579
-
}
580
-
static inline void *get_irq_chip_data(unsigned int irq)
581
-
{
582
-
return irq_get_chip_data(irq);
583
-
}
584
-
static inline void *get_irq_data(unsigned int irq)
585
-
{
586
-
return irq_get_handler_data(irq);
587
-
}
588
-
static inline void *irq_data_get_irq_data(struct irq_data *d)
589
-
{
590
-
return irq_data_get_irq_handler_data(d);
591
-
}
592
-
static inline struct msi_desc *get_irq_msi(unsigned int irq)
593
-
{
594
-
return irq_get_msi_desc(irq);
595
-
}
596
-
static inline void set_irq_noprobe(unsigned int irq)
597
-
{
598
-
irq_set_noprobe(irq);
599
-
}
600
-
static inline void set_irq_probe(unsigned int irq)
601
-
{
602
-
irq_set_probe(irq);
603
-
}
604
-
static inline void set_irq_nested_thread(unsigned int irq, int nest)
605
-
{
606
-
irq_set_nested_thread(irq, nest);
607
-
}
608
-
static inline void
609
-
set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
610
-
irq_flow_handler_t handle, const char *name)
611
-
{
612
-
irq_set_chip_and_handler_name(irq, chip, handle, name);
613
-
}
614
-
static inline void
615
-
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
616
-
irq_flow_handler_t handle)
617
-
{
618
-
irq_set_chip_and_handler(irq, chip, handle);
619
-
}
620
-
static inline void
621
-
__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
622
-
const char *name)
623
-
{
624
-
__irq_set_handler(irq, handle, is_chained, name);
625
-
}
626
-
static inline void set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
627
-
{
628
-
irq_set_handler(irq, handle);
629
-
}
630
-
static inline void
631
-
set_irq_chained_handler(unsigned int irq, irq_flow_handler_t handle)
632
-
{
633
-
irq_set_chained_handler(irq, handle);
634
-
}
635
-
#endif
636
591
637
592
int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node);
638
593
void irq_free_descs(unsigned int irq, unsigned int cnt);
+1
-59
include/linux/irqdesc.h
+1
-59
include/linux/irqdesc.h
···
35
35
* @name: flow handler name for /proc/interrupts output
36
36
*/
37
37
struct irq_desc {
38
-
39
-
#ifdef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
40
38
struct irq_data irq_data;
41
-
#else
42
-
/*
43
-
* This union will go away, once we fixed the direct access to
44
-
* irq_desc all over the place. The direct fields are a 1:1
45
-
* overlay of irq_data.
46
-
*/
47
-
union {
48
-
struct irq_data irq_data;
49
-
struct {
50
-
unsigned int irq;
51
-
unsigned int node;
52
-
unsigned int pad_do_not_even_think_about_it;
53
-
struct irq_chip *chip;
54
-
void *handler_data;
55
-
void *chip_data;
56
-
struct msi_desc *msi_desc;
57
-
#ifdef CONFIG_SMP
58
-
cpumask_var_t affinity;
59
-
#endif
60
-
};
61
-
};
62
-
#endif
63
-
64
39
struct timer_rand_state *timer_rand_state;
65
40
unsigned int __percpu *kstat_irqs;
66
41
irq_flow_handler_t handle_irq;
···
43
68
irq_preflow_handler_t preflow_handler;
44
69
#endif
45
70
struct irqaction *action; /* IRQ action list */
46
-
#ifdef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
47
71
unsigned int status_use_accessors;
48
-
#else
49
-
unsigned int status; /* IRQ status */
50
-
#endif
51
72
unsigned int core_internal_state__do_not_mess_with_it;
52
73
unsigned int depth; /* nested irq disables */
53
74
unsigned int wake_depth; /* nested wake enables */
···
98
127
return desc->irq_data.msi_desc;
99
128
}
100
129
101
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
102
-
static inline struct irq_chip *get_irq_desc_chip(struct irq_desc *desc)
103
-
{
104
-
return irq_desc_get_chip(desc);
105
-
}
106
-
static inline void *get_irq_desc_data(struct irq_desc *desc)
107
-
{
108
-
return irq_desc_get_handler_data(desc);
109
-
}
110
-
111
-
static inline void *get_irq_desc_chip_data(struct irq_desc *desc)
112
-
{
113
-
return irq_desc_get_chip_data(desc);
114
-
}
115
-
116
-
static inline struct msi_desc *get_irq_desc_msi(struct irq_desc *desc)
117
-
{
118
-
return irq_desc_get_msi_desc(desc);
119
-
}
120
-
#endif
121
-
122
130
/*
123
131
* Architectures call this to let the generic IRQ layer
124
132
* handle an interrupt. If the descriptor is attached to an
···
144
194
desc->name = name;
145
195
}
146
196
147
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
148
-
static inline void __set_irq_handler_unlocked(int irq,
149
-
irq_flow_handler_t handler)
150
-
{
151
-
__irq_set_handler_locked(irq, handler);
152
-
}
153
-
154
197
static inline int irq_balancing_disabled(unsigned int irq)
155
198
{
156
199
struct irq_desc *desc;
157
200
158
201
desc = irq_to_desc(irq);
159
-
return desc->status & IRQ_NO_BALANCING_MASK;
202
+
return desc->status_use_accessors & IRQ_NO_BALANCING_MASK;
160
203
}
161
-
#endif
162
204
163
205
static inline void
164
206
irq_set_lockdep_class(unsigned int irq, struct lock_class_key *class)
-4
kernel/irq/Kconfig
-4
kernel/irq/Kconfig
+1
-3
kernel/irq/autoprobe.c
+1
-3
kernel/irq/autoprobe.c
···
70
70
raw_spin_lock_irq(&desc->lock);
71
71
if (!desc->action && irq_settings_can_probe(desc)) {
72
72
desc->istate |= IRQS_AUTODETECT | IRQS_WAITING;
73
-
if (irq_startup(desc)) {
74
-
irq_compat_set_pending(desc);
73
+
if (irq_startup(desc))
75
74
desc->istate |= IRQS_PENDING;
76
-
}
77
75
}
78
76
raw_spin_unlock_irq(&desc->lock);
79
77
}
-129
kernel/irq/chip.c
-129
kernel/irq/chip.c
···
34
34
if (!chip)
35
35
chip = &no_irq_chip;
36
36
37
-
irq_chip_set_defaults(chip);
38
37
desc->irq_data.chip = chip;
39
38
irq_put_desc_unlock(desc, flags);
40
39
/*
···
140
141
static void irq_state_clr_disabled(struct irq_desc *desc)
141
142
{
142
143
irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
143
-
irq_compat_clr_disabled(desc);
144
144
}
145
145
146
146
static void irq_state_set_disabled(struct irq_desc *desc)
147
147
{
148
148
irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
149
-
irq_compat_set_disabled(desc);
150
149
}
151
150
152
151
static void irq_state_clr_masked(struct irq_desc *desc)
153
152
{
154
153
irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
155
-
irq_compat_clr_masked(desc);
156
154
}
157
155
158
156
static void irq_state_set_masked(struct irq_desc *desc)
159
157
{
160
158
irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
161
-
irq_compat_set_masked(desc);
162
159
}
163
160
164
161
int irq_startup(struct irq_desc *desc)
···
202
207
desc->irq_data.chip->irq_disable(&desc->irq_data);
203
208
irq_state_set_masked(desc);
204
209
}
205
-
}
206
-
207
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
208
-
/* Temporary migration helpers */
209
-
static void compat_irq_mask(struct irq_data *data)
210
-
{
211
-
data->chip->mask(data->irq);
212
-
}
213
-
214
-
static void compat_irq_unmask(struct irq_data *data)
215
-
{
216
-
data->chip->unmask(data->irq);
217
-
}
218
-
219
-
static void compat_irq_ack(struct irq_data *data)
220
-
{
221
-
data->chip->ack(data->irq);
222
-
}
223
-
224
-
static void compat_irq_mask_ack(struct irq_data *data)
225
-
{
226
-
data->chip->mask_ack(data->irq);
227
-
}
228
-
229
-
static void compat_irq_eoi(struct irq_data *data)
230
-
{
231
-
data->chip->eoi(data->irq);
232
-
}
233
-
234
-
static void compat_irq_enable(struct irq_data *data)
235
-
{
236
-
data->chip->enable(data->irq);
237
-
}
238
-
239
-
static void compat_irq_disable(struct irq_data *data)
240
-
{
241
-
data->chip->disable(data->irq);
242
-
}
243
-
244
-
static void compat_irq_shutdown(struct irq_data *data)
245
-
{
246
-
data->chip->shutdown(data->irq);
247
-
}
248
-
249
-
static unsigned int compat_irq_startup(struct irq_data *data)
250
-
{
251
-
return data->chip->startup(data->irq);
252
-
}
253
-
254
-
static int compat_irq_set_affinity(struct irq_data *data,
255
-
const struct cpumask *dest, bool force)
256
-
{
257
-
return data->chip->set_affinity(data->irq, dest);
258
-
}
259
-
260
-
static int compat_irq_set_type(struct irq_data *data, unsigned int type)
261
-
{
262
-
return data->chip->set_type(data->irq, type);
263
-
}
264
-
265
-
static int compat_irq_set_wake(struct irq_data *data, unsigned int on)
266
-
{
267
-
return data->chip->set_wake(data->irq, on);
268
-
}
269
-
270
-
static int compat_irq_retrigger(struct irq_data *data)
271
-
{
272
-
return data->chip->retrigger(data->irq);
273
-
}
274
-
275
-
static void compat_bus_lock(struct irq_data *data)
276
-
{
277
-
data->chip->bus_lock(data->irq);
278
-
}
279
-
280
-
static void compat_bus_sync_unlock(struct irq_data *data)
281
-
{
282
-
data->chip->bus_sync_unlock(data->irq);
283
-
}
284
-
#endif
285
-
286
-
/*
287
-
* Fixup enable/disable function pointers
288
-
*/
289
-
void irq_chip_set_defaults(struct irq_chip *chip)
290
-
{
291
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
292
-
if (chip->enable)
293
-
chip->irq_enable = compat_irq_enable;
294
-
if (chip->disable)
295
-
chip->irq_disable = compat_irq_disable;
296
-
if (chip->shutdown)
297
-
chip->irq_shutdown = compat_irq_shutdown;
298
-
if (chip->startup)
299
-
chip->irq_startup = compat_irq_startup;
300
-
if (!chip->end)
301
-
chip->end = dummy_irq_chip.end;
302
-
if (chip->bus_lock)
303
-
chip->irq_bus_lock = compat_bus_lock;
304
-
if (chip->bus_sync_unlock)
305
-
chip->irq_bus_sync_unlock = compat_bus_sync_unlock;
306
-
if (chip->mask)
307
-
chip->irq_mask = compat_irq_mask;
308
-
if (chip->unmask)
309
-
chip->irq_unmask = compat_irq_unmask;
310
-
if (chip->ack)
311
-
chip->irq_ack = compat_irq_ack;
312
-
if (chip->mask_ack)
313
-
chip->irq_mask_ack = compat_irq_mask_ack;
314
-
if (chip->eoi)
315
-
chip->irq_eoi = compat_irq_eoi;
316
-
if (chip->set_affinity)
317
-
chip->irq_set_affinity = compat_irq_set_affinity;
318
-
if (chip->set_type)
319
-
chip->irq_set_type = compat_irq_set_type;
320
-
if (chip->set_wake)
321
-
chip->irq_set_wake = compat_irq_set_wake;
322
-
if (chip->retrigger)
323
-
chip->irq_retrigger = compat_irq_retrigger;
324
-
#endif
325
210
}
326
211
327
212
static inline void mask_ack_irq(struct irq_desc *desc)
···
256
381
if (unlikely(!action || irqd_irq_disabled(&desc->irq_data)))
257
382
goto out_unlock;
258
383
259
-
irq_compat_set_progress(desc);
260
384
irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
261
385
raw_spin_unlock_irq(&desc->lock);
262
386
···
265
391
266
392
raw_spin_lock_irq(&desc->lock);
267
393
irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
268
-
irq_compat_clr_progress(desc);
269
394
270
395
out_unlock:
271
396
raw_spin_unlock_irq(&desc->lock);
···
387
514
* then mask it and get out of here:
388
515
*/
389
516
if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
390
-
irq_compat_set_pending(desc);
391
517
desc->istate |= IRQS_PENDING;
392
518
mask_irq(desc);
393
519
goto out;
···
439
567
if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
440
568
irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
441
569
if (!irq_check_poll(desc)) {
442
-
irq_compat_set_pending(desc);
443
570
desc->istate |= IRQS_PENDING;
444
571
mask_ack_irq(desc);
445
572
goto out_unlock;
-72
kernel/irq/compat.h
-72
kernel/irq/compat.h
···
1
-
/*
2
-
* Compat layer for transition period
3
-
*/
4
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
5
-
static inline void irq_compat_set_progress(struct irq_desc *desc)
6
-
{
7
-
desc->status |= IRQ_INPROGRESS;
8
-
}
9
-
10
-
static inline void irq_compat_clr_progress(struct irq_desc *desc)
11
-
{
12
-
desc->status &= ~IRQ_INPROGRESS;
13
-
}
14
-
static inline void irq_compat_set_disabled(struct irq_desc *desc)
15
-
{
16
-
desc->status |= IRQ_DISABLED;
17
-
}
18
-
static inline void irq_compat_clr_disabled(struct irq_desc *desc)
19
-
{
20
-
desc->status &= ~IRQ_DISABLED;
21
-
}
22
-
static inline void irq_compat_set_pending(struct irq_desc *desc)
23
-
{
24
-
desc->status |= IRQ_PENDING;
25
-
}
26
-
27
-
static inline void irq_compat_clr_pending(struct irq_desc *desc)
28
-
{
29
-
desc->status &= ~IRQ_PENDING;
30
-
}
31
-
static inline void irq_compat_set_masked(struct irq_desc *desc)
32
-
{
33
-
desc->status |= IRQ_MASKED;
34
-
}
35
-
36
-
static inline void irq_compat_clr_masked(struct irq_desc *desc)
37
-
{
38
-
desc->status &= ~IRQ_MASKED;
39
-
}
40
-
static inline void irq_compat_set_move_pending(struct irq_desc *desc)
41
-
{
42
-
desc->status |= IRQ_MOVE_PENDING;
43
-
}
44
-
45
-
static inline void irq_compat_clr_move_pending(struct irq_desc *desc)
46
-
{
47
-
desc->status &= ~IRQ_MOVE_PENDING;
48
-
}
49
-
static inline void irq_compat_set_affinity(struct irq_desc *desc)
50
-
{
51
-
desc->status |= IRQ_AFFINITY_SET;
52
-
}
53
-
54
-
static inline void irq_compat_clr_affinity(struct irq_desc *desc)
55
-
{
56
-
desc->status &= ~IRQ_AFFINITY_SET;
57
-
}
58
-
#else
59
-
static inline void irq_compat_set_progress(struct irq_desc *desc) { }
60
-
static inline void irq_compat_clr_progress(struct irq_desc *desc) { }
61
-
static inline void irq_compat_set_disabled(struct irq_desc *desc) { }
62
-
static inline void irq_compat_clr_disabled(struct irq_desc *desc) { }
63
-
static inline void irq_compat_set_pending(struct irq_desc *desc) { }
64
-
static inline void irq_compat_clr_pending(struct irq_desc *desc) { }
65
-
static inline void irq_compat_set_masked(struct irq_desc *desc) { }
66
-
static inline void irq_compat_clr_masked(struct irq_desc *desc) { }
67
-
static inline void irq_compat_set_move_pending(struct irq_desc *desc) { }
68
-
static inline void irq_compat_clr_move_pending(struct irq_desc *desc) { }
69
-
static inline void irq_compat_set_affinity(struct irq_desc *desc) { }
70
-
static inline void irq_compat_clr_affinity(struct irq_desc *desc) { }
71
-
#endif
72
-
+1
-1
kernel/irq/debug.h
+1
-1
kernel/irq/debug.h
···
4
4
5
5
#include <linux/kallsyms.h>
6
6
7
-
#define P(f) if (desc->status & f) printk("%14s set\n", #f)
7
+
#define P(f) if (desc->status_use_accessors & f) printk("%14s set\n", #f)
8
8
#define PS(f) if (desc->istate & f) printk("%14s set\n", #f)
9
9
/* FIXME */
10
10
#define PD(f) do { } while (0)
-9
kernel/irq/dummychip.c
-9
kernel/irq/dummychip.c
···
31
31
return 0;
32
32
}
33
33
34
-
#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
35
-
static void compat_noop(unsigned int irq) { }
36
-
#define END_INIT .end = compat_noop
37
-
#else
38
-
#define END_INIT
39
-
#endif
40
-
41
34
/*
42
35
* Generic no controller implementation
43
36
*/
···
41
48
.irq_enable = noop,
42
49
.irq_disable = noop,
43
50
.irq_ack = ack_bad,
44
-
END_INIT
45
51
};
46
52
47
53
/*
···
56
64
.irq_ack = noop,
57
65
.irq_mask = noop,
58
66
.irq_unmask = noop,
59
-
END_INIT
60
67
};
-3
kernel/irq/handle.c
-3
kernel/irq/handle.c
···
175
175
struct irqaction *action = desc->action;
176
176
irqreturn_t ret;
177
177
178
-
irq_compat_clr_pending(desc);
179
178
desc->istate &= ~IRQS_PENDING;
180
-
irq_compat_set_progress(desc);
181
179
irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
182
180
raw_spin_unlock(&desc->lock);
183
181
···
183
185
184
186
raw_spin_lock(&desc->lock);
185
187
irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
186
-
irq_compat_clr_progress(desc);
187
188
return ret;
188
189
}
-10
kernel/irq/internals.h
-10
kernel/irq/internals.h
···
15
15
16
16
#define istate core_internal_state__do_not_mess_with_it
17
17
18
-
#ifdef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
19
-
# define status status_use_accessors
20
-
#endif
21
-
22
18
extern int noirqdebug;
23
19
24
20
/*
···
57
61
IRQS_SUSPENDED = 0x00000800,
58
62
};
59
63
60
-
#include "compat.h"
61
64
#include "debug.h"
62
65
#include "settings.h"
63
66
64
67
#define irq_data_to_desc(data) container_of(data, struct irq_desc, irq_data)
65
-
66
-
/* Set default functions for irq_chip structures: */
67
-
extern void irq_chip_set_defaults(struct irq_chip *chip);
68
68
69
69
extern int __irq_set_trigger(struct irq_desc *desc, unsigned int irq,
70
70
unsigned long flags);
···
148
156
static inline void irqd_set_move_pending(struct irq_data *d)
149
157
{
150
158
d->state_use_accessors |= IRQD_SETAFFINITY_PENDING;
151
-
irq_compat_set_move_pending(irq_data_to_desc(d));
152
159
}
153
160
154
161
static inline void irqd_clr_move_pending(struct irq_data *d)
155
162
{
156
163
d->state_use_accessors &= ~IRQD_SETAFFINITY_PENDING;
157
-
irq_compat_clr_move_pending(irq_data_to_desc(d));
158
164
}
159
165
160
166
static inline void irqd_clear(struct irq_data *d, unsigned int mask)
+2
-10
kernel/irq/manage.c
+2
-10
kernel/irq/manage.c
···
132
132
}
133
133
#else
134
134
static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; }
135
-
static inline bool irq_move_pending(struct irq_desc *data) { return false; }
135
+
static inline bool irq_move_pending(struct irq_data *data) { return false; }
136
136
static inline void
137
137
irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { }
138
138
static inline void
···
166
166
kref_get(&desc->affinity_notify->kref);
167
167
schedule_work(&desc->affinity_notify->work);
168
168
}
169
-
irq_compat_set_affinity(desc);
170
169
irqd_set(data, IRQD_AFFINITY_SET);
171
170
172
171
return ret;
···
296
297
if (cpumask_intersects(desc->irq_data.affinity,
297
298
cpu_online_mask))
298
299
set = desc->irq_data.affinity;
299
-
else {
300
-
irq_compat_clr_affinity(desc);
300
+
else
301
301
irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET);
302
-
}
303
302
}
304
303
305
304
cpumask_and(mask, cpu_online_mask, set);
···
584
587
irqd_set(&desc->irq_data, IRQD_LEVEL);
585
588
}
586
589
587
-
if (chip != desc->irq_data.chip)
588
-
irq_chip_set_defaults(desc->irq_data.chip);
589
590
ret = 0;
590
591
break;
591
592
default:
···
780
785
* but AFAICT IRQS_PENDING should be fine as it
781
786
* retriggers the interrupt itself --- tglx
782
787
*/
783
-
irq_compat_set_pending(desc);
784
788
desc->istate |= IRQS_PENDING;
785
789
raw_spin_unlock_irq(&desc->lock);
786
790
} else {
···
975
981
new->thread_mask = 1 << ffz(thread_mask);
976
982
977
983
if (!shared) {
978
-
irq_chip_set_defaults(desc->irq_data.chip);
979
-
980
984
init_waitqueue_head(&desc->wait_for_threads);
981
985
982
986
/* Setup the type (level, edge polarity) if configured: */
-10
kernel/irq/migration.c
-10
kernel/irq/migration.c
···
53
53
cpumask_clear(desc->pending_mask);
54
54
}
55
55
56
-
void move_masked_irq(int irq)
57
-
{
58
-
irq_move_masked_irq(irq_get_irq_data(irq));
59
-
}
60
-
61
56
void irq_move_irq(struct irq_data *idata)
62
57
{
63
58
bool masked;
···
74
79
irq_move_masked_irq(idata);
75
80
if (!masked)
76
81
idata->chip->irq_unmask(idata);
77
-
}
78
-
79
-
void move_native_irq(int irq)
80
-
{
81
-
irq_move_irq(irq_get_irq_data(irq));
82
82
}
+6
-2
kernel/irq/proc.c
+6
-2
kernel/irq/proc.c
···
364
364
return 0;
365
365
}
366
366
367
+
#ifndef ACTUAL_NR_IRQS
368
+
# define ACTUAL_NR_IRQS nr_irqs
369
+
#endif
370
+
367
371
int show_interrupts(struct seq_file *p, void *v)
368
372
{
369
373
static int prec;
···
377
373
struct irqaction *action;
378
374
struct irq_desc *desc;
379
375
380
-
if (i > nr_irqs)
376
+
if (i > ACTUAL_NR_IRQS)
381
377
return 0;
382
378
383
-
if (i == nr_irqs)
379
+
if (i == ACTUAL_NR_IRQS)
384
380
return arch_show_interrupts(p, prec);
385
381
386
382
/* print header and calculate the width of the first column */
-1
kernel/irq/resend.c
-1
kernel/irq/resend.c
+21
-34
kernel/irq/settings.h
+21
-34
kernel/irq/settings.h
···
15
15
_IRQF_MODIFY_MASK = IRQF_MODIFY_MASK,
16
16
};
17
17
18
-
#define IRQ_INPROGRESS GOT_YOU_MORON
19
-
#define IRQ_REPLAY GOT_YOU_MORON
20
-
#define IRQ_WAITING GOT_YOU_MORON
21
-
#define IRQ_DISABLED GOT_YOU_MORON
22
-
#define IRQ_PENDING GOT_YOU_MORON
23
-
#define IRQ_MASKED GOT_YOU_MORON
24
-
#define IRQ_WAKEUP GOT_YOU_MORON
25
-
#define IRQ_MOVE_PENDING GOT_YOU_MORON
26
18
#define IRQ_PER_CPU GOT_YOU_MORON
27
19
#define IRQ_NO_BALANCING GOT_YOU_MORON
28
-
#define IRQ_AFFINITY_SET GOT_YOU_MORON
29
20
#define IRQ_LEVEL GOT_YOU_MORON
30
21
#define IRQ_NOPROBE GOT_YOU_MORON
31
22
#define IRQ_NOREQUEST GOT_YOU_MORON
···
28
37
static inline void
29
38
irq_settings_clr_and_set(struct irq_desc *desc, u32 clr, u32 set)
30
39
{
31
-
desc->status &= ~(clr & _IRQF_MODIFY_MASK);
32
-
desc->status |= (set & _IRQF_MODIFY_MASK);
40
+
desc->status_use_accessors &= ~(clr & _IRQF_MODIFY_MASK);
41
+
desc->status_use_accessors |= (set & _IRQF_MODIFY_MASK);
33
42
}
34
43
35
44
static inline bool irq_settings_is_per_cpu(struct irq_desc *desc)
36
45
{
37
-
return desc->status & _IRQ_PER_CPU;
46
+
return desc->status_use_accessors & _IRQ_PER_CPU;
38
47
}
39
48
40
49
static inline void irq_settings_set_per_cpu(struct irq_desc *desc)
41
50
{
42
-
desc->status |= _IRQ_PER_CPU;
51
+
desc->status_use_accessors |= _IRQ_PER_CPU;
43
52
}
44
53
45
54
static inline void irq_settings_set_no_balancing(struct irq_desc *desc)
46
55
{
47
-
desc->status |= _IRQ_NO_BALANCING;
56
+
desc->status_use_accessors |= _IRQ_NO_BALANCING;
48
57
}
49
58
50
59
static inline bool irq_settings_has_no_balance_set(struct irq_desc *desc)
51
60
{
52
-
return desc->status & _IRQ_NO_BALANCING;
61
+
return desc->status_use_accessors & _IRQ_NO_BALANCING;
53
62
}
54
63
55
64
static inline u32 irq_settings_get_trigger_mask(struct irq_desc *desc)
56
65
{
57
-
return desc->status & IRQ_TYPE_SENSE_MASK;
66
+
return desc->status_use_accessors & IRQ_TYPE_SENSE_MASK;
58
67
}
59
68
60
69
static inline void
61
70
irq_settings_set_trigger_mask(struct irq_desc *desc, u32 mask)
62
71
{
63
-
desc->status &= ~IRQ_TYPE_SENSE_MASK;
64
-
desc->status |= mask & IRQ_TYPE_SENSE_MASK;
72
+
desc->status_use_accessors &= ~IRQ_TYPE_SENSE_MASK;
73
+
desc->status_use_accessors |= mask & IRQ_TYPE_SENSE_MASK;
65
74
}
66
75
67
76
static inline bool irq_settings_is_level(struct irq_desc *desc)
68
77
{
69
-
return desc->status & _IRQ_LEVEL;
78
+
return desc->status_use_accessors & _IRQ_LEVEL;
70
79
}
71
80
72
81
static inline void irq_settings_clr_level(struct irq_desc *desc)
73
82
{
74
-
desc->status &= ~_IRQ_LEVEL;
83
+
desc->status_use_accessors &= ~_IRQ_LEVEL;
75
84
}
76
85
77
86
static inline void irq_settings_set_level(struct irq_desc *desc)
78
87
{
79
-
desc->status |= _IRQ_LEVEL;
88
+
desc->status_use_accessors |= _IRQ_LEVEL;
80
89
}
81
90
82
91
static inline bool irq_settings_can_request(struct irq_desc *desc)
83
92
{
84
-
return !(desc->status & _IRQ_NOREQUEST);
93
+
return !(desc->status_use_accessors & _IRQ_NOREQUEST);
85
94
}
86
95
87
96
static inline void irq_settings_clr_norequest(struct irq_desc *desc)
88
97
{
89
-
desc->status &= ~_IRQ_NOREQUEST;
98
+
desc->status_use_accessors &= ~_IRQ_NOREQUEST;
90
99
}
91
100
92
101
static inline void irq_settings_set_norequest(struct irq_desc *desc)
93
102
{
94
-
desc->status |= _IRQ_NOREQUEST;
103
+
desc->status_use_accessors |= _IRQ_NOREQUEST;
95
104
}
96
105
97
106
static inline bool irq_settings_can_probe(struct irq_desc *desc)
98
107
{
99
-
return !(desc->status & _IRQ_NOPROBE);
108
+
return !(desc->status_use_accessors & _IRQ_NOPROBE);
100
109
}
101
110
102
111
static inline void irq_settings_clr_noprobe(struct irq_desc *desc)
103
112
{
104
-
desc->status &= ~_IRQ_NOPROBE;
113
+
desc->status_use_accessors &= ~_IRQ_NOPROBE;
105
114
}
106
115
107
116
static inline void irq_settings_set_noprobe(struct irq_desc *desc)
108
117
{
109
-
desc->status |= _IRQ_NOPROBE;
118
+
desc->status_use_accessors |= _IRQ_NOPROBE;
110
119
}
111
120
112
121
static inline bool irq_settings_can_move_pcntxt(struct irq_desc *desc)
113
122
{
114
-
return desc->status & _IRQ_MOVE_PCNTXT;
123
+
return desc->status_use_accessors & _IRQ_MOVE_PCNTXT;
115
124
}
116
125
117
126
static inline bool irq_settings_can_autoenable(struct irq_desc *desc)
118
127
{
119
-
return !(desc->status & _IRQ_NOAUTOEN);
128
+
return !(desc->status_use_accessors & _IRQ_NOAUTOEN);
120
129
}
121
130
122
131
static inline bool irq_settings_is_nested_thread(struct irq_desc *desc)
123
132
{
124
-
return desc->status & _IRQ_NESTED_THREAD;
133
+
return desc->status_use_accessors & _IRQ_NESTED_THREAD;
125
134
}
126
-
127
-
/* Nothing should touch desc->status from now on */
128
-
#undef status
129
-
#define status USE_THE_PROPER_WRAPPERS_YOU_MORON