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cxl/pci: cxl_dport_map_rch_aer() cleanup

cxl_dport_map_ras() is used to map CXL RAS capability, the RCH AER
capability should not be mapped in the function but should mapped in
cxl_dport_init_ras_reporting(). Moving cxl_dport_map_ras() out of
cxl_dport_map_ras() and into cxl_dport_init_ras_reporting().

In cxl_dport_init_ras_reporting(), the AER capability position in RCRB
will be located but the position is only used in
cxl_dport_map_rch_aer(), getting the position in cxl_dport_map_rch_aer()
rather than cxl_dport_init_ras_reporting() is more reasonable and makes
the code clearer.

Besides, some local variables in cxl_dport_map_rch_aer() are
unnecessary, remove them to make the function more concise.

Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240830061308.2327065-2-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Li Ming and committed by
Dave Jiang c8706cc1 577a6766

+14 -21
+14 -21
drivers/cxl/core/pci.c
··· 772 772 773 773 static void cxl_dport_map_rch_aer(struct cxl_dport *dport) 774 774 { 775 - struct cxl_rcrb_info *ri = &dport->rcrb; 776 - void __iomem *dport_aer = NULL; 777 775 resource_size_t aer_phys; 778 776 struct device *host; 777 + u16 aer_cap; 779 778 780 - if (dport->rch && ri->aer_cap) { 779 + aer_cap = cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); 780 + if (aer_cap) { 781 781 host = dport->reg_map.host; 782 - aer_phys = ri->aer_cap + ri->base; 783 - dport_aer = devm_cxl_iomap_block(host, aer_phys, 784 - sizeof(struct aer_capability_regs)); 782 + aer_phys = aer_cap + dport->rcrb.base; 783 + dport->regs.dport_aer = devm_cxl_iomap_block(host, aer_phys, 784 + sizeof(struct aer_capability_regs)); 785 785 } 786 - 787 - dport->regs.dport_aer = dport_aer; 788 786 } 789 787 790 788 static void cxl_dport_map_ras(struct cxl_dport *dport) ··· 795 797 else if (cxl_map_component_regs(map, &dport->regs.component, 796 798 BIT(CXL_CM_CAP_CAP_ID_RAS))) 797 799 dev_dbg(dev, "Failed to map RAS capability.\n"); 798 - 799 - if (dport->rch) 800 - cxl_dport_map_rch_aer(dport); 801 800 } 802 801 803 802 static void cxl_disable_rch_root_ints(struct cxl_dport *dport) ··· 833 838 */ 834 839 void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) 835 840 { 836 - struct device *dport_dev = dport->dport_dev; 837 - 838 - if (dport->rch) { 839 - struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); 840 - 841 - if (host_bridge->native_aer) 842 - dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base); 843 - } 844 - 845 841 dport->reg_map.host = host; 846 842 cxl_dport_map_ras(dport); 847 843 848 - if (dport->rch) 844 + if (dport->rch) { 845 + struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev); 846 + 847 + if (!host_bridge->native_aer) 848 + return; 849 + 850 + cxl_dport_map_rch_aer(dport); 849 851 cxl_disable_rch_root_ints(dport); 852 + } 850 853 } 851 854 EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL); 852 855