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phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi

The current workaround to setup the TMDS character rate relies on the
unconventional usage of phy_set_bus_width().

Make use of the recently introduced HDMI PHY configuration API to
properly handle the setup. The workaround will be dropped as soon as
the switch has been completed on both ends.

Rename rk_hdptx_phy_verify_config() to rk_hdptx_phy_verify_dp_config()
and introduce the rk_hdptx_phy_verify_hdmi_config() helper to check the
HDMI parameters during phy_configure().

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-9-8cb1678e7663@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Cristian Ciocaltea and committed by
Vinod Koul c871a311 0edf9d2b

+47 -17
+47 -17
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
··· 394 394 395 395 int phy_id; 396 396 struct phy *phy; 397 + struct phy_configure_opts_hdmi hdmi_cfg; 397 398 struct clk_bulk_data *clks; 398 399 int nr_clks; 399 400 struct reset_control_bulk_data rsts[RST_MAX]; ··· 1413 1412 { 1414 1413 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1415 1414 enum phy_mode mode = phy_get_mode(phy); 1416 - unsigned long long rate; 1417 1415 int ret, lane; 1418 1416 1419 - /* 1420 - * FIXME: Temporary workaround to pass pixel_clk_rate 1421 - * from the HDMI bridge driver until phy_configure_opts_hdmi 1422 - * becomes available in the PHY API. 1423 - */ 1424 - rate = phy_get_bus_width(hdptx->phy) & 0xfffffff; 1425 - rate *= 100; 1417 + if (mode != PHY_MODE_DP) { 1418 + if (!hdptx->hdmi_cfg.tmds_char_rate) { 1419 + /* 1420 + * FIXME: Temporary workaround to setup TMDS char rate 1421 + * from the RK DW HDMI QP bridge driver. 1422 + * Will be removed as soon the switch to the HDMI PHY 1423 + * configuration API has been completed on both ends. 1424 + */ 1425 + hdptx->hdmi_cfg.tmds_char_rate = phy_get_bus_width(hdptx->phy) & 0xfffffff; 1426 + hdptx->hdmi_cfg.tmds_char_rate *= 100; 1427 + } 1426 1428 1427 - dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, rate); 1429 + dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, hdptx->hdmi_cfg.tmds_char_rate); 1430 + } 1428 1431 1429 - ret = rk_hdptx_phy_consumer_get(hdptx, rate); 1432 + ret = rk_hdptx_phy_consumer_get(hdptx, hdptx->hdmi_cfg.tmds_char_rate); 1430 1433 if (ret) 1431 1434 return ret; 1432 1435 ··· 1461 1456 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1462 1457 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1463 1458 1464 - ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); 1459 + ret = rk_hdptx_ropll_tmds_mode_config(hdptx, hdptx->hdmi_cfg.tmds_char_rate); 1465 1460 if (ret) 1466 1461 rk_hdptx_phy_consumer_put(hdptx, true); 1467 1462 } ··· 1476 1471 return rk_hdptx_phy_consumer_put(hdptx, false); 1477 1472 } 1478 1473 1479 - static int rk_hdptx_phy_verify_config(struct rk_hdptx_phy *hdptx, 1480 - struct phy_configure_opts_dp *dp) 1474 + static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, 1475 + struct phy_configure_opts_hdmi *hdmi) 1476 + { 1477 + int i; 1478 + 1479 + if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) 1480 + return -EINVAL; 1481 + 1482 + for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 1483 + if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate) 1484 + break; 1485 + 1486 + if (i == ARRAY_SIZE(ropll_tmds_cfg) && 1487 + !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) 1488 + return -EINVAL; 1489 + 1490 + return 0; 1491 + } 1492 + 1493 + static int rk_hdptx_phy_verify_dp_config(struct rk_hdptx_phy *hdptx, 1494 + struct phy_configure_opts_dp *dp) 1481 1495 { 1482 1496 int i; 1483 1497 ··· 1756 1732 enum phy_mode mode = phy_get_mode(phy); 1757 1733 int ret; 1758 1734 1759 - if (mode != PHY_MODE_DP) 1760 - return 0; 1735 + if (mode != PHY_MODE_DP) { 1736 + ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); 1737 + if (ret) 1738 + dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); 1739 + else 1740 + hdptx->hdmi_cfg = opts->hdmi; 1741 + return ret; 1742 + } 1761 1743 1762 - ret = rk_hdptx_phy_verify_config(hdptx, &opts->dp); 1744 + ret = rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); 1763 1745 if (ret) { 1764 - dev_err(hdptx->dev, "invalid params for phy configure\n"); 1746 + dev_err(hdptx->dev, "invalid dp params for phy configure\n"); 1765 1747 return ret; 1766 1748 } 1767 1749