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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dt-bindings: media: Add qcom,sm6150-camss
Add bindings for the Camera Subsystem on the SM6150 SoC
The SM6150 platform provides:
- 2 x VFE (version 170), each with 3 RDI
- 1 x VFE Lite (version 170), each with 4 RDI
- 2 x CSID (version 170)
- 1 x CSID Lite (version 170)
- 3 x CSIPHY (version 2.0.0)
- 1 x BPS (Bayer Processing Segment)
- 1 x ICP (Imaging Control Processor)
- 1 x IPE (Image Postprocessing Engine)
- 1 x JPEG Encoder/Decoder
- 1 x LRME (Low Resolution Motion Estimation)
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
authored by
Wenmeng Liu
and committed by
Hans Verkuil
c88c5441
77a2ff40
+439
+439
Documentation/devicetree/bindings/media/qcom,sm6150-camss.yaml
+439
Documentation/devicetree/bindings/media/qcom,sm6150-camss.yaml
···
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sm6150-camss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM6150 Camera Subsystem (CAMSS)
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maintainers:
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- Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
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description:
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This binding describes the camera subsystem hardware found on SM6150
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Qualcomm SoCs. It includes submodules such as CSIPHY (CSI Physical layer)
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and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol.
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The subsystem also integrates a set of real-time image processing engines
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and their associated configuration modules, as well as non-real-time engines.
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properties:
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compatible:
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const: qcom,sm6150-camss
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reg:
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items:
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- description: Registers for CSID 0
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- description: Registers for CSID 1
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- description: Registers for CSID Lite
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- description: Registers for CSIPHY 0
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- description: Registers for CSIPHY 1
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- description: Registers for CSIPHY 2
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- description: Registers for VFE 0
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- description: Registers for VFE 1
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- description: Registers for VFE Lite
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- description: Registers for BPS (Bayer Processing Segment)
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- description: Registers for CAMNOC
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- description: Registers for CPAS CDM
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- description: Registers for CPAS TOP
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- description: Registers for ICP (Imaging Control Processor) CSR (Control and Status Registers)
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- description: Registers for ICP QGIC (Qualcomm Generic Interrupt Controller)
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- description: Registers for ICP SIERRA ((A5 subsystem communication))
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- description: Registers for IPE (Image Postprocessing Engine) 0
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- description: Registers for JPEG DMA
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- description: Registers for JPEG ENC
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- description: Registers for LRME (Low Resolution Motion Estimation)
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reg-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid_lite
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: vfe0
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- const: vfe1
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- const: vfe_lite
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- const: bps
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- const: camnoc
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- const: cpas_cdm
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- const: cpas_top
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- const: icp_csr
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- const: icp_qgic
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- const: icp_sierra
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- const: ipe0
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- const: jpeg_dma
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- const: jpeg_enc
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- const: lrme
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clocks:
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maxItems: 33
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clock-names:
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items:
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- const: gcc_ahb
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- const: gcc_axi_hf
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- const: camnoc_axi
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- const: cpas_ahb
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: soc_ahb
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- const: vfe0
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- const: vfe0_axi
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- const: vfe0_cphy_rx
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- const: vfe0_csid
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- const: vfe1
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- const: vfe1_axi
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- const: vfe1_cphy_rx
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- const: vfe1_csid
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- const: vfe_lite
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- const: vfe_lite_cphy_rx
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- const: vfe_lite_csid
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- const: bps
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- const: bps_ahb
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- const: bps_axi
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- const: bps_areg
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- const: icp
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- const: ipe0
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- const: ipe0_ahb
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- const: ipe0_areg
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- const: ipe0_axi
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- const: jpeg
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- const: lrme
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interrupts:
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maxItems: 15
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interrupt-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid_lite
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: vfe0
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- const: vfe1
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- const: vfe_lite
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- const: camnoc
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- const: cdm
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- const: icp
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- const: jpeg_dma
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- const: jpeg_enc
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- const: lrme
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+
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interconnects:
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maxItems: 4
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interconnect-names:
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items:
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- const: ahb
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- const: hf_0
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- const: hf_1
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- const: sf_mnoc
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iommus:
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items:
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- description: Camera IFE 0 non-protected stream
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- description: Camera IFE 1 non-protected stream
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- description: Camera IFE 3 non-protected stream
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- description: Camera CDM non-protected stream
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- description: Camera LRME read non-protected stream
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- description: Camera IPE 0 read non-protected stream
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- description: Camera BPS read non-protected stream
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- description: Camera IPE 0 write non-protected stream
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- description: Camera BPS write non-protected stream
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- description: Camera LRME write non-protected stream
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- description: Camera JPEG read non-protected stream
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- description: Camera JPEG write non-protected stream
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- description: Camera ICP stream
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power-domains:
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items:
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- description:
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IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
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- description:
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IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
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- description:
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Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
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- description:
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Titan BPS - Bayer Processing Segment, Global Distributed Switch Controller.
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- description:
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IPE GDSC - Image Postprocessing Engine, Global Distributed Switch Controller.
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power-domain-names:
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items:
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- const: ife0
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- const: ife1
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- const: top
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- const: bps
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- const: ipe
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vdd-csiphy-1p2-supply:
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description:
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Phandle to a 1.2V regulator supply to CSI PHYs.
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vdd-csiphy-1p8-supply:
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description:
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Phandle to 1.8V regulator supply to CSI PHYs pll block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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patternProperties:
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"^port@[0-2]$":
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data from a CSIPHY.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- interconnects
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- interconnect-names
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- iommus
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- power-domains
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- power-domain-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,qcs615-camcc.h>
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#include <dt-bindings/clock/qcom,qcs615-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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camss: isp@acb3000 {
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compatible = "qcom,sm6150-camss";
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reg = <0x0 0x0acb3000 0x0 0x1000>,
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<0x0 0x0acba000 0x0 0x1000>,
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<0x0 0x0acc8000 0x0 0x1000>,
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<0x0 0x0ac65000 0x0 0x1000>,
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<0x0 0x0ac66000 0x0 0x1000>,
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<0x0 0x0ac67000 0x0 0x1000>,
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<0x0 0x0acaf000 0x0 0x4000>,
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<0x0 0x0acb6000 0x0 0x4000>,
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<0x0 0x0acc4000 0x0 0x4000>,
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<0x0 0x0ac6f000 0x0 0x3000>,
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<0x0 0x0ac42000 0x0 0x5000>,
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<0x0 0x0ac48000 0x0 0x1000>,
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<0x0 0x0ac40000 0x0 0x1000>,
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<0x0 0x0ac18000 0x0 0x3000>,
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<0x0 0x0ac00000 0x0 0x6000>,
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<0x0 0x0ac10000 0x0 0x8000>,
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<0x0 0x0ac87000 0x0 0x3000>,
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<0x0 0x0ac52000 0x0 0x4000>,
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<0x0 0x0ac4e000 0x0 0x4000>,
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<0x0 0x0ac6b000 0x0 0x0a00>;
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reg-names = "csid0",
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"csid1",
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"csid_lite",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"vfe0",
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"vfe1",
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"vfe_lite",
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"bps",
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"camnoc",
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"cpas_cdm",
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"cpas_top",
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"icp_csr",
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"icp_qgic",
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"icp_sierra",
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"ipe0",
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"jpeg_dma",
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"jpeg_enc",
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"lrme";
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clocks = <&gcc GCC_CAMERA_AHB_CLK>,
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<&gcc GCC_CAMERA_HF_AXI_CLK>,
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<&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&camcc CAM_CC_SOC_AHB_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_AXI_CLK>,
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<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_0_CSID_CLK>,
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<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_AXI_CLK>,
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<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_1_CSID_CLK>,
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<&camcc CAM_CC_IFE_LITE_CLK>,
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<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
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<&camcc CAM_CC_BPS_CLK>,
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<&camcc CAM_CC_BPS_AHB_CLK>,
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<&camcc CAM_CC_BPS_AXI_CLK>,
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<&camcc CAM_CC_BPS_AREG_CLK>,
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<&camcc CAM_CC_ICP_CLK>,
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<&camcc CAM_CC_IPE_0_CLK>,
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<&camcc CAM_CC_IPE_0_AHB_CLK>,
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<&camcc CAM_CC_IPE_0_AREG_CLK>,
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<&camcc CAM_CC_IPE_0_AXI_CLK>,
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<&camcc CAM_CC_JPEG_CLK>,
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<&camcc CAM_CC_LRME_CLK>;
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+
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clock-names = "gcc_ahb",
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"gcc_axi_hf",
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"camnoc_axi",
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"cpas_ahb",
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"csiphy0",
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"csiphy0_timer",
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"csiphy1",
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"csiphy1_timer",
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"csiphy2",
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"csiphy2_timer",
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"soc_ahb",
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"vfe0",
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"vfe0_axi",
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"vfe0_cphy_rx",
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"vfe0_csid",
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"vfe1",
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"vfe1_axi",
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"vfe1_cphy_rx",
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"vfe1_csid",
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"vfe_lite",
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"vfe_lite_cphy_rx",
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"vfe_lite_csid",
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"bps",
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"bps_ahb",
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"bps_axi",
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"bps_areg",
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"icp",
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"ipe0",
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"ipe0_ahb",
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"ipe0_areg",
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"ipe0_axi",
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"jpeg",
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"lrme";
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "ahb",
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"hf_0",
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"hf_1",
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"sf_mnoc";
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interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csid0",
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"csid1",
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"csid_lite",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"vfe0",
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"vfe1",
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"vfe_lite",
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"camnoc",
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"cdm",
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"icp",
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"jpeg_dma",
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"jpeg_enc",
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"lrme";
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+
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iommus = <&apps_smmu 0x0820 0x40>,
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<&apps_smmu 0x0840 0x00>,
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<&apps_smmu 0x0860 0x40>,
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<&apps_smmu 0x0c00 0x00>,
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<&apps_smmu 0x0cc0 0x00>,
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<&apps_smmu 0x0c80 0x00>,
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<&apps_smmu 0x0ca0 0x00>,
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<&apps_smmu 0x0d00 0x00>,
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<&apps_smmu 0x0d20 0x00>,
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<&apps_smmu 0x0d40 0x00>,
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<&apps_smmu 0x0d80 0x20>,
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<&apps_smmu 0x0da0 0x20>,
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<&apps_smmu 0x0de2 0x00>;
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power-domains = <&camcc IFE_0_GDSC>,
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<&camcc IFE_1_GDSC>,
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<&camcc TITAN_TOP_GDSC>,
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<&camcc BPS_GDSC>,
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<&camcc IPE_0_GDSC>;
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power-domain-names = "ife0",
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"ife1",
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"top",
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"bps",
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"ipe";
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vdd-csiphy-1p2-supply = <&vreg_l11a_1p2>;
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vdd-csiphy-1p8-supply = <&vreg_l12a_1p8>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csiphy_ep0: endpoint {
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data-lanes = <0 1>;
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remote-endpoint = <&sensor_ep>;
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};
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};
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};
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};
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};