Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: Add support for RZ/G2UL SoC
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.
This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Biju Das
and committed by
Geert Uytterhoeven
c8b08822
948f5924
+171
-1
+6
-1
drivers/clk/renesas/Kconfig
+6
-1
drivers/clk/renesas/Kconfig
···
33
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select CLK_R8A779A0 if ARCH_R8A779A0
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select CLK_R8A779F0 if ARCH_R8A779F0
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select CLK_R9A06G032 if ARCH_R9A06G032
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+
select CLK_R9A07G043 if ARCH_R9A07G043
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select CLK_R9A07G044 if ARCH_R9A07G044
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select CLK_R9A07G054 if ARCH_R9A07G054
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select CLK_SH73A0 if ARCH_SH73A0
···
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config CLK_R9A06G032
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bool "RZ/N1D clock support" if COMPILE_TEST
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+
config CLK_R9A07G043
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bool "RZ/G2UL clock support" if COMPILE_TEST
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select CLK_RZG2L
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+
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config CLK_R9A07G044
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bool "RZ/G2L clock support" if COMPILE_TEST
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select CLK_RZG2L
···
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This is a driver for R-Car USB2 clock selector
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config CLK_RZG2L
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-
bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
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+
bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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# Generic
+1
drivers/clk/renesas/Makefile
+1
drivers/clk/renesas/Makefile
···
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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+
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
+157
drivers/clk/renesas/r9a07g043-cpg.c
+157
drivers/clk/renesas/r9a07g043-cpg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
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+
* RZ/G2UL CPG driver
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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+
*/
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+
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+
#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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+
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#include <dt-bindings/clock/r9a07g043-cpg.h>
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+
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#include "rzg2l-cpg.h"
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+
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
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+
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/* External Input Clocks */
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CLK_EXTAL,
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+
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+
/* Internal Core Clocks */
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CLK_OSC_DIV1000,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV2_8,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_4_2,
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CLK_PLL5,
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CLK_PLL6,
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CLK_P1_DIV2,
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+
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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+
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/* Divider tables */
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static const struct clk_div_table dtable_1_8[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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+
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static const struct clk_div_table dtable_1_32[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{4, 32},
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{0, 0},
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};
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+
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static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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+
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/* Internal Core Clocks */
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DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
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DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
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DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
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+
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/* Core output clk */
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DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
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CLK_DIVIDER_HIWORD_MASK),
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DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
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dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
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DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
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DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2,
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DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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};
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+
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static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
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DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
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0x514, 0),
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DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
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0x518, 0),
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DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
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0x518, 1),
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DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
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0x52c, 0),
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DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
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0x52c, 1),
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DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
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0x584, 0),
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DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
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0x584, 1),
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DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
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0x584, 2),
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DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
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0x584, 3),
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DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
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+
0x584, 4),
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DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
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0x588, 0),
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DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
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0x588, 1),
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+
};
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+
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static struct rzg2l_reset r9a07g043_resets[] = {
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DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
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DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
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DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
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DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
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DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
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DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
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DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
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DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
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+
DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
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+
DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
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DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
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DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
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};
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+
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static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
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MOD_CLK_BASE + R9A07G043_IA55_CLK,
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MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
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};
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+
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const struct rzg2l_cpg_info r9a07g043_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a07g043_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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+
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+
/* Critical Module Clocks */
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.crit_mod_clks = r9a07g043_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
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+
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/* Module Clocks */
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.mod_clks = r9a07g043_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
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.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
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+
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/* Resets */
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.resets = r9a07g043_resets,
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.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
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+
};
+6
drivers/clk/renesas/rzg2l-cpg.c
+6
drivers/clk/renesas/rzg2l-cpg.c
···
945
945
}
946
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static const struct of_device_id rzg2l_cpg_match[] = {
948
+
#ifdef CONFIG_CLK_R9A07G043
949
+
{
950
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.compatible = "renesas,r9a07g043-cpg",
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.data = &r9a07g043_cpg_info,
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+
},
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#endif
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#ifdef CONFIG_CLK_R9A07G044
949
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{
950
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.compatible = "renesas,r9a07g044-cpg",