tjh.dev / kernel
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dmaengine: jz4780: Replace uint32_t with u32

Replace the uint32_t type used all over dma-jz4780.c with the equivalent
Linux type: u32.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20211206174259.68133-6-paul@crapouillou.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Paul Cercueil and committed by
Vinod Koul c8c0cda8 3d70fccf

+19 -19
+19 -19
drivers/dma/dma-jz4780.c
··· 104 104 * descriptor base address in the upper 8 bits. 105 105 */ 106 106 struct jz4780_dma_hwdesc { 107 - uint32_t dcm; 108 - uint32_t dsa; 109 - uint32_t dta; 110 - uint32_t dtc; 107 + u32 dcm; 108 + u32 dsa; 109 + u32 dta; 110 + u32 dtc; 111 111 }; 112 112 113 113 /* Size of allocations for hardware descriptor blocks. */ ··· 122 122 dma_addr_t desc_phys; 123 123 unsigned int count; 124 124 enum dma_transaction_type type; 125 - uint32_t status; 125 + u32 status; 126 126 }; 127 127 128 128 struct jz4780_dma_chan { ··· 130 130 unsigned int id; 131 131 struct dma_pool *desc_pool; 132 132 133 - uint32_t transfer_type; 134 - uint32_t transfer_shift; 133 + u32 transfer_type; 134 + u32 transfer_shift; 135 135 struct dma_slave_config config; 136 136 137 137 struct jz4780_dma_desc *desc; ··· 152 152 unsigned int irq; 153 153 const struct jz4780_dma_soc_data *soc_data; 154 154 155 - uint32_t chan_reserved; 155 + u32 chan_reserved; 156 156 struct jz4780_dma_chan chan[]; 157 157 }; 158 158 159 159 struct jz4780_dma_filter_data { 160 - uint32_t transfer_type; 160 + u32 transfer_type; 161 161 int channel; 162 162 }; 163 163 ··· 179 179 dma_device); 180 180 } 181 181 182 - static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma, 182 + static inline u32 jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma, 183 183 unsigned int chn, unsigned int reg) 184 184 { 185 185 return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); 186 186 } 187 187 188 188 static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma, 189 - unsigned int chn, unsigned int reg, uint32_t val) 189 + unsigned int chn, unsigned int reg, u32 val) 190 190 { 191 191 writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); 192 192 } 193 193 194 - static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma, 194 + static inline u32 jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma, 195 195 unsigned int reg) 196 196 { 197 197 return readl(jzdma->ctrl_base + reg); 198 198 } 199 199 200 200 static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma, 201 - unsigned int reg, uint32_t val) 201 + unsigned int reg, u32 val) 202 202 { 203 203 writel(val, jzdma->ctrl_base + reg); 204 204 } ··· 260 260 kfree(desc); 261 261 } 262 262 263 - static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan, 264 - unsigned long val, uint32_t *shift) 263 + static u32 jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan, 264 + unsigned long val, u32 *shift) 265 265 { 266 266 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 267 267 int ord = ffs(val) - 1; ··· 303 303 enum dma_transfer_direction direction) 304 304 { 305 305 struct dma_slave_config *config = &jzchan->config; 306 - uint32_t width, maxburst, tsz; 306 + u32 width, maxburst, tsz; 307 307 308 308 if (direction == DMA_MEM_TO_DEV) { 309 309 desc->dcm = JZ_DMA_DCM_SAI; ··· 453 453 { 454 454 struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 455 455 struct jz4780_dma_desc *desc; 456 - uint32_t tsz; 456 + u32 tsz; 457 457 458 458 desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY); 459 459 if (!desc) ··· 670 670 { 671 671 const unsigned int soc_flags = jzdma->soc_data->flags; 672 672 struct jz4780_dma_desc *desc = jzchan->desc; 673 - uint32_t dcs; 673 + u32 dcs; 674 674 bool ack = true; 675 675 676 676 spin_lock(&jzchan->vchan.lock); ··· 727 727 struct jz4780_dma_dev *jzdma = data; 728 728 unsigned int nb_channels = jzdma->soc_data->nb_channels; 729 729 unsigned long pending; 730 - uint32_t dmac; 730 + u32 dmac; 731 731 int i; 732 732 733 733 pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);