+1 -1

MAINTAINERS

reviewed

··· 7821 7821 Q: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests 7822 7822 B: https://gitlab.freedesktop.org/drm/nouveau/-/issues 7823 7823 C: irc://irc.oftc.net/nouveau 7824 7824 - T: git https://gitlab.freedesktop.org/drm/nouveau.git 7824 7824 + T: git https://gitlab.freedesktop.org/drm/misc/kernel.git 7825 7825 F: drivers/gpu/drm/nouveau/ 7826 7826 F: include/uapi/drm/nouveau_drm.h 7827 7827

+1 -1

drivers/accel/ivpu/ivpu_drv.c

reviewed

··· 677 677 static void ivpu_dev_fini(struct ivpu_device *vdev) 678 678 { 679 679 ivpu_jobs_abort_all(vdev); 680 680 - ivpu_pm_cancel_recovery(vdev); 680 680 + ivpu_pm_disable_recovery(vdev); 681 681 ivpu_pm_disable(vdev); 682 682 ivpu_prepare_for_reset(vdev); 683 683 ivpu_shutdown(vdev);

+2 -2

drivers/accel/ivpu/ivpu_pm.c

reviewed

··· 417 417 ivpu_dbg(vdev, PM, "Autosuspend delay = %d\n", delay); 418 418 } 419 419 420 420 - void ivpu_pm_cancel_recovery(struct ivpu_device *vdev) 420 420 + void ivpu_pm_disable_recovery(struct ivpu_device *vdev) 421 421 { 422 422 drm_WARN_ON(&vdev->drm, delayed_work_pending(&vdev->pm->job_timeout_work)); 423 423 - cancel_work_sync(&vdev->pm->recovery_work); 423 423 + disable_work_sync(&vdev->pm->recovery_work); 424 424 } 425 425 426 426 void ivpu_pm_enable(struct ivpu_device *vdev)

+1 -1

drivers/accel/ivpu/ivpu_pm.h

reviewed

··· 25 25 void ivpu_pm_init(struct ivpu_device *vdev); 26 26 void ivpu_pm_enable(struct ivpu_device *vdev); 27 27 void ivpu_pm_disable(struct ivpu_device *vdev); 28 28 - void ivpu_pm_cancel_recovery(struct ivpu_device *vdev); 28 28 + void ivpu_pm_disable_recovery(struct ivpu_device *vdev); 29 29 30 30 int ivpu_pm_suspend_cb(struct device *dev); 31 31 int ivpu_pm_resume_cb(struct device *dev);

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

reviewed

··· 448 448 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 449 449 if (!psp->cmd) { 450 450 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 451 451 - ret = -ENOMEM; 451 451 + return -ENOMEM; 452 452 } 453 453 454 454 adev->psp.xgmi_context.supports_extended_data =

-5

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

reviewed

··· 1462 1462 1463 1463 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1464 1464 { 1465 1465 - int i; 1466 1466 - 1467 1465 if (!amdgpu_audio) 1468 1466 return; 1469 1467 1470 1468 if (!adev->mode_info.audio.enabled) 1471 1469 return; 1472 1472 - 1473 1473 - for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1474 1474 - dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1475 1470 1476 1471 adev->mode_info.audio.enabled = false; 1477 1472 }

-5

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

reviewed

··· 1511 1511 1512 1512 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1513 1513 { 1514 1514 - int i; 1515 1515 - 1516 1514 if (!amdgpu_audio) 1517 1515 return; 1518 1516 1519 1517 if (!adev->mode_info.audio.enabled) 1520 1518 return; 1521 1521 - 1522 1522 - for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1523 1523 - dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1524 1519 1525 1520 adev->mode_info.audio.enabled = false; 1526 1521 }

-5

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

reviewed

··· 1451 1451 1452 1452 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1453 1453 { 1454 1454 - int i; 1455 1455 - 1456 1454 if (!amdgpu_audio) 1457 1455 return; 1458 1456 1459 1457 if (!adev->mode_info.audio.enabled) 1460 1458 return; 1461 1461 - 1462 1462 - for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1463 1463 - dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1464 1459 1465 1460 adev->mode_info.audio.enabled = false; 1466 1461 }

-5

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

reviewed

··· 1443 1443 1444 1444 static void dce_v8_0_audio_fini(struct amdgpu_device *adev) 1445 1445 { 1446 1446 - int i; 1447 1447 - 1448 1446 if (!amdgpu_audio) 1449 1447 return; 1450 1448 1451 1449 if (!adev->mode_info.audio.enabled) 1452 1450 return; 1453 1453 - 1454 1454 - for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1455 1455 - dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1456 1451 1457 1452 adev->mode_info.audio.enabled = false; 1458 1453 }

+3 -2

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

reviewed

··· 641 641 break; 642 642 case MES_MISC_OP_CHANGE_CONFIG: 643 643 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 644 644 - dev_err(mes->adev->dev, "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 645 645 - return -EINVAL; 644 644 + dev_warn_once(mes->adev->dev, 645 645 + "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 646 646 + return 0; 646 647 } 647 648 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 648 649 misc_pkt.change_config.opcode =

+3 -3

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

reviewed

··· 1377 1377 1378 1378 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1379 1379 case IP_VERSION(6, 0, 0): 1380 1380 - if ((adev->sdma.instance[0].fw_version >= 24) && !adev->sdma.disable_uq) 1380 1380 + if ((adev->sdma.instance[0].fw_version >= 27) && !adev->sdma.disable_uq) 1381 1381 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1382 1382 break; 1383 1383 case IP_VERSION(6, 0, 1): ··· 1385 1385 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1386 1386 break; 1387 1387 case IP_VERSION(6, 0, 2): 1388 1388 - if ((adev->sdma.instance[0].fw_version >= 21) && !adev->sdma.disable_uq) 1388 1388 + if ((adev->sdma.instance[0].fw_version >= 23) && !adev->sdma.disable_uq) 1389 1389 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1390 1390 break; 1391 1391 case IP_VERSION(6, 0, 3): 1392 1392 - if ((adev->sdma.instance[0].fw_version >= 25) && !adev->sdma.disable_uq) 1392 1392 + if ((adev->sdma.instance[0].fw_version >= 27) && !adev->sdma.disable_uq) 1393 1393 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1394 1394 break; 1395 1395 case IP_VERSION(6, 1, 0):

+1 -2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

reviewed

··· 8381 8381 drm_add_modes_noedid(connector, 1920, 1080); 8382 8382 } else { 8383 8383 amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); 8384 8384 - if (encoder && (connector->connector_type != DRM_MODE_CONNECTOR_eDP) && 8385 8385 - (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) 8384 8384 + if (encoder) 8386 8385 amdgpu_dm_connector_add_common_modes(encoder, connector); 8387 8386 amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); 8388 8387 }

+9

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

reviewed

··· 520 520 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); 521 521 } 522 522 523 523 + void dpp_force_disable_cursor(struct dpp *dpp_base) 524 524 + { 525 525 + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 526 526 + 527 527 + /* Force disable cursor */ 528 528 + REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0); 529 529 + dpp_base->pos.cur0_ctl.bits.cur0_enable = 0; 530 530 + } 531 531 + 523 532 static const struct dpp_funcs dcn10_dpp_funcs = { 524 533 .dpp_read_state = dpp_read_state, 525 534 .dpp_reset = dpp_reset,

+2

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

reviewed

··· 1525 1525 1526 1526 void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, 1527 1527 struct dpp_grph_csc_adjustment *adjust); 1528 1528 + void dpp_force_disable_cursor(struct dpp *dpp_base); 1529 1529 + 1528 1530 #endif

+1

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

reviewed

··· 1494 1494 .dpp_dppclk_control = dpp1_dppclk_control, 1495 1495 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, 1496 1496 .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, 1497 1497 + .dpp_force_disable_cursor = dpp_force_disable_cursor, 1497 1498 }; 1498 1499 1499 1500

+72

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

reviewed

··· 528 528 529 529 apply_symclk_on_tx_off_wa(link); 530 530 } 531 531 + 532 532 + /** 533 533 + * dcn314_dpp_pg_control - DPP power gate control. 534 534 + * 535 535 + * @hws: dce_hwseq reference. 536 536 + * @dpp_inst: DPP instance reference. 537 537 + * @power_on: true if we want to enable power gate, false otherwise. 538 538 + * 539 539 + * Enable or disable power gate in the specific DPP instance. 540 540 + * If power gating is disabled, will force disable cursor in the DPP instance. 541 541 + */ 542 542 + void dcn314_dpp_pg_control( 543 543 + struct dce_hwseq *hws, 544 544 + unsigned int dpp_inst, 545 545 + bool power_on) 546 546 + { 547 547 + uint32_t power_gate = power_on ? 0 : 1; 548 548 + uint32_t pwr_status = power_on ? 0 : 2; 549 549 + 550 550 + 551 551 + if (hws->ctx->dc->debug.disable_dpp_power_gate) { 552 552 + /* Workaround for DCN314 with disabled power gating */ 553 553 + if (!power_on) { 554 554 + 555 555 + /* Force disable cursor if power gating is disabled */ 556 556 + struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst]; 557 557 + if (dpp && dpp->funcs->dpp_force_disable_cursor) 558 558 + dpp->funcs->dpp_force_disable_cursor(dpp); 559 559 + } 560 560 + return; 561 561 + } 562 562 + if (REG(DOMAIN1_PG_CONFIG) == 0) 563 563 + return; 564 564 + 565 565 + switch (dpp_inst) { 566 566 + case 0: /* DPP0 */ 567 567 + REG_UPDATE(DOMAIN1_PG_CONFIG, 568 568 + DOMAIN1_POWER_GATE, power_gate); 569 569 + 570 570 + REG_WAIT(DOMAIN1_PG_STATUS, 571 571 + DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 572 572 + 1, 1000); 573 573 + break; 574 574 + case 1: /* DPP1 */ 575 575 + REG_UPDATE(DOMAIN3_PG_CONFIG, 576 576 + DOMAIN3_POWER_GATE, power_gate); 577 577 + 578 578 + REG_WAIT(DOMAIN3_PG_STATUS, 579 579 + DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 580 580 + 1, 1000); 581 581 + break; 582 582 + case 2: /* DPP2 */ 583 583 + REG_UPDATE(DOMAIN5_PG_CONFIG, 584 584 + DOMAIN5_POWER_GATE, power_gate); 585 585 + 586 586 + REG_WAIT(DOMAIN5_PG_STATUS, 587 587 + DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 588 588 + 1, 1000); 589 589 + break; 590 590 + case 3: /* DPP3 */ 591 591 + REG_UPDATE(DOMAIN7_PG_CONFIG, 592 592 + DOMAIN7_POWER_GATE, power_gate); 593 593 + 594 594 + REG_WAIT(DOMAIN7_PG_STATUS, 595 595 + DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 596 596 + 1, 1000); 597 597 + break; 598 598 + default: 599 599 + BREAK_TO_DEBUGGER(); 600 600 + break; 601 601 + } 602 602 + }

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

reviewed

··· 47 47 48 48 void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); 49 49 50 50 + void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); 51 51 + 50 52 #endif /* __DC_HWSS_DCN314_H__ */

+1

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

reviewed

··· 141 141 .enable_power_gating_plane = dcn314_enable_power_gating_plane, 142 142 .dpp_root_clock_control = dcn314_dpp_root_clock_control, 143 143 .hubp_pg_control = dcn31_hubp_pg_control, 144 144 + .dpp_pg_control = dcn314_dpp_pg_control, 144 145 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, 145 146 .update_odm = dcn314_update_odm, 146 147 .dsc_pg_control = dcn314_dsc_pg_control,

+3

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

reviewed

··· 349 349 struct dpp *dpp_base, 350 350 enum dc_color_space color_space, 351 351 struct dc_csc_transform cursor_csc_color_matrix); 352 352 + 353 353 + void (*dpp_force_disable_cursor)(struct dpp *dpp_base); 354 354 + 352 355 }; 353 356 354 357

+11

drivers/gpu/drm/bridge/ti-sn65dsi86.c

reviewed

··· 393 393 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 394 394 395 395 /* 396 396 + * After EN is deasserted and an external clock is detected, the bridge 397 397 + * will sample GPIO3:1 to determine its frequency. The driver will 398 398 + * overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is 399 399 + * racy. Thus we have to wait a couple of us. According to the datasheet 400 400 + * the GPIO lines has to be stable at least 5 us (td5) but it seems that 401 401 + * is not enough and the refclk frequency value is still lost or 402 402 + * overwritten by the bridge itself. Waiting for 20us seems to work. 403 403 + */ 404 404 + usleep_range(20, 30); 405 405 + 406 406 + /* 396 407 * If we have a reference clock we can enable communication w/ the 397 408 * panel (including the aux channel) w/out any need for an input clock 398 409 * so we can do it in resume which lets us read the EDID before

+6 -1

drivers/gpu/drm/nouveau/gv100_fence.c

reviewed

··· 18 18 struct nvif_push *push = &chan->chan.push; 19 19 int ret; 20 20 21 21 - ret = PUSH_WAIT(push, 8); 21 21 + ret = PUSH_WAIT(push, 13); 22 22 if (ret) 23 23 return ret; 24 24 ··· 31 31 NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) | 32 32 NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | 33 33 NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS)); 34 34 + 35 35 + PUSH_MTHD(push, NVC36F, MEM_OP_A, 0, 36 36 + MEM_OP_B, 0, 37 37 + MEM_OP_C, NVDEF(NVC36F, MEM_OP_C, MEMBAR_TYPE, SYS_MEMBAR), 38 38 + MEM_OP_D, NVDEF(NVC36F, MEM_OP_D, OPERATION, MEMBAR)); 34 39 35 40 PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0); 36 41

+85

drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h

reviewed

··· 7 7 8 8 #define NVC36F_NON_STALL_INTERRUPT (0x00000020) 9 9 #define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0 10 10 + // NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for 11 11 + // specifying the page address for a targeted TLB invalidate and the uTLB for 12 12 + // a targeted REPLAY_CANCEL for UVM. 13 13 + // The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly 14 14 + // rearranged fields. 15 15 + #define NVC36F_MEM_OP_A (0x00000028) 16 16 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED 17 17 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type 18 18 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED 19 19 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL 20 20 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 21 21 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 22 22 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 23 23 + #define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 24 24 + #define NVC36F_MEM_OP_B (0x0000002c) 25 25 + #define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 26 26 + #define NVC36F_MEM_OP_C (0x00000030) 27 27 + #define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0 28 28 + #define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 29 29 + #define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 30 30 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 31 31 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 32 32 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED 33 33 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 34 34 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 35 35 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 36 36 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE 37 37 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 38 38 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 39 39 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 40 40 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 41 41 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 42 42 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 43 43 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE 44 44 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 45 45 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 46 46 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 47 47 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL 48 48 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 49 49 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 50 50 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 51 51 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 52 52 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 53 53 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 54 54 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 55 55 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 56 56 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below 57 57 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table 58 58 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 59 59 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 60 60 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 61 61 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 62 62 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 63 63 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 64 64 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 65 65 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE 66 66 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 67 67 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 68 68 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 69 69 + #define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE 70 70 + #define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 71 71 + // MEM_OP_D MUST be preceded by MEM_OPs A-C. 72 72 + #define NVC36F_MEM_OP_D (0x00000034) 73 73 + #define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE 74 74 + #define NVC36F_MEM_OP_D_OPERATION 31:27 75 75 + #define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 76 76 + #define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 77 77 + #define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a 78 78 + #define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d 79 79 + #define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e 80 80 + // CLEAN_LINES is an alias for Tegra/GPU IP usage 81 81 + #define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e 82 82 + #define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f 83 83 + #define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 84 84 + #define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 85 85 + #define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 86 86 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 87 87 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 88 88 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 89 89 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 90 90 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 91 91 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 92 92 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 93 93 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 94 94 + #define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 10 95 #define NVC36F_SEM_ADDR_LO (0x0000005c) 11 96 #define NVC36F_SEM_ADDR_LO_OFFSET 31:2 12 97 #define NVC36F_SEM_ADDR_HI (0x00000060)

+2

drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c

reviewed

··· 350 350 nvkm_chid_unref(&fifo->chid); 351 351 352 352 nvkm_event_fini(&fifo->nonstall.event); 353 353 + if (fifo->func->nonstall_dtor) 354 354 + fifo->func->nonstall_dtor(fifo); 353 355 mutex_destroy(&fifo->mutex); 354 356 355 357 if (fifo->func->dtor)

+15 -8

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c

reviewed

··· 517 517 static void 518 518 ga100_fifo_nonstall_block(struct nvkm_event *event, int type, int index) 519 519 { 520 520 - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event); 521 521 - struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0); 522 522 - 523 523 - nvkm_inth_block(&runl->nonstall.inth); 524 520 } 525 521 526 522 static void 527 523 ga100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index) 528 524 { 529 529 - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event); 530 530 - struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0); 531 531 - 532 532 - nvkm_inth_allow(&runl->nonstall.inth); 533 525 } 534 526 535 527 const struct nvkm_event_func ··· 556 564 if (ret) 557 565 return ret; 558 566 567 567 + nvkm_inth_allow(&runl->nonstall.inth); 568 568 + 559 569 nr = max(nr, runl->id + 1); 560 570 } 561 571 562 572 return nr; 573 573 + } 574 574 + 575 575 + void 576 576 + ga100_fifo_nonstall_dtor(struct nvkm_fifo *fifo) 577 577 + { 578 578 + struct nvkm_runl *runl; 579 579 + 580 580 + nvkm_runl_foreach(runl, fifo) { 581 581 + if (runl->nonstall.vector < 0) 582 582 + continue; 583 583 + nvkm_inth_block(&runl->nonstall.inth); 584 584 + } 563 585 } 564 586 565 587 int ··· 605 599 .runl_ctor = ga100_fifo_runl_ctor, 606 600 .mmu_fault = &tu102_fifo_mmu_fault, 607 601 .nonstall_ctor = ga100_fifo_nonstall_ctor, 602 602 + .nonstall_dtor = ga100_fifo_nonstall_dtor, 608 603 .nonstall = &ga100_fifo_nonstall, 609 604 .runl = &ga100_runl, 610 605 .runq = &ga100_runq,

+1

drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c

reviewed

··· 30 30 .runl_ctor = ga100_fifo_runl_ctor, 31 31 .mmu_fault = &tu102_fifo_mmu_fault, 32 32 .nonstall_ctor = ga100_fifo_nonstall_ctor, 33 33 + .nonstall_dtor = ga100_fifo_nonstall_dtor, 33 34 .nonstall = &ga100_fifo_nonstall, 34 35 .runl = &ga100_runl, 35 36 .runq = &ga100_runq,

+2

drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h

reviewed

··· 41 41 void (*start)(struct nvkm_fifo *, unsigned long *); 42 42 43 43 int (*nonstall_ctor)(struct nvkm_fifo *); 44 44 + void (*nonstall_dtor)(struct nvkm_fifo *); 44 45 const struct nvkm_event_func *nonstall; 45 46 46 47 const struct nvkm_runl_func *runl; ··· 201 200 202 201 int ga100_fifo_runl_ctor(struct nvkm_fifo *); 203 202 int ga100_fifo_nonstall_ctor(struct nvkm_fifo *); 203 203 + void ga100_fifo_nonstall_dtor(struct nvkm_fifo *); 204 204 extern const struct nvkm_event_func ga100_fifo_nonstall; 205 205 extern const struct nvkm_runl_func ga100_runl; 206 206 extern const struct nvkm_runq_func ga100_runq;

+1

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

reviewed

··· 601 601 rm->chan.func = &r535_chan; 602 602 rm->nonstall = &ga100_fifo_nonstall; 603 603 rm->nonstall_ctor = ga100_fifo_nonstall_ctor; 604 604 + rm->nonstall_dtor = ga100_fifo_nonstall_dtor; 604 605 605 606 return nvkm_fifo_new_(rm, device, type, inst, pfifo); 606 607 }

+7 -4

drivers/gpu/drm/scheduler/sched_entity.c

reviewed

··· 391 391 * Add a callback to the current dependency of the entity to wake up the 392 392 * scheduler when the entity becomes available. 393 393 */ 394 394 - static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) 394 394 + static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity, 395 395 + struct drm_sched_job *sched_job) 395 396 { 396 397 struct drm_gpu_scheduler *sched = entity->rq->sched; 397 398 struct dma_fence *fence = entity->dependency; ··· 421 420 dma_fence_put(entity->dependency); 422 421 entity->dependency = fence; 423 422 } 423 423 + 424 424 + if (trace_drm_sched_job_unschedulable_enabled() && 425 425 + !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &entity->dependency->flags)) 426 426 + trace_drm_sched_job_unschedulable(sched_job, entity->dependency); 424 427 425 428 if (!dma_fence_add_callback(entity->dependency, &entity->cb, 426 429 drm_sched_entity_wakeup)) ··· 466 461 467 462 while ((entity->dependency = 468 463 drm_sched_job_dependency(sched_job, entity))) { 469 469 - if (drm_sched_entity_add_dependency_cb(entity)) { 470 470 - trace_drm_sched_job_unschedulable(sched_job, entity->dependency); 464 464 + if (drm_sched_entity_add_dependency_cb(entity, sched_job)) 471 465 return NULL; 472 472 - } 473 466 } 474 467 475 468 /* skip jobs from entity that marked guilty */

+1 -2

drivers/gpu/drm/xe/xe_bo.c

reviewed

··· 819 819 return ret; 820 820 } 821 821 822 822 - tt_has_data = ttm && (ttm_tt_is_populated(ttm) || 823 823 - (ttm->page_flags & TTM_TT_FLAG_SWAPPED)); 822 822 + tt_has_data = ttm && (ttm_tt_is_populated(ttm) || ttm_tt_is_swapped(ttm)); 824 823 825 824 move_lacks_source = !old_mem || (handle_system_ccs ? (!bo->ccs_cleared) : 826 825 (!mem_type_is_vram(old_mem_type) && !tt_has_data));