Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: revision doorbel range for gfx v12_1
Revision doorbell range on muti-XCC mode for gfx v12_1.
Clean up doorbell range set for graphics engine.
V2: Remove doorbell range set from gfx_v12_1_xcc_kiq_init_register.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
c90ed181
cf356fe1
+6
-16
+6
-16
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+6
-16
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
···
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static void gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device *adev,
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int xcc_id)
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{
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-
/* set graphics engine doorbell range */
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-
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER,
2003
-
(adev->doorbell_index.gfx_ring0 * 2) << 2);
2004
-
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER,
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-
(adev->doorbell_index.gfx_userqueue_end * 2) << 2);
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-
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/* set compute engine doorbell range */
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WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER,
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-
(adev->doorbell_index.kiq * 2) << 2);
2003
+
((adev->doorbell_index.kiq +
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+
xcc_id * adev->doorbell_index.xcc_doorbell_range) *
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+
2) << 2);
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WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER,
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-
(adev->doorbell_index.userqueue_end * 2) << 2);
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+
((adev->doorbell_index.userqueue_end +
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+
xcc_id * adev->doorbell_index.xcc_doorbell_range) *
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+
2) << 2);
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}
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static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
···
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mqd->cp_hqd_pq_wptr_poll_addr_lo);
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WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
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mqd->cp_hqd_pq_wptr_poll_addr_hi);
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-
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/* enable the doorbell if requested */
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if (ring->use_doorbell) {
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WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER,
2222
-
(adev->doorbell_index.kiq * 2) << 2);
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-
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER,
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-
(adev->doorbell_index.userqueue_end * 2) << 2);
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-
}
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WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
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2222
mqd->cp_hqd_pq_doorbell_control);