tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/pm: Add support for reset completion on aldebaran

v1: On aldebaran, after hardware context restore, another handshake
needs to happen with PMFW so that reset recovery is complete from
PMFW side. Treat this as RESET_COMPLETE event for aldebaran.

v2: Cleanup coding style, info logs

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher c941e9fe 6d77dd9f

+36 -2
+2 -1
drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
··· 100 100 #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40 101 101 #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41 102 102 103 - #define PPSMC_Message_Count 0x42 103 + #define PPSMC_MSG_GfxDriverResetRecovery 0x42 104 + #define PPSMC_Message_Count 0x43 104 105 105 106 //PPSMC Reset Types 106 107 #define PPSMC_RESET_TYPE_WARM_RESET 0x00
+1
drivers/gpu/drm/amd/pm/inc/smu_types.h
··· 225 225 __SMU_DUMMY_MAP(DisableDeterminism), \ 226 226 __SMU_DUMMY_MAP(SetUclkDpmMode), \ 227 227 __SMU_DUMMY_MAP(LightSBR), \ 228 + __SMU_DUMMY_MAP(GfxDriverResetRecovery), 228 229 229 230 #undef __SMU_DUMMY_MAP 230 231 #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
+3
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
··· 268 268 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 269 269 bool enablement); 270 270 271 + int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 272 + uint64_t event_arg); 273 + 271 274 #endif 272 275 #endif
+3 -1
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
··· 126 126 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 127 127 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 128 128 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 129 - MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 129 + MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 130 + MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 130 131 }; 131 132 132 133 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { ··· 1584 1583 .mode1_reset = smu_v13_0_mode1_reset, 1585 1584 .set_mp1_state = aldebaran_set_mp1_state, 1586 1585 .mode2_reset = aldebaran_mode2_reset, 1586 + .wait_for_event = smu_v13_0_wait_for_event, 1587 1587 }; 1588 1588 1589 1589 void aldebaran_set_ppt_funcs(struct smu_context *smu)
+27
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
··· 1374 1374 return ret; 1375 1375 } 1376 1376 1377 + static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu, 1378 + uint64_t event_arg) 1379 + { 1380 + int ret = 0; 1381 + 1382 + dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 1383 + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 1384 + 1385 + return ret; 1386 + } 1387 + 1388 + int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1389 + uint64_t event_arg) 1390 + { 1391 + int ret = -EINVAL; 1392 + 1393 + switch (event) { 1394 + case SMU_EVENT_RESET_COMPLETE: 1395 + ret = smu_v13_0_wait_for_reset_complete(smu, event_arg); 1396 + break; 1397 + default: 1398 + break; 1399 + } 1400 + 1401 + return ret; 1402 + } 1403 + 1377 1404 int smu_v13_0_mode2_reset(struct smu_context *smu) 1378 1405 { 1379 1406 int ret;