Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qualcomm: Update the QMP clamp register for V6
QMP combo phy V6 and above use the clamp register from the PCS always on
(AON) address space. Update the driver accordingly.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Elson Roy Serrao <quic_eserrao@quicinc.com>
Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://patch.msgid.link/20251209-linux-next-12825-v8-7-42133596bda0@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Wesley Cheng
and committed by
Vinod Koul
c9543cca
7dbba9fb
+57
-5
+33
-5
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+33
-5
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
30
30
#include "phy-qcom-qmp-common.h"
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#include "phy-qcom-qmp.h"
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+
#include "phy-qcom-qmp-pcs-aon-v6.h"
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#include "phy-qcom-qmp-pcs-misc-v3.h"
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+
#include "phy-qcom-qmp-pcs-misc-v4.h"
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#include "phy-qcom-qmp-pcs-misc-v5.h"
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#include "phy-qcom-qmp-pcs-usb-v4.h"
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#include "phy-qcom-qmp-pcs-usb-v5.h"
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#include "phy-qcom-qmp-pcs-usb-v6.h"
···
82
79
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
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QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
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QPHY_PCS_POWER_DOWN_CONTROL,
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+
QPHY_PCS_CLAMP_ENABLE,
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QPHY_COM_RESETSM_CNTRL,
87
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QPHY_COM_C_READY_STATUS,
···
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[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
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[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
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+
[QPHY_PCS_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
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+
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[QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL,
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[QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
···
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/* In PCS_USB */
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[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
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[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
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+
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+
[QPHY_PCS_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
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[QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL,
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[QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS,
···
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[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
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[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
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+
[QPHY_PCS_CLAMP_ENABLE] = QPHY_V5_PCS_MISC_CLAMP_ENABLE,
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+
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[QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL,
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[QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS,
···
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[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
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[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
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+
[QPHY_PCS_CLAMP_ENABLE] = QPHY_V6_PCS_AON_CLAMP_ENABLE,
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+
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[QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
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[QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
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[QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
···
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/* In PCS_USB */
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[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
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[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
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+
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[QPHY_PCS_CLAMP_ENABLE] = QPHY_V6_PCS_AON_CLAMP_ENABLE,
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[QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
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[QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
···
1785
1771
u16 usb3_serdes;
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u16 usb3_pcs_misc;
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u16 usb3_pcs;
1774
+
u16 usb3_pcs_aon;
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u16 usb3_pcs_usb;
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u16 dp_serdes;
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u16 dp_txa;
···
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void __iomem *tx2;
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void __iomem *rx2;
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void __iomem *pcs_misc;
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void __iomem *pcs_aon;
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void __iomem *pcs_usb;
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1858
void __iomem *dp_serdes;
···
1992
1976
.usb3_serdes = 0x1000,
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.usb3_pcs_misc = 0x1c00,
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.usb3_pcs = 0x1e00,
1979
+
.usb3_pcs_aon = 0x2000,
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.usb3_pcs_usb = 0x2100,
1996
1981
.dp_serdes = 0x3000,
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.dp_txa = 0x3400,
···
3378
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
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void __iomem *pcs_misc = qmp->pcs_misc;
3364
+
void __iomem *pcs_aon = qmp->pcs_aon;
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u32 intr_mask;
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if (qmp->phy_mode == PHY_MODE_USB_HOST_SS ||
···
3398
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/* Enable required PHY autonomous mode interrupts */
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qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3400
3382
3401
-
/* Enable i/o clamp_n for autonomous mode */
3402
-
if (pcs_misc)
3403
-
qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3383
+
/*
3384
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* Enable i/o clamp_n for autonomous mode
3385
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* V6 and later versions use pcs aon clamp register
3386
+
*/
3387
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if (pcs_aon)
3388
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qphy_clrbits(pcs_aon, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN);
3389
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else if (pcs_misc)
3390
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qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN);
3404
3391
}
3405
3392
3406
3393
static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
···
3413
3390
const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
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void __iomem *pcs_misc = qmp->pcs_misc;
3393
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void __iomem *pcs_aon = qmp->pcs_aon;
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/* Disable i/o clamp_n on resume for normal mode */
3418
-
if (pcs_misc)
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-
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3396
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if (pcs_aon)
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qphy_setbits(pcs_aon, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN);
3398
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else if (pcs_misc)
3399
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qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN);
3420
3400
3421
3401
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
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3402
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
···
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qmp->serdes = base + offs->usb3_serdes;
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qmp->pcs_misc = base + offs->usb3_pcs_misc;
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qmp->pcs = base + offs->usb3_pcs;
4061
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if (offs->usb3_pcs_aon)
4062
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qmp->pcs_aon = base + offs->usb3_pcs_aon;
4087
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qmp->pcs_usb = base + offs->usb3_pcs_usb;
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4089
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qmp->dp_serdes = base + offs->dp_serdes;
+12
drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v6.h
+12
drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
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+
/*
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* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
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+
*/
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+
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#ifndef QCOM_PHY_QMP_PCS_AON_V6_H_
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#define QCOM_PHY_QMP_PCS_AON_V6_H_
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+
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/* Only for QMP V6 PHY - PCS_AON registers */
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#define QPHY_V6_PCS_AON_CLAMP_ENABLE 0x00
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+
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+
#endif
+12
drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v5.h
+12
drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v5.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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+
*/
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+
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#ifndef QCOM_PHY_QMP_PCS_MISC_V5_H_
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#define QCOM_PHY_QMP_PCS_MISC_V5_H_
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/* Only for QMP V5 PHY - PCS_MISC registers */
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#define QPHY_V5_PCS_MISC_CLAMP_ENABLE 0x0c
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+
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#endif