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phy: qcom: qmp-pcie: add QMP PCIe PHY tables for SM8650

Add QMP PCIe PHY support for the SM8650 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-6-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Neil Armstrong and committed by
Vinod Koul c954b6d3 7c4bf8cb

+65
+65
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1909 1909 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 1910 1910 }; 1911 1911 1912 + static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 1913 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 1914 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1915 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1916 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1917 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 1918 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 1919 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1920 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1921 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1922 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1923 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1924 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1925 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 1926 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 1927 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 1928 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1929 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 1930 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1931 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1932 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 1933 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 1934 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1935 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1936 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 1937 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1938 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1939 + }; 1940 + 1912 1941 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 1913 1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1914 1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ··· 3076 3047 .has_nocsr_reset = true, 3077 3048 }; 3078 3049 3050 + static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 3051 + .lanes = 2, 3052 + 3053 + .offsets = &qmp_pcie_offsets_v6_20, 3054 + 3055 + .tbls = { 3056 + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3057 + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3058 + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3059 + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3060 + .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 3061 + .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 3062 + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3063 + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3064 + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3065 + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3066 + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3067 + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3068 + }, 3069 + .reset_list = sdm845_pciephy_reset_l, 3070 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3071 + .vreg_list = sm8550_qmp_phy_vreg_l, 3072 + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3073 + .regs = pciephy_v5_regs_layout, 3074 + 3075 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3076 + .phy_status = PHYSTATUS_4_20, 3077 + .has_nocsr_reset = true, 3078 + }; 3079 + 3079 3080 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 3080 3081 .lanes = 2, 3081 3082 .offsets = &qmp_pcie_offsets_v5_20, ··· 3879 3820 }, { 3880 3821 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 3881 3822 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 3823 + }, { 3824 + .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 3825 + .data = &sm8550_qmp_gen3x2_pciephy_cfg, 3826 + }, { 3827 + .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 3828 + .data = &sm8650_qmp_gen4x2_pciephy_cfg, 3882 3829 }, 3883 3830 { }, 3884 3831 };