pwm: mediatek: Simplify representation of channel offsets

The general register layout contains some per-chip registers starting at
offset 0 and then at a higher address there are n nearly identical and
equidistant blocks for the registers of the n channels.

This allows to represent the offsets of per-channel registers as $base +
i * $width instead of listing all (or too many) offsets explicitly in an
array. So for a small additional effort in pwm_mediatek_writel() the
three arrays with the channel offsets can be dropped.

The size changes according to bloat-o-meter are:

add/remove: 0/3 grow/shrink: 1/0 up/down: 12/-96 (-84)
Function old new delta
pwm_mediatek_apply 696 708 +12
mtk_pwm_reg_offset_v3 32 - -32
mtk_pwm_reg_offset_v2 32 - -32
mtk_pwm_reg_offset_v1 32 - -32
Total: Before=5347, After=5263, chg -1.57%

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250725154506.2610172-11-u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

authored by

Uwe Kleine-König and committed by

Uwe Kleine-König 9 months ago c95ab56a a2f77ae4

+30 -28

1 changed file

expand all

drivers

pwm

pwm-mediatek.c

+30 -28

drivers/pwm/pwm-mediatek.c

··· 38 38 unsigned int num_pwms; 39 39 bool pwm45_fixup; 40 40 u16 pwm_ck_26m_sel_reg; 41 - const unsigned int *reg_offset; 41 + unsigned int chanreg_base; 42 + unsigned int chanreg_width; 42 43 }; 43 44 44 45 /** ··· 56 55 struct clk *clk_main; 57 56 struct clk **clk_pwms; 58 57 const struct pwm_mediatek_of_data *soc; 59 - }; 60 - 61 - static const unsigned int mtk_pwm_reg_offset_v1[] = { 62 - 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 63 - }; 64 - 65 - static const unsigned int mtk_pwm_reg_offset_v2[] = { 66 - 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 67 - }; 68 - 69 - /* PWM IP Version 3.0.2 */ 70 - static const unsigned int mtk_pwm_reg_offset_v3[] = { 71 - 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800 72 58 }; 73 59 74 60 static inline struct pwm_mediatek_chip * ··· 106 118 unsigned int num, unsigned int offset, 107 119 u32 value) 108 120 { 109 - writel(value, chip->regs + chip->soc->reg_offset[num] + offset); 121 + writel(value, chip->regs + chip->soc->chanreg_base + 122 + num * chip->soc->chanreg_width + offset); 110 123 } 111 124 112 125 static void pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) ··· 292 303 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 293 304 .num_pwms = 8, 294 305 .pwm45_fixup = false, 295 - .reg_offset = mtk_pwm_reg_offset_v1, 306 + .chanreg_base = 0x10, 307 + .chanreg_width = 0x40, 296 308 }; 297 309 298 310 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 299 311 .num_pwms = 7, 300 312 .pwm45_fixup = false, 301 - .reg_offset = mtk_pwm_reg_offset_v1, 313 + .chanreg_base = 0x10, 314 + .chanreg_width = 0x40, 302 315 }; 303 316 304 317 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 305 318 .num_pwms = 6, 306 319 .pwm45_fixup = false, 307 320 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 308 - .reg_offset = mtk_pwm_reg_offset_v1, 321 + .chanreg_base = 0x10, 322 + .chanreg_width = 0x40, 309 323 }; 310 324 311 325 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 312 326 .num_pwms = 5, 313 327 .pwm45_fixup = true, 314 - .reg_offset = mtk_pwm_reg_offset_v1, 328 + .chanreg_base = 0x10, 329 + .chanreg_width = 0x40, 315 330 }; 316 331 317 332 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 318 333 .num_pwms = 4, 319 334 .pwm45_fixup = true, 320 - .reg_offset = mtk_pwm_reg_offset_v1, 335 + .chanreg_base = 0x10, 336 + .chanreg_width = 0x40, 321 337 }; 322 338 323 339 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 324 340 .num_pwms = 1, 325 341 .pwm45_fixup = false, 326 - .reg_offset = mtk_pwm_reg_offset_v1, 342 + .chanreg_base = 0x10, 343 + .chanreg_width = 0x40, 327 344 }; 328 345 329 346 static const struct pwm_mediatek_of_data mt7981_pwm_data = { 330 347 .num_pwms = 3, 331 348 .pwm45_fixup = false, 332 349 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 333 - .reg_offset = mtk_pwm_reg_offset_v2, 350 + .chanreg_base = 0x80, 351 + .chanreg_width = 0x40, 334 352 }; 335 353 336 354 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 337 355 .num_pwms = 2, 338 356 .pwm45_fixup = false, 339 357 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 340 - .reg_offset = mtk_pwm_reg_offset_v1, 358 + .chanreg_base = 0x10, 359 + .chanreg_width = 0x40, 341 360 }; 342 361 343 362 static const struct pwm_mediatek_of_data mt7988_pwm_data = { 344 363 .num_pwms = 8, 345 364 .pwm45_fixup = false, 346 - .reg_offset = mtk_pwm_reg_offset_v2, 365 + .chanreg_base = 0x80, 366 + .chanreg_width = 0x40, 347 367 }; 348 368 349 369 static const struct pwm_mediatek_of_data mt8183_pwm_data = { 350 370 .num_pwms = 4, 351 371 .pwm45_fixup = false, 352 372 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 353 - .reg_offset = mtk_pwm_reg_offset_v1, 373 + .chanreg_base = 0x10, 374 + .chanreg_width = 0x40, 354 375 }; 355 376 356 377 static const struct pwm_mediatek_of_data mt8365_pwm_data = { 357 378 .num_pwms = 3, 358 379 .pwm45_fixup = false, 359 380 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 360 - .reg_offset = mtk_pwm_reg_offset_v1, 381 + .chanreg_base = 0x10, 382 + .chanreg_width = 0x40, 361 383 }; 362 384 363 385 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 364 386 .num_pwms = 5, 365 387 .pwm45_fixup = false, 366 388 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 367 - .reg_offset = mtk_pwm_reg_offset_v1, 389 + .chanreg_base = 0x10, 390 + .chanreg_width = 0x40, 368 391 }; 369 392 370 393 static const struct pwm_mediatek_of_data mt6991_pwm_data = { 371 394 .num_pwms = 4, 372 395 .pwm45_fixup = false, 373 396 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3, 374 - .reg_offset = mtk_pwm_reg_offset_v3, 397 + .chanreg_base = 0x100, 398 + .chanreg_width = 0x100, 375 399 }; 376 400 377 401 static const struct of_device_id pwm_mediatek_of_match[] = {

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