tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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serial: xilinx_uartps: Use port lock wrappers

When a serial port is used for kernel console output, then all
modifications to the UART registers which are done from other contexts,
e.g. getty, termios, are interference points for the kernel console.

So far this has been ignored and the printk output is based on the
principle of hope. The rework of the console infrastructure which aims to
support threaded and atomic consoles, requires to mark sections which
modify the UART registers as unsafe. This allows the atomic write function
to make informed decisions and eventually to restore operational state. It
also allows to prevent the regular UART code from modifying UART registers
while printk output is in progress.

All modifications of UART registers are guarded by the UART port lock,
which provides an obvious synchronization point with the console
infrastructure.

To avoid adding this functionality to all UART drivers, wrap the
spin_[un]lock*() invocations for uart_port::lock into helper functions
which just contain the spin_[un]lock*() invocations for now. In a
subsequent step these helpers will gain the console synchronization
mechanisms.

Converted with coccinelle. No functional change.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: John Ogness <john.ogness@linutronix.de>
Link: https://lore.kernel.org/r/20230914183831.587273-75-john.ogness@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Thomas Gleixner and committed by
Greg Kroah-Hartman c9802481 4bfdd1ed

+28 -28
+28 -28
drivers/tty/serial/xilinx_uartps.c
··· 346 346 struct uart_port *port = (struct uart_port *)dev_id; 347 347 unsigned int isrstatus; 348 348 349 - spin_lock(&port->lock); 349 + uart_port_lock(port); 350 350 351 351 /* Read the interrupt status register to determine which 352 352 * interrupt(s) is/are active and clear them. ··· 369 369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) 370 370 cdns_uart_handle_rx(dev_id, isrstatus); 371 371 372 - spin_unlock(&port->lock); 372 + uart_port_unlock(port); 373 373 return IRQ_HANDLED; 374 374 } 375 375 ··· 506 506 return NOTIFY_BAD; 507 507 } 508 508 509 - spin_lock_irqsave(&cdns_uart->port->lock, flags); 509 + uart_port_lock_irqsave(cdns_uart->port, &flags); 510 510 511 511 /* Disable the TX and RX to set baud rate */ 512 512 ctrl_reg = readl(port->membase + CDNS_UART_CR); 513 513 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 514 514 writel(ctrl_reg, port->membase + CDNS_UART_CR); 515 515 516 - spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 516 + uart_port_unlock_irqrestore(cdns_uart->port, flags); 517 517 518 518 return NOTIFY_OK; 519 519 } ··· 523 523 * frequency. 524 524 */ 525 525 526 - spin_lock_irqsave(&cdns_uart->port->lock, flags); 526 + uart_port_lock_irqsave(cdns_uart->port, &flags); 527 527 528 528 locked = 1; 529 529 port->uartclk = ndata->new_rate; ··· 533 533 fallthrough; 534 534 case ABORT_RATE_CHANGE: 535 535 if (!locked) 536 - spin_lock_irqsave(&cdns_uart->port->lock, flags); 536 + uart_port_lock_irqsave(cdns_uart->port, &flags); 537 537 538 538 /* Set TX/RX Reset */ 539 539 ctrl_reg = readl(port->membase + CDNS_UART_CR); ··· 555 555 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 556 556 writel(ctrl_reg, port->membase + CDNS_UART_CR); 557 557 558 - spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 558 + uart_port_unlock_irqrestore(cdns_uart->port, flags); 559 559 560 560 return NOTIFY_OK; 561 561 default: ··· 652 652 unsigned int status; 653 653 unsigned long flags; 654 654 655 - spin_lock_irqsave(&port->lock, flags); 655 + uart_port_lock_irqsave(port, &flags); 656 656 657 657 status = readl(port->membase + CDNS_UART_CR); 658 658 ··· 664 664 writel(CDNS_UART_CR_STOPBRK | status, 665 665 port->membase + CDNS_UART_CR); 666 666 } 667 - spin_unlock_irqrestore(&port->lock, flags); 667 + uart_port_unlock_irqrestore(port, flags); 668 668 } 669 669 670 670 /** ··· 683 683 unsigned long flags; 684 684 unsigned int ctrl_reg, mode_reg; 685 685 686 - spin_lock_irqsave(&port->lock, flags); 686 + uart_port_lock_irqsave(port, &flags); 687 687 688 688 /* Disable the TX and RX to set baud rate */ 689 689 ctrl_reg = readl(port->membase + CDNS_UART_CR); ··· 794 794 cval &= ~CDNS_UART_MODEMCR_FCM; 795 795 writel(cval, port->membase + CDNS_UART_MODEMCR); 796 796 797 - spin_unlock_irqrestore(&port->lock, flags); 797 + uart_port_unlock_irqrestore(port, flags); 798 798 } 799 799 800 800 /** ··· 813 813 814 814 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 815 815 816 - spin_lock_irqsave(&port->lock, flags); 816 + uart_port_lock_irqsave(port, &flags); 817 817 818 818 /* Disable the TX and RX */ 819 819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, ··· 861 861 writel(readl(port->membase + CDNS_UART_ISR), 862 862 port->membase + CDNS_UART_ISR); 863 863 864 - spin_unlock_irqrestore(&port->lock, flags); 864 + uart_port_unlock_irqrestore(port, flags); 865 865 866 866 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 867 867 if (ret) { ··· 889 889 int status; 890 890 unsigned long flags; 891 891 892 - spin_lock_irqsave(&port->lock, flags); 892 + uart_port_lock_irqsave(port, &flags); 893 893 894 894 /* Disable interrupts */ 895 895 status = readl(port->membase + CDNS_UART_IMR); ··· 900 900 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 901 901 port->membase + CDNS_UART_CR); 902 902 903 - spin_unlock_irqrestore(&port->lock, flags); 903 + uart_port_unlock_irqrestore(port, flags); 904 904 905 905 free_irq(port->irq, port); 906 906 } ··· 1050 1050 int c; 1051 1051 unsigned long flags; 1052 1052 1053 - spin_lock_irqsave(&port->lock, flags); 1053 + uart_port_lock_irqsave(port, &flags); 1054 1054 1055 1055 /* Check if FIFO is empty */ 1056 1056 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) ··· 1058 1058 else /* Read a character */ 1059 1059 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1060 1060 1061 - spin_unlock_irqrestore(&port->lock, flags); 1061 + uart_port_unlock_irqrestore(port, flags); 1062 1062 1063 1063 return c; 1064 1064 } ··· 1067 1067 { 1068 1068 unsigned long flags; 1069 1069 1070 - spin_lock_irqsave(&port->lock, flags); 1070 + uart_port_lock_irqsave(port, &flags); 1071 1071 1072 1072 /* Wait until FIFO is empty */ 1073 1073 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) ··· 1080 1080 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1081 1081 cpu_relax(); 1082 1082 1083 - spin_unlock_irqrestore(&port->lock, flags); 1083 + uart_port_unlock_irqrestore(port, flags); 1084 1084 } 1085 1085 #endif 1086 1086 ··· 1232 1232 if (port->sysrq) 1233 1233 locked = 0; 1234 1234 else if (oops_in_progress) 1235 - locked = spin_trylock_irqsave(&port->lock, flags); 1235 + locked = uart_port_trylock_irqsave(port, &flags); 1236 1236 else 1237 - spin_lock_irqsave(&port->lock, flags); 1237 + uart_port_lock_irqsave(port, &flags); 1238 1238 1239 1239 /* save and disable interrupt */ 1240 1240 imr = readl(port->membase + CDNS_UART_IMR); ··· 1257 1257 writel(imr, port->membase + CDNS_UART_IER); 1258 1258 1259 1259 if (locked) 1260 - spin_unlock_irqrestore(&port->lock, flags); 1260 + uart_port_unlock_irqrestore(port, flags); 1261 1261 } 1262 1262 1263 1263 /** ··· 1325 1325 if (console_suspend_enabled && uart_console(port) && may_wake) { 1326 1326 unsigned long flags; 1327 1327 1328 - spin_lock_irqsave(&port->lock, flags); 1328 + uart_port_lock_irqsave(port, &flags); 1329 1329 /* Empty the receive FIFO 1st before making changes */ 1330 1330 while (!(readl(port->membase + CDNS_UART_SR) & 1331 1331 CDNS_UART_SR_RXEMPTY)) ··· 1334 1334 writel(1, port->membase + CDNS_UART_RXWM); 1335 1335 /* disable RX timeout interrups */ 1336 1336 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1337 - spin_unlock_irqrestore(&port->lock, flags); 1337 + uart_port_unlock_irqrestore(port, flags); 1338 1338 } 1339 1339 1340 1340 /* ··· 1372 1372 return ret; 1373 1373 } 1374 1374 1375 - spin_lock_irqsave(&port->lock, flags); 1375 + uart_port_lock_irqsave(port, &flags); 1376 1376 1377 1377 /* Set TX/RX Reset */ 1378 1378 ctrl_reg = readl(port->membase + CDNS_UART_CR); ··· 1392 1392 1393 1393 clk_disable(cdns_uart->uartclk); 1394 1394 clk_disable(cdns_uart->pclk); 1395 - spin_unlock_irqrestore(&port->lock, flags); 1395 + uart_port_unlock_irqrestore(port, flags); 1396 1396 } else { 1397 - spin_lock_irqsave(&port->lock, flags); 1397 + uart_port_lock_irqsave(port, &flags); 1398 1398 /* restore original rx trigger level */ 1399 1399 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1400 1400 /* enable RX timeout interrupt */ 1401 1401 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1402 - spin_unlock_irqrestore(&port->lock, flags); 1402 + uart_port_unlock_irqrestore(port, flags); 1403 1403 } 1404 1404 1405 1405 return uart_resume_port(cdns_uart->cdns_uart_driver, port);