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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"A nice small set of bug fixes for arm-soc:

- two incorrect register addresses in DT files on shmobile and hisilicon
- one revert for a regression on omap
- one bug fix for a newly introduced pin controller binding
- one regression fix for the memory controller on omap
- one patch to avoid a harmless WARN_ON"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: Revert enabling of twl configuration for n900
ARM: dts: fix L2 address in Hi3620
ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable()
pinctrl: dra: dt-bindings: Fix pull enable/disable
ARM: shmobile: r8a7791: Fix SD2CKCR register address
ARM: OMAP2+: l2c: squelch warning dump on power control setting

+22 -15
+1 -1
arch/arm/boot/dts/hi3620.dtsi
··· 73 73 74 74 L2: l2-cache { 75 75 compatible = "arm,pl310-cache"; 76 - reg = <0xfc10000 0x100000>; 76 + reg = <0x100000 0x100000>; 77 77 interrupts = <0 15 4>; 78 78 cache-unified; 79 79 cache-level = <2>;
+1 -1
arch/arm/boot/dts/omap3-n900.dts
··· 353 353 }; 354 354 355 355 twl_power: power { 356 - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; 356 + compatible = "ti,twl4030-power-n900"; 357 357 ti,use_poweroff; 358 358 }; 359 359 };
+2 -2
arch/arm/boot/dts/r8a7791.dtsi
··· 540 540 #clock-cells = <0>; 541 541 clock-output-names = "sd1"; 542 542 }; 543 - sd2_clk: sd3_clk@e615007c { 543 + sd2_clk: sd3_clk@e615026c { 544 544 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 545 - reg = <0 0xe615007c 0 4>; 545 + reg = <0 0xe615026c 0 4>; 546 546 clocks = <&pll1_div2_clk>; 547 547 #clock-cells = <0>; 548 548 clock-output-names = "sd2";
+10 -8
arch/arm/mach-omap2/gpmc-nand.c
··· 50 50 soc_is_omap54xx() || soc_is_dra7xx()) 51 51 return 1; 52 52 53 + if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW || 54 + ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) { 55 + if (cpu_is_omap24xx()) 56 + return 0; 57 + else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0)) 58 + return 0; 59 + else 60 + return 1; 61 + } 62 + 53 63 /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes 54 64 * which require H/W based ECC error detection */ 55 65 if ((cpu_is_omap34xx() || cpu_is_omap3630()) && 56 66 ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) || 57 67 (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) 58 - return 0; 59 - 60 - /* 61 - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 62 - * and AM33xx derivates. Other chips may be added if confirmed to work. 63 - */ 64 - if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) && 65 - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) 66 68 return 0; 67 69 68 70 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
+4
arch/arm/mach-omap2/omap4-common.c
··· 168 168 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX; 169 169 break; 170 170 171 + case L310_POWER_CTRL: 172 + pr_info_once("OMAP L2C310: ROM does not support power control setting\n"); 173 + return; 174 + 171 175 default: 172 176 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); 173 177 return;
+4 -3
include/dt-bindings/pinctrl/dra.h
··· 30 30 #define MUX_MODE14 0xe 31 31 #define MUX_MODE15 0xf 32 32 33 - #define PULL_ENA (1 << 16) 33 + #define PULL_ENA (0 << 16) 34 + #define PULL_DIS (1 << 16) 34 35 #define PULL_UP (1 << 17) 35 36 #define INPUT_EN (1 << 18) 36 37 #define SLEWCONTROL (1 << 19) ··· 39 38 #define WAKEUP_EVENT (1 << 25) 40 39 41 40 /* Active pin states */ 42 - #define PIN_OUTPUT 0 41 + #define PIN_OUTPUT (0 | PULL_DIS) 43 42 #define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) 44 43 #define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) 45 - #define PIN_INPUT INPUT_EN 44 + #define PIN_INPUT (INPUT_EN | PULL_DIS) 46 45 #define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) 47 46 #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) 48 47 #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)