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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
pwm: sophgo: add driver for Sophgo SG2042 PWM
Add a PWM driver for PWM controller in Sophgo SG2042 SoC.
Signed-off-by: Sean Young <sean@mess.org>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/ae8ea1bf0bb0a09336cd8b7f627a994630524bba.1738737617.git.unicorn_wang@outlook.com
[ukleinek: Drop unneeded reset_control_assert() from error path]
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
authored by
Chen Wang
and committed by
Uwe Kleine-König
c98e6614
d893760c
+205
+10
drivers/pwm/Kconfig
+10
drivers/pwm/Kconfig
···
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To compile this driver as a module, choose M here: the module
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will be called pwm-sl28cpld.
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config PWM_SOPHGO_SG2042
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tristate "Sophgo SG2042 PWM support"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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PWM driver for the PWM controller on Sophgo SG2042 SoC. The PWM
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controller supports outputing 4 channels of PWM waveforms.
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To compile this driver as a module, choose M here: the module
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will be called pwm_sophgo_sg2042.
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config PWM_SPEAR
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tristate "STMicroelectronics SPEAr PWM support"
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depends on PLAT_SPEAR || COMPILE_TEST
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drivers/pwm/Makefile
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drivers/pwm/Makefile
···
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
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obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
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obj-$(CONFIG_PWM_SOPHGO_SG2042) += pwm-sophgo-sg2042.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
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obj-$(CONFIG_PWM_STI) += pwm-sti.o
+194
drivers/pwm/pwm-sophgo-sg2042.c
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drivers/pwm/pwm-sophgo-sg2042.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Sophgo SG2042 PWM Controller Driver
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*
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* Copyright (C) 2024 Sophgo Technology Inc.
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* Copyright (C) 2024 Chen Wang <unicorn_wang@outlook.com>
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*
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* Limitations:
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* - After reset, the output of the PWM channel is always high.
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* The value of HLPERIOD/PERIOD is 0.
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* - When HLPERIOD or PERIOD is reconfigured, PWM will start to
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* output waveforms with the new configuration after completing
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* the running period.
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* - When PERIOD and HLPERIOD is set to 0, the PWM wave output will
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* be stopped and the output is pulled to high.
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* See the datasheet [1] for more details.
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* [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/reset.h>
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/*
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* Offset RegisterName
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* 0x0000 HLPERIOD0
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* 0x0004 PERIOD0
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* 0x0008 HLPERIOD1
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* 0x000C PERIOD1
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* 0x0010 HLPERIOD2
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* 0x0014 PERIOD2
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* 0x0018 HLPERIOD3
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* 0x001C PERIOD3
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* Four groups and every group is composed of HLPERIOD & PERIOD
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*/
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#define SG2042_PWM_HLPERIOD(chan) ((chan) * 8 + 0)
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#define SG2042_PWM_PERIOD(chan) ((chan) * 8 + 4)
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#define SG2042_PWM_CHANNELNUM 4
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/**
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* struct sg2042_pwm_ddata - private driver data
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* @base: base address of mapped PWM registers
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* @clk_rate_hz: rate of base clock in HZ
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*/
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struct sg2042_pwm_ddata {
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void __iomem *base;
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unsigned long clk_rate_hz;
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};
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/*
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* period_ticks: PERIOD
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* hlperiod_ticks: HLPERIOD
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*/
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static void pwm_sg2042_config(struct sg2042_pwm_ddata *ddata, unsigned int chan,
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u32 period_ticks, u32 hlperiod_ticks)
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{
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void __iomem *base = ddata->base;
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writel(period_ticks, base + SG2042_PWM_PERIOD(chan));
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writel(hlperiod_ticks, base + SG2042_PWM_HLPERIOD(chan));
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}
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static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
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u32 hlperiod_ticks;
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u32 period_ticks;
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if (state->polarity == PWM_POLARITY_INVERSED)
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return -EINVAL;
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if (!state->enabled) {
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pwm_sg2042_config(ddata, pwm->hwpwm, 0, 0);
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return 0;
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}
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/*
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* Duration of High level (duty_cycle) = HLPERIOD x Period_of_input_clk
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* Duration of One Cycle (period) = PERIOD x Period_of_input_clk
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*/
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period_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSEC_PER_SEC), U32_MAX);
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hlperiod_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->duty_cycle, NSEC_PER_SEC), U32_MAX);
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dev_dbg(pwmchip_parent(chip), "chan[%u]: PERIOD=%u, HLPERIOD=%u\n",
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pwm->hwpwm, period_ticks, hlperiod_ticks);
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pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks);
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return 0;
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}
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static int pwm_sg2042_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
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unsigned int chan = pwm->hwpwm;
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u32 hlperiod_ticks;
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u32 period_ticks;
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period_ticks = readl(ddata->base + SG2042_PWM_PERIOD(chan));
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hlperiod_ticks = readl(ddata->base + SG2042_PWM_HLPERIOD(chan));
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if (!period_ticks) {
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state->enabled = false;
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return 0;
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}
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if (hlperiod_ticks > period_ticks)
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hlperiod_ticks = period_ticks;
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state->enabled = true;
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state->period = DIV_ROUND_UP_ULL((u64)period_ticks * NSEC_PER_SEC, ddata->clk_rate_hz);
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state->duty_cycle = DIV_ROUND_UP_ULL((u64)hlperiod_ticks * NSEC_PER_SEC, ddata->clk_rate_hz);
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state->polarity = PWM_POLARITY_NORMAL;
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return 0;
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}
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static const struct pwm_ops pwm_sg2042_ops = {
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.apply = pwm_sg2042_apply,
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.get_state = pwm_sg2042_get_state,
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};
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static const struct of_device_id sg2042_pwm_ids[] = {
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{ .compatible = "sophgo,sg2042-pwm" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sg2042_pwm_ids);
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static int pwm_sg2042_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sg2042_pwm_ddata *ddata;
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struct reset_control *rst;
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struct pwm_chip *chip;
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struct clk *clk;
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int ret;
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chip = devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata));
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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ddata = pwmchip_get_drvdata(chip);
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ddata->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ddata->base))
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return PTR_ERR(ddata->base);
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clk = devm_clk_get_enabled(dev, "apb");
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk), "Failed to get base clk\n");
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ret = devm_clk_rate_exclusive_get(dev, clk);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to get exclusive rate\n");
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ddata->clk_rate_hz = clk_get_rate(clk);
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/* period = PERIOD * NSEC_PER_SEC / clk_rate_hz */
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if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
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return dev_err_probe(dev, -EINVAL,
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"Invalid clock rate: %lu\n", ddata->clk_rate_hz);
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rst = devm_reset_control_get_optional_shared_deasserted(dev, NULL);
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if (IS_ERR(rst))
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return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n");
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chip->ops = &pwm_sg2042_ops;
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chip->atomic = true;
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ret = devm_pwmchip_add(dev, chip);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Failed to register PWM chip\n");
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return 0;
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}
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static struct platform_driver pwm_sg2042_driver = {
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.driver = {
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.name = "sg2042-pwm",
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.of_match_table = sg2042_pwm_ids,
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},
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.probe = pwm_sg2042_probe,
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};
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module_platform_driver(pwm_sg2042_driver);
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MODULE_AUTHOR("Chen Wang");
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MODULE_DESCRIPTION("Sophgo SG2042 PWM driver");
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MODULE_LICENSE("GPL");