Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"This is dominated by a large number of changes necessary for the MIPS
BPF code. code. Aside of that there are
- a fix for the MSC system controller support code.
- a Turbochannel fix.
- a recordmcount fix that's MIPS-specific.
- barrier fixes to smp-cps / pm-cps after unrelated changes elsewhere
in the kernel.
- revert support for MSA registers in the signal frames. The
reverted patch did modify the signal stack frame which of course is
inacceptable.
- fix math-emu build breakage with older compilers.
- some related cleanup.
- fix Lasat build error if CONFIG_CRC32 isn't set to y by the user"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (27 commits)
MIPS: Lasat: Fix build error if CRC32 is not enabled.
TC: Handle device_register() errors.
MIPS: MSC: Prevent out-of-bounds writes to MIPS SC ioremap'd region
MIPS: bpf: Fix stack space allocation for BPF memwords on MIPS64
MIPS: BPF: Use 32 or 64-bit load instruction to load an address to register
MIPS: bpf: Fix PKT_TYPE case for big-endian cores
MIPS: BPF: Prevent kernel fall over for >=32bit shifts
MIPS: bpf: Drop update_on_xread and always initialize the X register
MIPS: bpf: Fix is_range() semantics
MIPS: bpf: Use pr_debug instead of pr_warn for unhandled opcodes
MIPS: bpf: Fix return values for VLAN_TAG_PRESENT case
MIPS: bpf: Use correct mask for VLAN_TAG case
MIPS: bpf: Fix branch conditional for BPF_J{GT/GE} cases
MIPS: bpf: Add SEEN_SKB to flags when looking for the PKT_TYPE
MIPS: bpf: Use 'andi' instead of 'and' for the VLAN cases
MIPS: bpf: Return error code if the offset is a negative number
MIPS: bpf: Use the LO register to get division's quotient
MIPS: mm: uasm: Fix lh micro-assembler instruction
MIPS: uasm: Add SLT uasm instruction
MIPS: uasm: Add s3s1s2 instruction builder
...
+211
-499
+1
arch/mips/Kconfig
+1
arch/mips/Kconfig
-2
arch/mips/include/asm/sigcontext.h
-2
arch/mips/include/asm/sigcontext.h
+4
arch/mips/include/asm/uasm.h
+4
arch/mips/include/asm/uasm.h
···
67
67
#define Ip_u2s3u1(op) \
68
68
void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
69
69
70
+
#define Ip_s3s1s2(op) \
71
+
void ISAOPC(op)(u32 **buf, int a, int b, int c)
72
+
70
73
#define Ip_u2u1s3(op) \
71
74
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
72
75
···
150
147
Ip_u2s3u1(_sd);
151
148
Ip_u2u1u3(_sll);
152
149
Ip_u3u2u1(_sllv);
150
+
Ip_s3s1s2(_slt);
153
151
Ip_u2u1s3(_sltiu);
154
152
Ip_u3u1u2(_sltu);
155
153
Ip_u2u1u3(_sra);
+1
arch/mips/include/uapi/asm/inst.h
+1
arch/mips/include/uapi/asm/inst.h
-8
arch/mips/include/uapi/asm/sigcontext.h
-8
arch/mips/include/uapi/asm/sigcontext.h
···
12
12
#include <linux/types.h>
13
13
#include <asm/sgidefs.h>
14
14
15
-
/* Bits which may be set in sc_used_math */
16
-
#define USEDMATH_FP (1 << 0)
17
-
#define USEDMATH_MSA (1 << 1)
18
-
19
15
#if _MIPS_SIM == _MIPS_SIM_ABI32
20
16
21
17
/*
···
37
41
unsigned long sc_lo2;
38
42
unsigned long sc_hi3;
39
43
unsigned long sc_lo3;
40
-
unsigned long long sc_msaregs[32]; /* Most significant 64 bits */
41
-
unsigned long sc_msa_csr;
42
44
};
43
45
44
46
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
···
70
76
__u32 sc_used_math;
71
77
__u32 sc_dsp;
72
78
__u32 sc_reserved;
73
-
__u64 sc_msaregs[32];
74
-
__u32 sc_msa_csr;
75
79
};
76
80
77
81
-3
arch/mips/kernel/asm-offsets.c
-3
arch/mips/kernel/asm-offsets.c
···
293
293
OFFSET(SC_LO2, sigcontext, sc_lo2);
294
294
OFFSET(SC_HI3, sigcontext, sc_hi3);
295
295
OFFSET(SC_LO3, sigcontext, sc_lo3);
296
-
OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
297
296
BLANK();
298
297
}
299
298
#endif
···
307
308
OFFSET(SC_MDLO, sigcontext, sc_mdlo);
308
309
OFFSET(SC_PC, sigcontext, sc_pc);
309
310
OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
310
-
OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
311
311
BLANK();
312
312
}
313
313
#endif
···
318
320
OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
319
321
OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
320
322
OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
321
-
OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
322
323
BLANK();
323
324
}
324
325
#endif
+1
-1
arch/mips/kernel/irq-msc01.c
+1
-1
arch/mips/kernel/irq-msc01.c
+2
-2
arch/mips/kernel/pm-cps.c
+2
-2
arch/mips/kernel/pm-cps.c
···
101
101
if (!coupled_coherence)
102
102
return;
103
103
104
-
smp_mb__before_atomic_inc();
104
+
smp_mb__before_atomic();
105
105
atomic_inc(a);
106
106
107
107
while (atomic_read(a) < online)
···
158
158
159
159
/* Indicate that this CPU might not be coherent */
160
160
cpumask_clear_cpu(cpu, &cpu_coherent_mask);
161
-
smp_mb__after_clear_bit();
161
+
smp_mb__after_atomic();
162
162
163
163
/* Create a non-coherent mapping of the core ready_count */
164
164
core_ready_count = per_cpu(ready_count, core);
-213
arch/mips/kernel/r4k_fpu.S
-213
arch/mips/kernel/r4k_fpu.S
···
13
13
* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
14
14
*/
15
15
#include <asm/asm.h>
16
-
#include <asm/asmmacro.h>
17
16
#include <asm/errno.h>
18
17
#include <asm/fpregdef.h>
19
18
#include <asm/mipsregs.h>
···
244
245
li v0, 0 # success
245
246
END(_restore_fp_context32)
246
247
#endif
247
-
248
-
#ifdef CONFIG_CPU_HAS_MSA
249
-
250
-
.macro save_sc_msareg wr, off, sc, tmp
251
-
#ifdef CONFIG_64BIT
252
-
copy_u_d \tmp, \wr, 1
253
-
EX sd \tmp, (\off+(\wr*8))(\sc)
254
-
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
255
-
copy_u_w \tmp, \wr, 2
256
-
EX sw \tmp, (\off+(\wr*8)+0)(\sc)
257
-
copy_u_w \tmp, \wr, 3
258
-
EX sw \tmp, (\off+(\wr*8)+4)(\sc)
259
-
#else /* CONFIG_CPU_BIG_ENDIAN */
260
-
copy_u_w \tmp, \wr, 2
261
-
EX sw \tmp, (\off+(\wr*8)+4)(\sc)
262
-
copy_u_w \tmp, \wr, 3
263
-
EX sw \tmp, (\off+(\wr*8)+0)(\sc)
264
-
#endif
265
-
.endm
266
-
267
-
/*
268
-
* int _save_msa_context(struct sigcontext *sc)
269
-
*
270
-
* Save the upper 64 bits of each vector register along with the MSA_CSR
271
-
* register into sc. Returns zero on success, else non-zero.
272
-
*/
273
-
LEAF(_save_msa_context)
274
-
save_sc_msareg 0, SC_MSAREGS, a0, t0
275
-
save_sc_msareg 1, SC_MSAREGS, a0, t0
276
-
save_sc_msareg 2, SC_MSAREGS, a0, t0
277
-
save_sc_msareg 3, SC_MSAREGS, a0, t0
278
-
save_sc_msareg 4, SC_MSAREGS, a0, t0
279
-
save_sc_msareg 5, SC_MSAREGS, a0, t0
280
-
save_sc_msareg 6, SC_MSAREGS, a0, t0
281
-
save_sc_msareg 7, SC_MSAREGS, a0, t0
282
-
save_sc_msareg 8, SC_MSAREGS, a0, t0
283
-
save_sc_msareg 9, SC_MSAREGS, a0, t0
284
-
save_sc_msareg 10, SC_MSAREGS, a0, t0
285
-
save_sc_msareg 11, SC_MSAREGS, a0, t0
286
-
save_sc_msareg 12, SC_MSAREGS, a0, t0
287
-
save_sc_msareg 13, SC_MSAREGS, a0, t0
288
-
save_sc_msareg 14, SC_MSAREGS, a0, t0
289
-
save_sc_msareg 15, SC_MSAREGS, a0, t0
290
-
save_sc_msareg 16, SC_MSAREGS, a0, t0
291
-
save_sc_msareg 17, SC_MSAREGS, a0, t0
292
-
save_sc_msareg 18, SC_MSAREGS, a0, t0
293
-
save_sc_msareg 19, SC_MSAREGS, a0, t0
294
-
save_sc_msareg 20, SC_MSAREGS, a0, t0
295
-
save_sc_msareg 21, SC_MSAREGS, a0, t0
296
-
save_sc_msareg 22, SC_MSAREGS, a0, t0
297
-
save_sc_msareg 23, SC_MSAREGS, a0, t0
298
-
save_sc_msareg 24, SC_MSAREGS, a0, t0
299
-
save_sc_msareg 25, SC_MSAREGS, a0, t0
300
-
save_sc_msareg 26, SC_MSAREGS, a0, t0
301
-
save_sc_msareg 27, SC_MSAREGS, a0, t0
302
-
save_sc_msareg 28, SC_MSAREGS, a0, t0
303
-
save_sc_msareg 29, SC_MSAREGS, a0, t0
304
-
save_sc_msareg 30, SC_MSAREGS, a0, t0
305
-
save_sc_msareg 31, SC_MSAREGS, a0, t0
306
-
jr ra
307
-
li v0, 0
308
-
END(_save_msa_context)
309
-
310
-
#ifdef CONFIG_MIPS32_COMPAT
311
-
312
-
/*
313
-
* int _save_msa_context32(struct sigcontext32 *sc)
314
-
*
315
-
* Save the upper 64 bits of each vector register along with the MSA_CSR
316
-
* register into sc. Returns zero on success, else non-zero.
317
-
*/
318
-
LEAF(_save_msa_context32)
319
-
save_sc_msareg 0, SC32_MSAREGS, a0, t0
320
-
save_sc_msareg 1, SC32_MSAREGS, a0, t0
321
-
save_sc_msareg 2, SC32_MSAREGS, a0, t0
322
-
save_sc_msareg 3, SC32_MSAREGS, a0, t0
323
-
save_sc_msareg 4, SC32_MSAREGS, a0, t0
324
-
save_sc_msareg 5, SC32_MSAREGS, a0, t0
325
-
save_sc_msareg 6, SC32_MSAREGS, a0, t0
326
-
save_sc_msareg 7, SC32_MSAREGS, a0, t0
327
-
save_sc_msareg 8, SC32_MSAREGS, a0, t0
328
-
save_sc_msareg 9, SC32_MSAREGS, a0, t0
329
-
save_sc_msareg 10, SC32_MSAREGS, a0, t0
330
-
save_sc_msareg 11, SC32_MSAREGS, a0, t0
331
-
save_sc_msareg 12, SC32_MSAREGS, a0, t0
332
-
save_sc_msareg 13, SC32_MSAREGS, a0, t0
333
-
save_sc_msareg 14, SC32_MSAREGS, a0, t0
334
-
save_sc_msareg 15, SC32_MSAREGS, a0, t0
335
-
save_sc_msareg 16, SC32_MSAREGS, a0, t0
336
-
save_sc_msareg 17, SC32_MSAREGS, a0, t0
337
-
save_sc_msareg 18, SC32_MSAREGS, a0, t0
338
-
save_sc_msareg 19, SC32_MSAREGS, a0, t0
339
-
save_sc_msareg 20, SC32_MSAREGS, a0, t0
340
-
save_sc_msareg 21, SC32_MSAREGS, a0, t0
341
-
save_sc_msareg 22, SC32_MSAREGS, a0, t0
342
-
save_sc_msareg 23, SC32_MSAREGS, a0, t0
343
-
save_sc_msareg 24, SC32_MSAREGS, a0, t0
344
-
save_sc_msareg 25, SC32_MSAREGS, a0, t0
345
-
save_sc_msareg 26, SC32_MSAREGS, a0, t0
346
-
save_sc_msareg 27, SC32_MSAREGS, a0, t0
347
-
save_sc_msareg 28, SC32_MSAREGS, a0, t0
348
-
save_sc_msareg 29, SC32_MSAREGS, a0, t0
349
-
save_sc_msareg 30, SC32_MSAREGS, a0, t0
350
-
save_sc_msareg 31, SC32_MSAREGS, a0, t0
351
-
jr ra
352
-
li v0, 0
353
-
END(_save_msa_context32)
354
-
355
-
#endif /* CONFIG_MIPS32_COMPAT */
356
-
357
-
.macro restore_sc_msareg wr, off, sc, tmp
358
-
#ifdef CONFIG_64BIT
359
-
EX ld \tmp, (\off+(\wr*8))(\sc)
360
-
insert_d \wr, 1, \tmp
361
-
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
362
-
EX lw \tmp, (\off+(\wr*8)+0)(\sc)
363
-
insert_w \wr, 2, \tmp
364
-
EX lw \tmp, (\off+(\wr*8)+4)(\sc)
365
-
insert_w \wr, 3, \tmp
366
-
#else /* CONFIG_CPU_BIG_ENDIAN */
367
-
EX lw \tmp, (\off+(\wr*8)+4)(\sc)
368
-
insert_w \wr, 2, \tmp
369
-
EX lw \tmp, (\off+(\wr*8)+0)(\sc)
370
-
insert_w \wr, 3, \tmp
371
-
#endif
372
-
.endm
373
-
374
-
/*
375
-
* int _restore_msa_context(struct sigcontext *sc)
376
-
*/
377
-
LEAF(_restore_msa_context)
378
-
restore_sc_msareg 0, SC_MSAREGS, a0, t0
379
-
restore_sc_msareg 1, SC_MSAREGS, a0, t0
380
-
restore_sc_msareg 2, SC_MSAREGS, a0, t0
381
-
restore_sc_msareg 3, SC_MSAREGS, a0, t0
382
-
restore_sc_msareg 4, SC_MSAREGS, a0, t0
383
-
restore_sc_msareg 5, SC_MSAREGS, a0, t0
384
-
restore_sc_msareg 6, SC_MSAREGS, a0, t0
385
-
restore_sc_msareg 7, SC_MSAREGS, a0, t0
386
-
restore_sc_msareg 8, SC_MSAREGS, a0, t0
387
-
restore_sc_msareg 9, SC_MSAREGS, a0, t0
388
-
restore_sc_msareg 10, SC_MSAREGS, a0, t0
389
-
restore_sc_msareg 11, SC_MSAREGS, a0, t0
390
-
restore_sc_msareg 12, SC_MSAREGS, a0, t0
391
-
restore_sc_msareg 13, SC_MSAREGS, a0, t0
392
-
restore_sc_msareg 14, SC_MSAREGS, a0, t0
393
-
restore_sc_msareg 15, SC_MSAREGS, a0, t0
394
-
restore_sc_msareg 16, SC_MSAREGS, a0, t0
395
-
restore_sc_msareg 17, SC_MSAREGS, a0, t0
396
-
restore_sc_msareg 18, SC_MSAREGS, a0, t0
397
-
restore_sc_msareg 19, SC_MSAREGS, a0, t0
398
-
restore_sc_msareg 20, SC_MSAREGS, a0, t0
399
-
restore_sc_msareg 21, SC_MSAREGS, a0, t0
400
-
restore_sc_msareg 22, SC_MSAREGS, a0, t0
401
-
restore_sc_msareg 23, SC_MSAREGS, a0, t0
402
-
restore_sc_msareg 24, SC_MSAREGS, a0, t0
403
-
restore_sc_msareg 25, SC_MSAREGS, a0, t0
404
-
restore_sc_msareg 26, SC_MSAREGS, a0, t0
405
-
restore_sc_msareg 27, SC_MSAREGS, a0, t0
406
-
restore_sc_msareg 28, SC_MSAREGS, a0, t0
407
-
restore_sc_msareg 29, SC_MSAREGS, a0, t0
408
-
restore_sc_msareg 30, SC_MSAREGS, a0, t0
409
-
restore_sc_msareg 31, SC_MSAREGS, a0, t0
410
-
jr ra
411
-
li v0, 0
412
-
END(_restore_msa_context)
413
-
414
-
#ifdef CONFIG_MIPS32_COMPAT
415
-
416
-
/*
417
-
* int _restore_msa_context32(struct sigcontext32 *sc)
418
-
*/
419
-
LEAF(_restore_msa_context32)
420
-
restore_sc_msareg 0, SC32_MSAREGS, a0, t0
421
-
restore_sc_msareg 1, SC32_MSAREGS, a0, t0
422
-
restore_sc_msareg 2, SC32_MSAREGS, a0, t0
423
-
restore_sc_msareg 3, SC32_MSAREGS, a0, t0
424
-
restore_sc_msareg 4, SC32_MSAREGS, a0, t0
425
-
restore_sc_msareg 5, SC32_MSAREGS, a0, t0
426
-
restore_sc_msareg 6, SC32_MSAREGS, a0, t0
427
-
restore_sc_msareg 7, SC32_MSAREGS, a0, t0
428
-
restore_sc_msareg 8, SC32_MSAREGS, a0, t0
429
-
restore_sc_msareg 9, SC32_MSAREGS, a0, t0
430
-
restore_sc_msareg 10, SC32_MSAREGS, a0, t0
431
-
restore_sc_msareg 11, SC32_MSAREGS, a0, t0
432
-
restore_sc_msareg 12, SC32_MSAREGS, a0, t0
433
-
restore_sc_msareg 13, SC32_MSAREGS, a0, t0
434
-
restore_sc_msareg 14, SC32_MSAREGS, a0, t0
435
-
restore_sc_msareg 15, SC32_MSAREGS, a0, t0
436
-
restore_sc_msareg 16, SC32_MSAREGS, a0, t0
437
-
restore_sc_msareg 17, SC32_MSAREGS, a0, t0
438
-
restore_sc_msareg 18, SC32_MSAREGS, a0, t0
439
-
restore_sc_msareg 19, SC32_MSAREGS, a0, t0
440
-
restore_sc_msareg 20, SC32_MSAREGS, a0, t0
441
-
restore_sc_msareg 21, SC32_MSAREGS, a0, t0
442
-
restore_sc_msareg 22, SC32_MSAREGS, a0, t0
443
-
restore_sc_msareg 23, SC32_MSAREGS, a0, t0
444
-
restore_sc_msareg 24, SC32_MSAREGS, a0, t0
445
-
restore_sc_msareg 25, SC32_MSAREGS, a0, t0
446
-
restore_sc_msareg 26, SC32_MSAREGS, a0, t0
447
-
restore_sc_msareg 27, SC32_MSAREGS, a0, t0
448
-
restore_sc_msareg 28, SC32_MSAREGS, a0, t0
449
-
restore_sc_msareg 29, SC32_MSAREGS, a0, t0
450
-
restore_sc_msareg 30, SC32_MSAREGS, a0, t0
451
-
restore_sc_msareg 31, SC32_MSAREGS, a0, t0
452
-
jr ra
453
-
li v0, 0
454
-
END(_restore_msa_context32)
455
-
456
-
#endif /* CONFIG_MIPS32_COMPAT */
457
-
458
-
#endif /* CONFIG_CPU_HAS_MSA */
459
248
460
249
.set reorder
461
250
+8
-71
arch/mips/kernel/signal.c
+8
-71
arch/mips/kernel/signal.c
···
31
31
#include <linux/bitops.h>
32
32
#include <asm/cacheflush.h>
33
33
#include <asm/fpu.h>
34
-
#include <asm/msa.h>
35
34
#include <asm/sim.h>
36
35
#include <asm/ucontext.h>
37
36
#include <asm/cpu-features.h>
···
46
47
47
48
extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
48
49
extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
49
-
50
-
extern asmlinkage int _save_msa_context(struct sigcontext __user *sc);
51
-
extern asmlinkage int _restore_msa_context(struct sigcontext __user *sc);
52
50
53
51
struct sigframe {
54
52
u32 sf_ass[4]; /* argument save space for o32 */
···
96
100
}
97
101
98
102
/*
99
-
* These functions will save only the upper 64 bits of the vector registers,
100
-
* since the lower 64 bits have already been saved as the scalar FP context.
101
-
*/
102
-
static int copy_msa_to_sigcontext(struct sigcontext __user *sc)
103
-
{
104
-
int i;
105
-
int err = 0;
106
-
107
-
for (i = 0; i < NUM_FPU_REGS; i++) {
108
-
err |=
109
-
__put_user(get_fpr64(¤t->thread.fpu.fpr[i], 1),
110
-
&sc->sc_msaregs[i]);
111
-
}
112
-
err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
113
-
114
-
return err;
115
-
}
116
-
117
-
static int copy_msa_from_sigcontext(struct sigcontext __user *sc)
118
-
{
119
-
int i;
120
-
int err = 0;
121
-
u64 val;
122
-
123
-
for (i = 0; i < NUM_FPU_REGS; i++) {
124
-
err |= __get_user(val, &sc->sc_msaregs[i]);
125
-
set_fpr64(¤t->thread.fpu.fpr[i], 1, val);
126
-
}
127
-
err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
128
-
129
-
return err;
130
-
}
131
-
132
-
/*
133
103
* Helper routines
134
104
*/
135
-
static int protected_save_fp_context(struct sigcontext __user *sc,
136
-
unsigned used_math)
105
+
static int protected_save_fp_context(struct sigcontext __user *sc)
137
106
{
138
107
int err;
139
-
bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
140
108
#ifndef CONFIG_EVA
141
109
while (1) {
142
110
lock_fpu_owner();
143
111
if (is_fpu_owner()) {
144
112
err = save_fp_context(sc);
145
-
if (save_msa && !err)
146
-
err = _save_msa_context(sc);
147
113
unlock_fpu_owner();
148
114
} else {
149
115
unlock_fpu_owner();
150
116
err = copy_fp_to_sigcontext(sc);
151
-
if (save_msa && !err)
152
-
err = copy_msa_to_sigcontext(sc);
153
117
}
154
118
if (likely(!err))
155
119
break;
···
125
169
* EVA does not have FPU EVA instructions so saving fpu context directly
126
170
* does not work.
127
171
*/
128
-
disable_msa();
129
172
lose_fpu(1);
130
173
err = save_fp_context(sc); /* this might fail */
131
-
if (save_msa && !err)
132
-
err = copy_msa_to_sigcontext(sc);
133
174
#endif
134
175
return err;
135
176
}
136
177
137
-
static int protected_restore_fp_context(struct sigcontext __user *sc,
138
-
unsigned used_math)
178
+
static int protected_restore_fp_context(struct sigcontext __user *sc)
139
179
{
140
180
int err, tmp __maybe_unused;
141
-
bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
142
181
#ifndef CONFIG_EVA
143
182
while (1) {
144
183
lock_fpu_owner();
145
184
if (is_fpu_owner()) {
146
185
err = restore_fp_context(sc);
147
-
if (restore_msa && !err) {
148
-
enable_msa();
149
-
err = _restore_msa_context(sc);
150
-
} else {
151
-
/* signal handler may have used MSA */
152
-
disable_msa();
153
-
}
154
186
unlock_fpu_owner();
155
187
} else {
156
188
unlock_fpu_owner();
157
189
err = copy_fp_from_sigcontext(sc);
158
-
if (!err && (used_math & USEDMATH_MSA))
159
-
err = copy_msa_from_sigcontext(sc);
160
190
}
161
191
if (likely(!err))
162
192
break;
···
158
216
* EVA does not have FPU EVA instructions so restoring fpu context
159
217
* directly does not work.
160
218
*/
161
-
enable_msa();
162
219
lose_fpu(0);
163
220
err = restore_fp_context(sc); /* this might fail */
164
-
if (restore_msa && !err)
165
-
err = copy_msa_from_sigcontext(sc);
166
221
#endif
167
222
return err;
168
223
}
···
191
252
err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
192
253
}
193
254
194
-
used_math = used_math() ? USEDMATH_FP : 0;
195
-
used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
255
+
used_math = !!used_math();
196
256
err |= __put_user(used_math, &sc->sc_used_math);
197
257
198
258
if (used_math) {
···
199
261
* Save FPU state to signal context. Signal handler
200
262
* will "inherit" current FPU state.
201
263
*/
202
-
err |= protected_save_fp_context(sc, used_math);
264
+
err |= protected_save_fp_context(sc);
203
265
}
204
266
return err;
205
267
}
···
224
286
}
225
287
226
288
static int
227
-
check_and_restore_fp_context(struct sigcontext __user *sc, unsigned used_math)
289
+
check_and_restore_fp_context(struct sigcontext __user *sc)
228
290
{
229
291
int err, sig;
230
292
231
293
err = sig = fpcsr_pending(&sc->sc_fpc_csr);
232
294
if (err > 0)
233
295
err = 0;
234
-
err |= protected_restore_fp_context(sc, used_math);
296
+
err |= protected_restore_fp_context(sc);
235
297
return err ?: sig;
236
298
}
237
299
···
271
333
if (used_math) {
272
334
/* restore fpu context if we have used it before */
273
335
if (!err)
274
-
err = check_and_restore_fp_context(sc, used_math);
336
+
err = check_and_restore_fp_context(sc);
275
337
} else {
276
-
/* signal handler may have used FPU or MSA. Disable them. */
277
-
disable_msa();
338
+
/* signal handler may have used FPU. Give it up. */
278
339
lose_fpu(0);
279
340
}
280
341
+8
-66
arch/mips/kernel/signal32.c
+8
-66
arch/mips/kernel/signal32.c
···
30
30
#include <asm/sim.h>
31
31
#include <asm/ucontext.h>
32
32
#include <asm/fpu.h>
33
-
#include <asm/msa.h>
34
33
#include <asm/war.h>
35
34
#include <asm/vdso.h>
36
35
#include <asm/dsp.h>
···
41
42
42
43
extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
43
44
extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
44
-
45
-
extern asmlinkage int _save_msa_context32(struct sigcontext32 __user *sc);
46
-
extern asmlinkage int _restore_msa_context32(struct sigcontext32 __user *sc);
47
45
48
46
/*
49
47
* Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
···
111
115
}
112
116
113
117
/*
114
-
* These functions will save only the upper 64 bits of the vector registers,
115
-
* since the lower 64 bits have already been saved as the scalar FP context.
116
-
*/
117
-
static int copy_msa_to_sigcontext32(struct sigcontext32 __user *sc)
118
-
{
119
-
int i;
120
-
int err = 0;
121
-
122
-
for (i = 0; i < NUM_FPU_REGS; i++) {
123
-
err |=
124
-
__put_user(get_fpr64(¤t->thread.fpu.fpr[i], 1),
125
-
&sc->sc_msaregs[i]);
126
-
}
127
-
err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
128
-
129
-
return err;
130
-
}
131
-
132
-
static int copy_msa_from_sigcontext32(struct sigcontext32 __user *sc)
133
-
{
134
-
int i;
135
-
int err = 0;
136
-
u64 val;
137
-
138
-
for (i = 0; i < NUM_FPU_REGS; i++) {
139
-
err |= __get_user(val, &sc->sc_msaregs[i]);
140
-
set_fpr64(¤t->thread.fpu.fpr[i], 1, val);
141
-
}
142
-
err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
143
-
144
-
return err;
145
-
}
146
-
147
-
/*
148
118
* sigcontext handlers
149
119
*/
150
-
static int protected_save_fp_context32(struct sigcontext32 __user *sc,
151
-
unsigned used_math)
120
+
static int protected_save_fp_context32(struct sigcontext32 __user *sc)
152
121
{
153
122
int err;
154
-
bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
155
123
while (1) {
156
124
lock_fpu_owner();
157
125
if (is_fpu_owner()) {
158
126
err = save_fp_context32(sc);
159
-
if (save_msa && !err)
160
-
err = _save_msa_context32(sc);
161
127
unlock_fpu_owner();
162
128
} else {
163
129
unlock_fpu_owner();
164
130
err = copy_fp_to_sigcontext32(sc);
165
-
if (save_msa && !err)
166
-
err = copy_msa_to_sigcontext32(sc);
167
131
}
168
132
if (likely(!err))
169
133
break;
···
137
181
return err;
138
182
}
139
183
140
-
static int protected_restore_fp_context32(struct sigcontext32 __user *sc,
141
-
unsigned used_math)
184
+
static int protected_restore_fp_context32(struct sigcontext32 __user *sc)
142
185
{
143
186
int err, tmp __maybe_unused;
144
-
bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
145
187
while (1) {
146
188
lock_fpu_owner();
147
189
if (is_fpu_owner()) {
148
190
err = restore_fp_context32(sc);
149
-
if (restore_msa && !err) {
150
-
enable_msa();
151
-
err = _restore_msa_context32(sc);
152
-
} else {
153
-
/* signal handler may have used MSA */
154
-
disable_msa();
155
-
}
156
191
unlock_fpu_owner();
157
192
} else {
158
193
unlock_fpu_owner();
159
194
err = copy_fp_from_sigcontext32(sc);
160
-
if (restore_msa && !err)
161
-
err = copy_msa_from_sigcontext32(sc);
162
195
}
163
196
if (likely(!err))
164
197
break;
···
186
241
err |= __put_user(mflo3(), &sc->sc_lo3);
187
242
}
188
243
189
-
used_math = used_math() ? USEDMATH_FP : 0;
190
-
used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
244
+
used_math = !!used_math();
191
245
err |= __put_user(used_math, &sc->sc_used_math);
192
246
193
247
if (used_math) {
···
194
250
* Save FPU state to signal context. Signal handler
195
251
* will "inherit" current FPU state.
196
252
*/
197
-
err |= protected_save_fp_context32(sc, used_math);
253
+
err |= protected_save_fp_context32(sc);
198
254
}
199
255
return err;
200
256
}
201
257
202
258
static int
203
-
check_and_restore_fp_context32(struct sigcontext32 __user *sc,
204
-
unsigned used_math)
259
+
check_and_restore_fp_context32(struct sigcontext32 __user *sc)
205
260
{
206
261
int err, sig;
207
262
208
263
err = sig = fpcsr_pending(&sc->sc_fpc_csr);
209
264
if (err > 0)
210
265
err = 0;
211
-
err |= protected_restore_fp_context32(sc, used_math);
266
+
err |= protected_restore_fp_context32(sc);
212
267
return err ?: sig;
213
268
}
214
269
···
244
301
if (used_math) {
245
302
/* restore fpu context if we have used it before */
246
303
if (!err)
247
-
err = check_and_restore_fp_context32(sc, used_math);
304
+
err = check_and_restore_fp_context32(sc);
248
305
} else {
249
-
/* signal handler may have used FPU or MSA. Disable them. */
250
-
disable_msa();
306
+
/* signal handler may have used FPU. Give it up. */
251
307
lose_fpu(0);
252
308
}
253
309
+1
-1
arch/mips/kernel/smp-cps.c
+1
-1
arch/mips/kernel/smp-cps.c
···
301
301
302
302
core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
303
303
atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
304
-
smp_mb__after_atomic_dec();
304
+
smp_mb__after_atomic();
305
305
set_cpu_online(cpu, false);
306
306
cpu_clear(cpu, cpu_callin_map);
307
307
+14
-9
arch/mips/math-emu/ieee754.c
+14
-9
arch/mips/math-emu/ieee754.c
···
34
34
* Special constants
35
35
*/
36
36
37
-
#define DPCNST(s, b, m) \
37
+
/*
38
+
* Older GCC requires the inner braces for initialization of union ieee754dp's
39
+
* anonymous struct member. Without an error will result.
40
+
*/
41
+
#define xPCNST(s, b, m, ebias) \
38
42
{ \
39
-
.sign = (s), \
40
-
.bexp = (b) + DP_EBIAS, \
41
-
.mant = (m) \
43
+
{ \
44
+
.sign = (s), \
45
+
.bexp = (b) + ebias, \
46
+
.mant = (m) \
47
+
} \
42
48
}
49
+
50
+
#define DPCNST(s, b, m) \
51
+
xPCNST(s, b, m, DP_EBIAS)
43
52
44
53
const union ieee754dp __ieee754dp_spcvals[] = {
45
54
DPCNST(0, DP_EMIN - 1, 0x0000000000000ULL), /* + zero */
···
71
62
};
72
63
73
64
#define SPCNST(s, b, m) \
74
-
{ \
75
-
.sign = (s), \
76
-
.bexp = (b) + SP_EBIAS, \
77
-
.mant = (m) \
78
-
}
65
+
xPCNST(s, b, m, SP_EBIAS)
79
66
80
67
const union ieee754sp __ieee754sp_spcvals[] = {
81
68
SPCNST(0, SP_EMIN - 1, 0x000000), /* + zero */
+1
arch/mips/mm/uasm-micromips.c
+1
arch/mips/mm/uasm-micromips.c
···
102
102
{ insn_sd, 0, 0 },
103
103
{ insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
104
104
{ insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
105
+
{ insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },
105
106
{ insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
106
107
{ insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },
107
108
{ insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
+2
-1
arch/mips/mm/uasm-mips.c
+2
-1
arch/mips/mm/uasm-mips.c
···
89
89
{ insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
90
90
{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
91
91
{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
92
-
{ insn_lh, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
92
+
{ insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
93
93
{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
94
94
{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
95
95
{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
···
110
110
{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
111
111
{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
112
112
{ insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD },
113
+
{ insn_slt, M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD },
113
114
{ insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
114
115
{ insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
115
116
{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
+9
-1
arch/mips/mm/uasm.c
+9
-1
arch/mips/mm/uasm.c
···
53
53
insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
54
54
insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul,
55
55
insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
56
-
insn_sd, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra,
56
+
insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,
57
57
insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
58
58
insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
59
59
insn_xor, insn_xori, insn_yield,
···
136
136
Ip_u1u2u3(op) \
137
137
{ \
138
138
build_insn(buf, insn##op, a, b, c); \
139
+
} \
140
+
UASM_EXPORT_SYMBOL(uasm_i##op);
141
+
142
+
#define I_s3s1s2(op) \
143
+
Ip_s3s1s2(op) \
144
+
{ \
145
+
build_insn(buf, insn##op, b, c, a); \
139
146
} \
140
147
UASM_EXPORT_SYMBOL(uasm_i##op);
141
148
···
296
289
I_u2s3u1(_sd)
297
290
I_u2u1u3(_sll)
298
291
I_u3u2u1(_sllv)
292
+
I_s3s1s2(_slt)
299
293
I_u2u1s3(_sltiu)
300
294
I_u3u1u2(_sltu)
301
295
I_u2u1u3(_sra)
+149
-117
arch/mips/net/bpf_jit.c
+149
-117
arch/mips/net/bpf_jit.c
···
119
119
/* Arguments used by JIT */
120
120
#define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */
121
121
122
-
#define FLAG_NEED_X_RESET (1 << 0)
123
-
124
122
#define SBIT(x) (1 << (x)) /* Signed version of BIT() */
125
123
126
124
/**
···
151
153
return 0;
152
154
}
153
155
156
+
static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx);
157
+
154
158
/* Simply emit the instruction if the JIT memory space has been allocated */
155
159
#define emit_instr(ctx, func, ...) \
156
160
do { \
···
166
166
/* Determine if immediate is within the 16-bit signed range */
167
167
static inline bool is_range16(s32 imm)
168
168
{
169
-
if (imm >= SBIT(15) || imm < -SBIT(15))
170
-
return true;
171
-
return false;
169
+
return !(imm >= SBIT(15) || imm < -SBIT(15));
172
170
}
173
171
174
172
static inline void emit_addu(unsigned int dst, unsigned int src1,
···
185
187
{
186
188
if (ctx->target != NULL) {
187
189
/* addiu can only handle s16 */
188
-
if (is_range16(imm)) {
190
+
if (!is_range16(imm)) {
189
191
u32 *p = &ctx->target[ctx->idx];
190
192
uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16);
191
193
p = &ctx->target[ctx->idx + 1];
···
197
199
}
198
200
ctx->idx++;
199
201
200
-
if (is_range16(imm))
202
+
if (!is_range16(imm))
201
203
ctx->idx++;
202
204
}
203
205
···
238
240
static inline void emit_addiu(unsigned int dst, unsigned int src,
239
241
u32 imm, struct jit_ctx *ctx)
240
242
{
241
-
if (is_range16(imm)) {
243
+
if (!is_range16(imm)) {
242
244
emit_load_imm(r_tmp, imm, ctx);
243
245
emit_addu(dst, r_tmp, src, ctx);
244
246
} else {
···
311
313
unsigned int sa, struct jit_ctx *ctx)
312
314
{
313
315
/* sa is 5-bits long */
314
-
BUG_ON(sa >= BIT(5));
315
-
emit_instr(ctx, sll, dst, src, sa);
316
+
if (sa >= BIT(5))
317
+
/* Shifting >= 32 results in zero */
318
+
emit_jit_reg_move(dst, r_zero, ctx);
319
+
else
320
+
emit_instr(ctx, sll, dst, src, sa);
316
321
}
317
322
318
323
static inline void emit_srlv(unsigned int dst, unsigned int src,
···
328
327
unsigned int sa, struct jit_ctx *ctx)
329
328
{
330
329
/* sa is 5-bits long */
331
-
BUG_ON(sa >= BIT(5));
332
-
emit_instr(ctx, srl, dst, src, sa);
330
+
if (sa >= BIT(5))
331
+
/* Shifting >= 32 results in zero */
332
+
emit_jit_reg_move(dst, r_zero, ctx);
333
+
else
334
+
emit_instr(ctx, srl, dst, src, sa);
335
+
}
336
+
337
+
static inline void emit_slt(unsigned int dst, unsigned int src1,
338
+
unsigned int src2, struct jit_ctx *ctx)
339
+
{
340
+
emit_instr(ctx, slt, dst, src1, src2);
333
341
}
334
342
335
343
static inline void emit_sltu(unsigned int dst, unsigned int src1,
···
351
341
unsigned int imm, struct jit_ctx *ctx)
352
342
{
353
343
/* 16 bit immediate */
354
-
if (is_range16((s32)imm)) {
344
+
if (!is_range16((s32)imm)) {
355
345
emit_load_imm(r_tmp, imm, ctx);
356
346
emit_sltu(dst, src, r_tmp, ctx);
357
347
} else {
···
418
408
u32 *p = &ctx->target[ctx->idx];
419
409
uasm_i_divu(&p, dst, src);
420
410
p = &ctx->target[ctx->idx + 1];
421
-
uasm_i_mfhi(&p, dst);
411
+
uasm_i_mflo(&p, dst);
422
412
}
423
413
ctx->idx += 2; /* 2 insts */
424
414
}
···
451
441
struct jit_ctx *ctx)
452
442
{
453
443
emit_instr(ctx, wsbh, dst, src);
444
+
}
445
+
446
+
/* load pointer to register */
447
+
static inline void emit_load_ptr(unsigned int dst, unsigned int src,
448
+
int imm, struct jit_ctx *ctx)
449
+
{
450
+
/* src contains the base addr of the 32/64-pointer */
451
+
if (config_enabled(CONFIG_64BIT))
452
+
emit_instr(ctx, ld, dst, imm, src);
453
+
else
454
+
emit_instr(ctx, lw, dst, imm, src);
454
455
}
455
456
456
457
/* load a function pointer to register */
···
566
545
return num;
567
546
}
568
547
569
-
static inline void update_on_xread(struct jit_ctx *ctx)
570
-
{
571
-
if (!(ctx->flags & SEEN_X))
572
-
ctx->flags |= FLAG_NEED_X_RESET;
573
-
574
-
ctx->flags |= SEEN_X;
575
-
}
576
-
577
548
static bool is_load_to_a(u16 inst)
578
549
{
579
550
switch (inst) {
580
-
case BPF_S_LD_W_LEN:
581
-
case BPF_S_LD_W_ABS:
582
-
case BPF_S_LD_H_ABS:
583
-
case BPF_S_LD_B_ABS:
584
-
case BPF_S_ANC_CPU:
585
-
case BPF_S_ANC_IFINDEX:
586
-
case BPF_S_ANC_MARK:
587
-
case BPF_S_ANC_PROTOCOL:
588
-
case BPF_S_ANC_RXHASH:
589
-
case BPF_S_ANC_VLAN_TAG:
590
-
case BPF_S_ANC_VLAN_TAG_PRESENT:
591
-
case BPF_S_ANC_QUEUE:
551
+
case BPF_LD | BPF_W | BPF_LEN:
552
+
case BPF_LD | BPF_W | BPF_ABS:
553
+
case BPF_LD | BPF_H | BPF_ABS:
554
+
case BPF_LD | BPF_B | BPF_ABS:
592
555
return true;
593
556
default:
594
557
return false;
···
623
618
if (ctx->flags & SEEN_MEM) {
624
619
if (real_off % (RSIZE * 2))
625
620
real_off += RSIZE;
626
-
emit_addiu(r_M, r_sp, real_off, ctx);
621
+
if (config_enabled(CONFIG_64BIT))
622
+
emit_daddiu(r_M, r_sp, real_off, ctx);
623
+
else
624
+
emit_addiu(r_M, r_sp, real_off, ctx);
627
625
}
628
626
}
629
627
···
713
705
if (ctx->flags & SEEN_SKB)
714
706
emit_reg_move(r_skb, MIPS_R_A0, ctx);
715
707
716
-
if (ctx->flags & FLAG_NEED_X_RESET)
708
+
if (ctx->flags & SEEN_X)
717
709
emit_jit_reg_move(r_X, r_zero, ctx);
718
710
719
711
/* Do not leak kernel data to userspace */
720
-
if ((first_inst != BPF_S_RET_K) && !(is_load_to_a(first_inst)))
712
+
if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst)))
721
713
emit_jit_reg_move(r_A, r_zero, ctx);
722
714
}
723
715
···
765
757
return (u64)err << 32 | ntohl(ret);
766
758
}
767
759
768
-
#define PKT_TYPE_MAX 7
760
+
#ifdef __BIG_ENDIAN_BITFIELD
761
+
#define PKT_TYPE_MAX (7 << 5)
762
+
#else
763
+
#define PKT_TYPE_MAX 7
764
+
#endif
769
765
static int pkt_type_offset(void)
770
766
{
771
767
struct sk_buff skb_probe = {
772
768
.pkt_type = ~0,
773
769
};
774
-
char *ct = (char *)&skb_probe;
770
+
u8 *ct = (u8 *)&skb_probe;
775
771
unsigned int off;
776
772
777
773
for (off = 0; off < sizeof(struct sk_buff); off++) {
···
795
783
u32 k, b_off __maybe_unused;
796
784
797
785
for (i = 0; i < prog->len; i++) {
786
+
u16 code;
787
+
798
788
inst = &(prog->insns[i]);
799
789
pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n",
800
790
__func__, inst->code, inst->jt, inst->jf, inst->k);
801
791
k = inst->k;
792
+
code = bpf_anc_helper(inst);
802
793
803
794
if (ctx->target == NULL)
804
795
ctx->offsets[i] = ctx->idx * 4;
805
796
806
-
switch (inst->code) {
807
-
case BPF_S_LD_IMM:
797
+
switch (code) {
798
+
case BPF_LD | BPF_IMM:
808
799
/* A <- k ==> li r_A, k */
809
800
ctx->flags |= SEEN_A;
810
801
emit_load_imm(r_A, k, ctx);
811
802
break;
812
-
case BPF_S_LD_W_LEN:
803
+
case BPF_LD | BPF_W | BPF_LEN:
813
804
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
814
805
/* A <- len ==> lw r_A, offset(skb) */
815
806
ctx->flags |= SEEN_SKB | SEEN_A;
816
807
off = offsetof(struct sk_buff, len);
817
808
emit_load(r_A, r_skb, off, ctx);
818
809
break;
819
-
case BPF_S_LD_MEM:
810
+
case BPF_LD | BPF_MEM:
820
811
/* A <- M[k] ==> lw r_A, offset(M) */
821
812
ctx->flags |= SEEN_MEM | SEEN_A;
822
813
emit_load(r_A, r_M, SCRATCH_OFF(k), ctx);
823
814
break;
824
-
case BPF_S_LD_W_ABS:
815
+
case BPF_LD | BPF_W | BPF_ABS:
825
816
/* A <- P[k:4] */
826
817
load_order = 2;
827
818
goto load;
828
-
case BPF_S_LD_H_ABS:
819
+
case BPF_LD | BPF_H | BPF_ABS:
829
820
/* A <- P[k:2] */
830
821
load_order = 1;
831
822
goto load;
832
-
case BPF_S_LD_B_ABS:
823
+
case BPF_LD | BPF_B | BPF_ABS:
833
824
/* A <- P[k:1] */
834
825
load_order = 0;
835
826
load:
827
+
/* the interpreter will deal with the negative K */
828
+
if ((int)k < 0)
829
+
return -ENOTSUPP;
830
+
836
831
emit_load_imm(r_off, k, ctx);
837
832
load_common:
833
+
/*
834
+
* We may got here from the indirect loads so
835
+
* return if offset is negative.
836
+
*/
837
+
emit_slt(r_s0, r_off, r_zero, ctx);
838
+
emit_bcond(MIPS_COND_NE, r_s0, r_zero,
839
+
b_imm(prog->len, ctx), ctx);
840
+
emit_reg_move(r_ret, r_zero, ctx);
841
+
838
842
ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
839
843
SEEN_SKB | SEEN_A;
840
844
···
880
852
emit_b(b_imm(prog->len, ctx), ctx);
881
853
emit_reg_move(r_ret, r_zero, ctx);
882
854
break;
883
-
case BPF_S_LD_W_IND:
855
+
case BPF_LD | BPF_W | BPF_IND:
884
856
/* A <- P[X + k:4] */
885
857
load_order = 2;
886
858
goto load_ind;
887
-
case BPF_S_LD_H_IND:
859
+
case BPF_LD | BPF_H | BPF_IND:
888
860
/* A <- P[X + k:2] */
889
861
load_order = 1;
890
862
goto load_ind;
891
-
case BPF_S_LD_B_IND:
863
+
case BPF_LD | BPF_B | BPF_IND:
892
864
/* A <- P[X + k:1] */
893
865
load_order = 0;
894
866
load_ind:
895
-
update_on_xread(ctx);
896
867
ctx->flags |= SEEN_OFF | SEEN_X;
897
868
emit_addiu(r_off, r_X, k, ctx);
898
869
goto load_common;
899
-
case BPF_S_LDX_IMM:
870
+
case BPF_LDX | BPF_IMM:
900
871
/* X <- k */
901
872
ctx->flags |= SEEN_X;
902
873
emit_load_imm(r_X, k, ctx);
903
874
break;
904
-
case BPF_S_LDX_MEM:
875
+
case BPF_LDX | BPF_MEM:
905
876
/* X <- M[k] */
906
877
ctx->flags |= SEEN_X | SEEN_MEM;
907
878
emit_load(r_X, r_M, SCRATCH_OFF(k), ctx);
908
879
break;
909
-
case BPF_S_LDX_W_LEN:
880
+
case BPF_LDX | BPF_W | BPF_LEN:
910
881
/* X <- len */
911
882
ctx->flags |= SEEN_X | SEEN_SKB;
912
883
off = offsetof(struct sk_buff, len);
913
884
emit_load(r_X, r_skb, off, ctx);
914
885
break;
915
-
case BPF_S_LDX_B_MSH:
886
+
case BPF_LDX | BPF_B | BPF_MSH:
887
+
/* the interpreter will deal with the negative K */
888
+
if ((int)k < 0)
889
+
return -ENOTSUPP;
890
+
916
891
/* X <- 4 * (P[k:1] & 0xf) */
917
892
ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
918
893
/* Load offset to a1 */
···
948
917
emit_b(b_imm(prog->len, ctx), ctx);
949
918
emit_load_imm(r_ret, 0, ctx); /* delay slot */
950
919
break;
951
-
case BPF_S_ST:
920
+
case BPF_ST:
952
921
/* M[k] <- A */
953
922
ctx->flags |= SEEN_MEM | SEEN_A;
954
923
emit_store(r_A, r_M, SCRATCH_OFF(k), ctx);
955
924
break;
956
-
case BPF_S_STX:
925
+
case BPF_STX:
957
926
/* M[k] <- X */
958
927
ctx->flags |= SEEN_MEM | SEEN_X;
959
928
emit_store(r_X, r_M, SCRATCH_OFF(k), ctx);
960
929
break;
961
-
case BPF_S_ALU_ADD_K:
930
+
case BPF_ALU | BPF_ADD | BPF_K:
962
931
/* A += K */
963
932
ctx->flags |= SEEN_A;
964
933
emit_addiu(r_A, r_A, k, ctx);
965
934
break;
966
-
case BPF_S_ALU_ADD_X:
935
+
case BPF_ALU | BPF_ADD | BPF_X:
967
936
/* A += X */
968
937
ctx->flags |= SEEN_A | SEEN_X;
969
938
emit_addu(r_A, r_A, r_X, ctx);
970
939
break;
971
-
case BPF_S_ALU_SUB_K:
940
+
case BPF_ALU | BPF_SUB | BPF_K:
972
941
/* A -= K */
973
942
ctx->flags |= SEEN_A;
974
943
emit_addiu(r_A, r_A, -k, ctx);
975
944
break;
976
-
case BPF_S_ALU_SUB_X:
945
+
case BPF_ALU | BPF_SUB | BPF_X:
977
946
/* A -= X */
978
947
ctx->flags |= SEEN_A | SEEN_X;
979
948
emit_subu(r_A, r_A, r_X, ctx);
980
949
break;
981
-
case BPF_S_ALU_MUL_K:
950
+
case BPF_ALU | BPF_MUL | BPF_K:
982
951
/* A *= K */
983
952
/* Load K to scratch register before MUL */
984
953
ctx->flags |= SEEN_A | SEEN_S0;
985
954
emit_load_imm(r_s0, k, ctx);
986
955
emit_mul(r_A, r_A, r_s0, ctx);
987
956
break;
988
-
case BPF_S_ALU_MUL_X:
957
+
case BPF_ALU | BPF_MUL | BPF_X:
989
958
/* A *= X */
990
-
update_on_xread(ctx);
991
959
ctx->flags |= SEEN_A | SEEN_X;
992
960
emit_mul(r_A, r_A, r_X, ctx);
993
961
break;
994
-
case BPF_S_ALU_DIV_K:
962
+
case BPF_ALU | BPF_DIV | BPF_K:
995
963
/* A /= k */
996
964
if (k == 1)
997
965
break;
···
1003
973
emit_load_imm(r_s0, k, ctx);
1004
974
emit_div(r_A, r_s0, ctx);
1005
975
break;
1006
-
case BPF_S_ALU_MOD_K:
976
+
case BPF_ALU | BPF_MOD | BPF_K:
1007
977
/* A %= k */
1008
978
if (k == 1 || optimize_div(&k)) {
1009
979
ctx->flags |= SEEN_A;
···
1014
984
emit_mod(r_A, r_s0, ctx);
1015
985
}
1016
986
break;
1017
-
case BPF_S_ALU_DIV_X:
987
+
case BPF_ALU | BPF_DIV | BPF_X:
1018
988
/* A /= X */
1019
-
update_on_xread(ctx);
1020
989
ctx->flags |= SEEN_X | SEEN_A;
1021
990
/* Check if r_X is zero */
1022
991
emit_bcond(MIPS_COND_EQ, r_X, r_zero,
···
1023
994
emit_load_imm(r_val, 0, ctx); /* delay slot */
1024
995
emit_div(r_A, r_X, ctx);
1025
996
break;
1026
-
case BPF_S_ALU_MOD_X:
997
+
case BPF_ALU | BPF_MOD | BPF_X:
1027
998
/* A %= X */
1028
-
update_on_xread(ctx);
1029
999
ctx->flags |= SEEN_X | SEEN_A;
1030
1000
/* Check if r_X is zero */
1031
1001
emit_bcond(MIPS_COND_EQ, r_X, r_zero,
···
1032
1004
emit_load_imm(r_val, 0, ctx); /* delay slot */
1033
1005
emit_mod(r_A, r_X, ctx);
1034
1006
break;
1035
-
case BPF_S_ALU_OR_K:
1007
+
case BPF_ALU | BPF_OR | BPF_K:
1036
1008
/* A |= K */
1037
1009
ctx->flags |= SEEN_A;
1038
1010
emit_ori(r_A, r_A, k, ctx);
1039
1011
break;
1040
-
case BPF_S_ALU_OR_X:
1012
+
case BPF_ALU | BPF_OR | BPF_X:
1041
1013
/* A |= X */
1042
-
update_on_xread(ctx);
1043
1014
ctx->flags |= SEEN_A;
1044
1015
emit_ori(r_A, r_A, r_X, ctx);
1045
1016
break;
1046
-
case BPF_S_ALU_XOR_K:
1017
+
case BPF_ALU | BPF_XOR | BPF_K:
1047
1018
/* A ^= k */
1048
1019
ctx->flags |= SEEN_A;
1049
1020
emit_xori(r_A, r_A, k, ctx);
1050
1021
break;
1051
-
case BPF_S_ANC_ALU_XOR_X:
1052
-
case BPF_S_ALU_XOR_X:
1022
+
case BPF_ANC | SKF_AD_ALU_XOR_X:
1023
+
case BPF_ALU | BPF_XOR | BPF_X:
1053
1024
/* A ^= X */
1054
-
update_on_xread(ctx);
1055
1025
ctx->flags |= SEEN_A;
1056
1026
emit_xor(r_A, r_A, r_X, ctx);
1057
1027
break;
1058
-
case BPF_S_ALU_AND_K:
1028
+
case BPF_ALU | BPF_AND | BPF_K:
1059
1029
/* A &= K */
1060
1030
ctx->flags |= SEEN_A;
1061
1031
emit_andi(r_A, r_A, k, ctx);
1062
1032
break;
1063
-
case BPF_S_ALU_AND_X:
1033
+
case BPF_ALU | BPF_AND | BPF_X:
1064
1034
/* A &= X */
1065
-
update_on_xread(ctx);
1066
1035
ctx->flags |= SEEN_A | SEEN_X;
1067
1036
emit_and(r_A, r_A, r_X, ctx);
1068
1037
break;
1069
-
case BPF_S_ALU_LSH_K:
1038
+
case BPF_ALU | BPF_LSH | BPF_K:
1070
1039
/* A <<= K */
1071
1040
ctx->flags |= SEEN_A;
1072
1041
emit_sll(r_A, r_A, k, ctx);
1073
1042
break;
1074
-
case BPF_S_ALU_LSH_X:
1043
+
case BPF_ALU | BPF_LSH | BPF_X:
1075
1044
/* A <<= X */
1076
1045
ctx->flags |= SEEN_A | SEEN_X;
1077
-
update_on_xread(ctx);
1078
1046
emit_sllv(r_A, r_A, r_X, ctx);
1079
1047
break;
1080
-
case BPF_S_ALU_RSH_K:
1048
+
case BPF_ALU | BPF_RSH | BPF_K:
1081
1049
/* A >>= K */
1082
1050
ctx->flags |= SEEN_A;
1083
1051
emit_srl(r_A, r_A, k, ctx);
1084
1052
break;
1085
-
case BPF_S_ALU_RSH_X:
1053
+
case BPF_ALU | BPF_RSH | BPF_X:
1086
1054
ctx->flags |= SEEN_A | SEEN_X;
1087
-
update_on_xread(ctx);
1088
1055
emit_srlv(r_A, r_A, r_X, ctx);
1089
1056
break;
1090
-
case BPF_S_ALU_NEG:
1057
+
case BPF_ALU | BPF_NEG:
1091
1058
/* A = -A */
1092
1059
ctx->flags |= SEEN_A;
1093
1060
emit_neg(r_A, ctx);
1094
1061
break;
1095
-
case BPF_S_JMP_JA:
1062
+
case BPF_JMP | BPF_JA:
1096
1063
/* pc += K */
1097
1064
emit_b(b_imm(i + k + 1, ctx), ctx);
1098
1065
emit_nop(ctx);
1099
1066
break;
1100
-
case BPF_S_JMP_JEQ_K:
1067
+
case BPF_JMP | BPF_JEQ | BPF_K:
1101
1068
/* pc += ( A == K ) ? pc->jt : pc->jf */
1102
1069
condt = MIPS_COND_EQ | MIPS_COND_K;
1103
1070
goto jmp_cmp;
1104
-
case BPF_S_JMP_JEQ_X:
1071
+
case BPF_JMP | BPF_JEQ | BPF_X:
1105
1072
ctx->flags |= SEEN_X;
1106
1073
/* pc += ( A == X ) ? pc->jt : pc->jf */
1107
1074
condt = MIPS_COND_EQ | MIPS_COND_X;
1108
1075
goto jmp_cmp;
1109
-
case BPF_S_JMP_JGE_K:
1076
+
case BPF_JMP | BPF_JGE | BPF_K:
1110
1077
/* pc += ( A >= K ) ? pc->jt : pc->jf */
1111
1078
condt = MIPS_COND_GE | MIPS_COND_K;
1112
1079
goto jmp_cmp;
1113
-
case BPF_S_JMP_JGE_X:
1080
+
case BPF_JMP | BPF_JGE | BPF_X:
1114
1081
ctx->flags |= SEEN_X;
1115
1082
/* pc += ( A >= X ) ? pc->jt : pc->jf */
1116
1083
condt = MIPS_COND_GE | MIPS_COND_X;
1117
1084
goto jmp_cmp;
1118
-
case BPF_S_JMP_JGT_K:
1085
+
case BPF_JMP | BPF_JGT | BPF_K:
1119
1086
/* pc += ( A > K ) ? pc->jt : pc->jf */
1120
1087
condt = MIPS_COND_GT | MIPS_COND_K;
1121
1088
goto jmp_cmp;
1122
-
case BPF_S_JMP_JGT_X:
1089
+
case BPF_JMP | BPF_JGT | BPF_X:
1123
1090
ctx->flags |= SEEN_X;
1124
1091
/* pc += ( A > X ) ? pc->jt : pc->jf */
1125
1092
condt = MIPS_COND_GT | MIPS_COND_X;
···
1132
1109
}
1133
1110
/* A < (K|X) ? r_scrach = 1 */
1134
1111
b_off = b_imm(i + inst->jf + 1, ctx);
1135
-
emit_bcond(MIPS_COND_GT, r_s0, r_zero, b_off,
1112
+
emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off,
1136
1113
ctx);
1137
1114
emit_nop(ctx);
1138
1115
/* A > (K|X) ? scratch = 0 */
···
1190
1167
}
1191
1168
}
1192
1169
break;
1193
-
case BPF_S_JMP_JSET_K:
1170
+
case BPF_JMP | BPF_JSET | BPF_K:
1194
1171
ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A;
1195
1172
/* pc += (A & K) ? pc -> jt : pc -> jf */
1196
1173
emit_load_imm(r_s1, k, ctx);
···
1204
1181
emit_b(b_off, ctx);
1205
1182
emit_nop(ctx);
1206
1183
break;
1207
-
case BPF_S_JMP_JSET_X:
1184
+
case BPF_JMP | BPF_JSET | BPF_X:
1208
1185
ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A;
1209
1186
/* pc += (A & X) ? pc -> jt : pc -> jf */
1210
1187
emit_and(r_s0, r_A, r_X, ctx);
···
1217
1194
emit_b(b_off, ctx);
1218
1195
emit_nop(ctx);
1219
1196
break;
1220
-
case BPF_S_RET_A:
1197
+
case BPF_RET | BPF_A:
1221
1198
ctx->flags |= SEEN_A;
1222
1199
if (i != prog->len - 1)
1223
1200
/*
···
1227
1204
emit_b(b_imm(prog->len, ctx), ctx);
1228
1205
emit_reg_move(r_ret, r_A, ctx); /* delay slot */
1229
1206
break;
1230
-
case BPF_S_RET_K:
1207
+
case BPF_RET | BPF_K:
1231
1208
/*
1232
1209
* It can emit two instructions so it does not fit on
1233
1210
* the delay slot.
···
1242
1219
emit_nop(ctx);
1243
1220
}
1244
1221
break;
1245
-
case BPF_S_MISC_TAX:
1222
+
case BPF_MISC | BPF_TAX:
1246
1223
/* X = A */
1247
1224
ctx->flags |= SEEN_X | SEEN_A;
1248
1225
emit_jit_reg_move(r_X, r_A, ctx);
1249
1226
break;
1250
-
case BPF_S_MISC_TXA:
1227
+
case BPF_MISC | BPF_TXA:
1251
1228
/* A = X */
1252
1229
ctx->flags |= SEEN_A | SEEN_X;
1253
-
update_on_xread(ctx);
1254
1230
emit_jit_reg_move(r_A, r_X, ctx);
1255
1231
break;
1256
1232
/* AUX */
1257
-
case BPF_S_ANC_PROTOCOL:
1233
+
case BPF_ANC | SKF_AD_PROTOCOL:
1258
1234
/* A = ntohs(skb->protocol */
1259
1235
ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A;
1260
1236
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
···
1278
1256
}
1279
1257
#endif
1280
1258
break;
1281
-
case BPF_S_ANC_CPU:
1259
+
case BPF_ANC | SKF_AD_CPU:
1282
1260
ctx->flags |= SEEN_A | SEEN_OFF;
1283
1261
/* A = current_thread_info()->cpu */
1284
1262
BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info,
···
1287
1265
/* $28/gp points to the thread_info struct */
1288
1266
emit_load(r_A, 28, off, ctx);
1289
1267
break;
1290
-
case BPF_S_ANC_IFINDEX:
1268
+
case BPF_ANC | SKF_AD_IFINDEX:
1291
1269
/* A = skb->dev->ifindex */
1292
1270
ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0;
1293
1271
off = offsetof(struct sk_buff, dev);
1294
-
emit_load(r_s0, r_skb, off, ctx);
1272
+
/* Load *dev pointer */
1273
+
emit_load_ptr(r_s0, r_skb, off, ctx);
1295
1274
/* error (0) in the delay slot */
1296
1275
emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
1297
1276
b_imm(prog->len, ctx), ctx);
···
1302
1279
off = offsetof(struct net_device, ifindex);
1303
1280
emit_load(r_A, r_s0, off, ctx);
1304
1281
break;
1305
-
case BPF_S_ANC_MARK:
1282
+
case BPF_ANC | SKF_AD_MARK:
1306
1283
ctx->flags |= SEEN_SKB | SEEN_A;
1307
1284
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
1308
1285
off = offsetof(struct sk_buff, mark);
1309
1286
emit_load(r_A, r_skb, off, ctx);
1310
1287
break;
1311
-
case BPF_S_ANC_RXHASH:
1288
+
case BPF_ANC | SKF_AD_RXHASH:
1312
1289
ctx->flags |= SEEN_SKB | SEEN_A;
1313
1290
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
1314
1291
off = offsetof(struct sk_buff, hash);
1315
1292
emit_load(r_A, r_skb, off, ctx);
1316
1293
break;
1317
-
case BPF_S_ANC_VLAN_TAG:
1318
-
case BPF_S_ANC_VLAN_TAG_PRESENT:
1294
+
case BPF_ANC | SKF_AD_VLAN_TAG:
1295
+
case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
1319
1296
ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A;
1320
1297
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1321
1298
vlan_tci) != 2);
1322
1299
off = offsetof(struct sk_buff, vlan_tci);
1323
1300
emit_half_load(r_s0, r_skb, off, ctx);
1324
-
if (inst->code == BPF_S_ANC_VLAN_TAG)
1325
-
emit_and(r_A, r_s0, VLAN_VID_MASK, ctx);
1326
-
else
1327
-
emit_and(r_A, r_s0, VLAN_TAG_PRESENT, ctx);
1301
+
if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
1302
+
emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx);
1303
+
} else {
1304
+
emit_andi(r_A, r_s0, VLAN_TAG_PRESENT, ctx);
1305
+
/* return 1 if present */
1306
+
emit_sltu(r_A, r_zero, r_A, ctx);
1307
+
}
1328
1308
break;
1329
-
case BPF_S_ANC_PKTTYPE:
1309
+
case BPF_ANC | SKF_AD_PKTTYPE:
1310
+
ctx->flags |= SEEN_SKB;
1311
+
1330
1312
off = pkt_type_offset();
1331
1313
1332
1314
if (off < 0)
···
1339
1311
emit_load_byte(r_tmp, r_skb, off, ctx);
1340
1312
/* Keep only the last 3 bits */
1341
1313
emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx);
1314
+
#ifdef __BIG_ENDIAN_BITFIELD
1315
+
/* Get the actual packet type to the lower 3 bits */
1316
+
emit_srl(r_A, r_A, 5, ctx);
1317
+
#endif
1342
1318
break;
1343
-
case BPF_S_ANC_QUEUE:
1319
+
case BPF_ANC | SKF_AD_QUEUE:
1344
1320
ctx->flags |= SEEN_SKB | SEEN_A;
1345
1321
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1346
1322
queue_mapping) != 2);
···
1354
1322
emit_half_load(r_A, r_skb, off, ctx);
1355
1323
break;
1356
1324
default:
1357
-
pr_warn("%s: Unhandled opcode: 0x%02x\n", __FILE__,
1358
-
inst->code);
1325
+
pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__,
1326
+
inst->code);
1359
1327
return -1;
1360
1328
}
1361
1329
}
+8
-2
drivers/tc/tc.c
+8
-2
drivers/tc/tc.c
···
129
129
130
130
tc_device_get_irq(tdev);
131
131
132
-
device_register(&tdev->dev);
132
+
if (device_register(&tdev->dev)) {
133
+
put_device(&tdev->dev);
134
+
goto out_err;
135
+
}
133
136
list_add_tail(&tdev->node, &tbus->devices);
134
137
135
138
out_err:
···
151
148
152
149
INIT_LIST_HEAD(&tc_bus.devices);
153
150
dev_set_name(&tc_bus.dev, "tc");
154
-
device_register(&tc_bus.dev);
151
+
if (device_register(&tc_bus.dev)) {
152
+
put_device(&tc_bus.dev);
153
+
return 0;
154
+
}
155
155
156
156
if (tc_bus.info.slot_size) {
157
157
unsigned int tc_clock = tc_get_speed(&tc_bus) / 100000;
+2
-2
scripts/recordmcount.h
+2
-2
scripts/recordmcount.h
···
163
163
164
164
static int MIPS_is_fake_mcount(Elf_Rel const *rp)
165
165
{
166
-
static Elf_Addr old_r_offset;
166
+
static Elf_Addr old_r_offset = ~(Elf_Addr)0;
167
167
Elf_Addr current_r_offset = _w(rp->r_offset);
168
168
int is_fake;
169
169
170
-
is_fake = old_r_offset &&
170
+
is_fake = (old_r_offset != ~(Elf_Addr)0) &&
171
171
(current_r_offset - old_r_offset == MIPS_FAKEMCOUNT_OFFSET);
172
172
old_r_offset = current_r_offset;
173
173