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phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct

As done for Qcom PCIe PHY driver, let's move the register settings to the
common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY
settings needed for functionalities like HS-G4 in the future by adding one
more instance of the qmp_phy_cfg_tbls.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul c9a7b0dd fcfcae3b

+113 -83
+113 -83
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 532 532 u16 rx2; 533 533 }; 534 534 535 + struct qmp_phy_cfg_tbls { 536 + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 537 + const struct qmp_phy_init_tbl *serdes; 538 + int serdes_num; 539 + const struct qmp_phy_init_tbl *tx; 540 + int tx_num; 541 + const struct qmp_phy_init_tbl *rx; 542 + int rx_num; 543 + const struct qmp_phy_init_tbl *pcs; 544 + int pcs_num; 545 + }; 546 + 535 547 /* struct qmp_phy_cfg - per-PHY initialization config */ 536 548 struct qmp_phy_cfg { 537 549 int lanes; 538 550 539 551 const struct qmp_ufs_offsets *offsets; 540 552 541 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 542 - const struct qmp_phy_init_tbl *serdes_tbl; 543 - int serdes_tbl_num; 544 - const struct qmp_phy_init_tbl *tx_tbl; 545 - int tx_tbl_num; 546 - const struct qmp_phy_init_tbl *rx_tbl; 547 - int rx_tbl_num; 548 - const struct qmp_phy_init_tbl *pcs_tbl; 549 - int pcs_tbl_num; 553 + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 554 + const struct qmp_phy_cfg_tbls tbls; 550 555 551 556 /* clock ids to be requested */ 552 557 const char * const *clk_list; ··· 642 637 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { 643 638 .lanes = 1, 644 639 645 - .serdes_tbl = msm8996_ufsphy_serdes, 646 - .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 647 - .tx_tbl = msm8996_ufsphy_tx, 648 - .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx), 649 - .rx_tbl = msm8996_ufsphy_rx, 650 - .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx), 640 + .tbls = { 641 + .serdes = msm8996_ufsphy_serdes, 642 + .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 643 + .tx = msm8996_ufsphy_tx, 644 + .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), 645 + .rx = msm8996_ufsphy_rx, 646 + .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 647 + }, 651 648 652 649 .clk_list = msm8996_ufs_phy_clk_l, 653 650 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), ··· 667 660 668 661 .offsets = &qmp_ufs_offsets_v5, 669 662 670 - .serdes_tbl = sm8350_ufsphy_serdes, 671 - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 672 - .tx_tbl = sm8350_ufsphy_tx, 673 - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), 674 - .rx_tbl = sm8350_ufsphy_rx, 675 - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), 676 - .pcs_tbl = sm8350_ufsphy_pcs, 677 - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 663 + .tbls = { 664 + .serdes = sm8350_ufsphy_serdes, 665 + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 666 + .tx = sm8350_ufsphy_tx, 667 + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 668 + .rx = sm8350_ufsphy_rx, 669 + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 670 + .pcs = sm8350_ufsphy_pcs, 671 + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 672 + }, 678 673 .clk_list = sdm845_ufs_phy_clk_l, 679 674 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 680 675 .vreg_list = qmp_phy_vreg_l, ··· 687 678 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 688 679 .lanes = 2, 689 680 690 - .serdes_tbl = sdm845_ufsphy_serdes, 691 - .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 692 - .tx_tbl = sdm845_ufsphy_tx, 693 - .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx), 694 - .rx_tbl = sdm845_ufsphy_rx, 695 - .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx), 696 - .pcs_tbl = sdm845_ufsphy_pcs, 697 - .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 681 + .tbls = { 682 + .serdes = sdm845_ufsphy_serdes, 683 + .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 684 + .tx = sdm845_ufsphy_tx, 685 + .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 686 + .rx = sdm845_ufsphy_rx, 687 + .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 688 + .pcs = sdm845_ufsphy_pcs, 689 + .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 690 + }, 698 691 .clk_list = sdm845_ufs_phy_clk_l, 699 692 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 700 693 .vreg_list = qmp_phy_vreg_l, ··· 711 700 712 701 .offsets = &qmp_ufs_offsets_v5, 713 702 714 - .serdes_tbl = sm6115_ufsphy_serdes, 715 - .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 716 - .tx_tbl = sm6115_ufsphy_tx, 717 - .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx), 718 - .rx_tbl = sm6115_ufsphy_rx, 719 - .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx), 720 - .pcs_tbl = sm6115_ufsphy_pcs, 721 - .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 703 + .tbls = { 704 + .serdes = sm6115_ufsphy_serdes, 705 + .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 706 + .tx = sm6115_ufsphy_tx, 707 + .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), 708 + .rx = sm6115_ufsphy_rx, 709 + .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), 710 + .pcs = sm6115_ufsphy_pcs, 711 + .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 712 + }, 722 713 .clk_list = sdm845_ufs_phy_clk_l, 723 714 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 724 715 .vreg_list = qmp_phy_vreg_l, ··· 733 720 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 734 721 .lanes = 2, 735 722 736 - .serdes_tbl = sm8150_ufsphy_serdes, 737 - .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 738 - .tx_tbl = sm8150_ufsphy_tx, 739 - .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx), 740 - .rx_tbl = sm8150_ufsphy_rx, 741 - .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx), 742 - .pcs_tbl = sm8150_ufsphy_pcs, 743 - .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 723 + .tbls = { 724 + .serdes = sm8150_ufsphy_serdes, 725 + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 726 + .tx = sm8150_ufsphy_tx, 727 + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 728 + .rx = sm8150_ufsphy_rx, 729 + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 730 + .pcs = sm8150_ufsphy_pcs, 731 + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 732 + }, 744 733 .clk_list = sdm845_ufs_phy_clk_l, 745 734 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 746 735 .vreg_list = qmp_phy_vreg_l, ··· 753 738 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 754 739 .lanes = 2, 755 740 756 - .serdes_tbl = sm8350_ufsphy_serdes, 757 - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 758 - .tx_tbl = sm8350_ufsphy_tx, 759 - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), 760 - .rx_tbl = sm8350_ufsphy_rx, 761 - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), 762 - .pcs_tbl = sm8350_ufsphy_pcs, 763 - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 741 + .tbls = { 742 + .serdes = sm8350_ufsphy_serdes, 743 + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 744 + .tx = sm8350_ufsphy_tx, 745 + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 746 + .rx = sm8350_ufsphy_rx, 747 + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 748 + .pcs = sm8350_ufsphy_pcs, 749 + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 750 + }, 764 751 .clk_list = sdm845_ufs_phy_clk_l, 765 752 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 766 753 .vreg_list = qmp_phy_vreg_l, ··· 773 756 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 774 757 .lanes = 2, 775 758 776 - .serdes_tbl = sm8350_ufsphy_serdes, 777 - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 778 - .tx_tbl = sm8350_ufsphy_tx, 779 - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), 780 - .rx_tbl = sm8350_ufsphy_rx, 781 - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), 782 - .pcs_tbl = sm8350_ufsphy_pcs, 783 - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 759 + .tbls = { 760 + .serdes = sm8350_ufsphy_serdes, 761 + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 762 + .tx = sm8350_ufsphy_tx, 763 + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 764 + .rx = sm8350_ufsphy_rx, 765 + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 766 + .pcs = sm8350_ufsphy_pcs, 767 + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 768 + }, 784 769 .clk_list = sm8450_ufs_phy_clk_l, 785 770 .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), 786 771 .vreg_list = qmp_phy_vreg_l, ··· 816 797 qmp_ufs_configure_lane(base, tbl, num, 0xff); 817 798 } 818 799 819 - static int qmp_ufs_serdes_init(struct qmp_ufs *qmp) 800 + static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 801 + { 802 + void __iomem *serdes = qmp->serdes; 803 + 804 + qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num); 805 + } 806 + 807 + static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 820 808 { 821 809 const struct qmp_phy_cfg *cfg = qmp->cfg; 822 - void __iomem *serdes = qmp->serdes; 823 - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 824 - int serdes_tbl_num = cfg->serdes_tbl_num; 810 + void __iomem *tx = qmp->tx; 811 + void __iomem *rx = qmp->rx; 825 812 826 - qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num); 813 + qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 814 + qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 827 815 828 - return 0; 816 + if (cfg->lanes >= 2) { 817 + qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2); 818 + qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2); 819 + } 820 + } 821 + 822 + static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 823 + { 824 + void __iomem *pcs = qmp->pcs; 825 + 826 + qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num); 827 + } 828 + 829 + static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 830 + { 831 + qmp_ufs_serdes_init(qmp, &cfg->tbls); 832 + qmp_ufs_lanes_init(qmp, &cfg->tbls); 833 + qmp_ufs_pcs_init(qmp, &cfg->tbls); 829 834 } 830 835 831 836 static int qmp_ufs_com_init(struct qmp_ufs *qmp) ··· 936 893 { 937 894 struct qmp_ufs *qmp = phy_get_drvdata(phy); 938 895 const struct qmp_phy_cfg *cfg = qmp->cfg; 939 - void __iomem *tx = qmp->tx; 940 - void __iomem *rx = qmp->rx; 941 896 void __iomem *pcs = qmp->pcs; 942 897 void __iomem *status; 943 898 unsigned int val; 944 899 int ret; 945 900 946 - qmp_ufs_serdes_init(qmp); 947 - 948 - /* Tx, Rx, and PCS configurations */ 949 - qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 950 - qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 951 - 952 - if (cfg->lanes >= 2) { 953 - qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 954 - qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 955 - } 956 - 957 - qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 901 + qmp_ufs_init_registers(qmp, cfg); 958 902 959 903 ret = reset_control_deassert(qmp->ufs_reset); 960 904 if (ret)