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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
"A few clk driver fixes for some SoC clk drivers:

- Change a usleep() to udelay() to avoid scheduling while atomic in
the Amlogic PLL code

- Revert a patch to the Mediatek MT8183 driver that caused an
out-of-bounds write

- Return the right error value when devm_of_iomap() fails in
imx93_clocks_probe()

- Constrain the Kconfig for the fixed mmio clk so that it depends on
HAS_IOMEM and can't be compiled on architectures such as s390"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: fixed-mmio: make COMMON_CLK_FIXED_MMIO depend on HAS_IOMEM
clk: imx93: Propagate correct error in imx93_clocks_probe()
clk: mediatek: mt8183: Add back SSPM related clocks
clk: meson: change usleep_range() to udelay() for atomic context

+31 -3
+1
drivers/clk/Kconfig
··· 444 444 config COMMON_CLK_FIXED_MMIO 445 445 bool "Clock driver for Memory Mapped Fixed values" 446 446 depends on COMMON_CLK && OF 447 + depends on HAS_IOMEM 447 448 help 448 449 Support for Memory Mapped IO Fixed clocks 449 450
+1 -1
drivers/clk/imx/clk-imx93.c
··· 291 291 anatop_base = devm_of_iomap(dev, np, 0, NULL); 292 292 of_node_put(np); 293 293 if (WARN_ON(IS_ERR(anatop_base))) { 294 - ret = PTR_ERR(base); 294 + ret = PTR_ERR(anatop_base); 295 295 goto unregister_hws; 296 296 } 297 297
+27
drivers/clk/mediatek/clk-mt8183.c
··· 328 328 "syspll_d5" 329 329 }; 330 330 331 + static const char * const sspm_parents[] = { 332 + "clk26m", 333 + "univpll_d2_d4", 334 + "syspll_d2_d2", 335 + "univpll_d2_d2", 336 + "syspll_d3" 337 + }; 338 + 331 339 static const char * const dpi0_parents[] = { 332 340 "clk26m", 333 341 "tvdpll_d2", ··· 515 507 /* CLK_CFG_6 */ 516 508 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 517 509 atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 510 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SSPM, "sspm_sel", 511 + sspm_parents, 0xa0, 0xa4, 0xa8, 8, 3, 15, 0x004, 25, 512 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 518 513 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 519 514 dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 520 515 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", ··· 684 673 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 685 674 &mtk_clk_gate_ops_setclr) 686 675 676 + #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flag) \ 677 + GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, \ 678 + _shift, &mtk_clk_gate_ops_setclr, _flag) 679 + 687 680 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 688 681 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 689 682 &mtk_clk_gate_ops_setclr) 683 + 684 + #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 685 + GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, \ 686 + _shift, &mtk_clk_gate_ops_setclr, _flag) 690 687 691 688 static const struct mtk_gate infra_clks[] = { 692 689 /* INFRA0 */ ··· 767 748 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12), 768 749 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13), 769 750 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), 751 + /* infra_sspm is main clock in co-processor, should not be closed in Linux. */ 752 + GATE_INFRA2_FLAGS(CLK_INFRA_SSPM, "infra_sspm", "sspm_sel", 15, CLK_IS_CRITICAL), 770 753 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 754 + /* infra_sspm_bus_hclk is main clock in co-processor, should not be closed in Linux. */ 755 + GATE_INFRA2_FLAGS(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", "axi_sel", 17, CLK_IS_CRITICAL), 771 756 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 772 757 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 773 758 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), ··· 789 766 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 790 767 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 791 768 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 769 + /* infra_sspm_26m_self is main clock in co-processor, should not be closed in Linux. */ 770 + GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", "f_f26m_ck", 3, CLK_IS_CRITICAL), 771 + /* infra_sspm_32k_self is main clock in co-processor, should not be closed in Linux. */ 772 + GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", "f_f26m_ck", 4, CLK_IS_CRITICAL), 792 773 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 793 774 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 794 775 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7),
+2 -2
drivers/clk/meson/clk-pll.c
··· 367 367 * 3. enable the lock detect module 368 368 */ 369 369 if (MESON_PARM_APPLICABLE(&pll->current_en)) { 370 - usleep_range(10, 20); 370 + udelay(10); 371 371 meson_parm_write(clk->map, &pll->current_en, 1); 372 - usleep_range(40, 50); 372 + udelay(40); 373 373 } 374 374 375 375 if (MESON_PARM_APPLICABLE(&pll->l_detect)) {