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Revert "drm/nouveau/gsp: add support for GA100"

This reverts commit 20e0c197802c545db220157fafd567a10f2b7672.

Despite claiming to add GA100 support, that commit actually has quite
a few problems. It falsely claims that there is no VBIOS. GA100 does
have a VBIOS, but it has no display engine, so it cannot use the
PRAMIN method the read VBIOS and must fall back to using PROM.

For whatever reason, the VBIOS on GA100 has an "Init-from-ROM"
(IFR) header where the PCI Expansion ROM would normally be found.
So to find that ROM, Nouveau needs to parse the IFR header.

The commit also falsely claimed that there is no graphics (GR) engine.

So rather than try to fix that commit, just revert it and start over
from scratch.

Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Link: https://patch.msgid.link/20260430223838.2530778-2-ttabi@nvidia.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>

authored by

Timur Tabi and committed by
Danilo Krummrich c9e3878a 7dd57d7a

+18 -15
+9 -2
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
··· 2513 2513 nv170_chipset = { 2514 2514 .name = "GA100", 2515 2515 .bar = { 0x00000001, tu102_bar_new }, 2516 + .bios = { 0x00000001, nvkm_bios_new }, 2516 2517 .devinit = { 0x00000001, ga100_devinit_new }, 2517 2518 .fault = { 0x00000001, tu102_fault_new }, 2518 2519 .fb = { 0x00000001, ga100_fb_new }, ··· 2530 2529 .vfn = { 0x00000001, ga100_vfn_new }, 2531 2530 .ce = { 0x000003ff, ga100_ce_new }, 2532 2531 .fifo = { 0x00000001, ga100_fifo_new }, 2533 - .sec2 = { 0x00000001, tu102_sec2_new }, 2534 2532 }; 2535 2533 2536 2534 static const struct nvkm_device_chip ··· 3341 3341 case 0x166: device->chip = &nv166_chipset; break; 3342 3342 case 0x167: device->chip = &nv167_chipset; break; 3343 3343 case 0x168: device->chip = &nv168_chipset; break; 3344 - case 0x170: device->chip = &nv170_chipset; break; 3345 3344 case 0x172: device->chip = &nv172_chipset; break; 3346 3345 case 0x173: device->chip = &nv173_chipset; break; 3347 3346 case 0x174: device->chip = &nv174_chipset; break; ··· 3360 3361 case 0x1b6: device->chip = &nv1b6_chipset; break; 3361 3362 case 0x1b7: device->chip = &nv1b7_chipset; break; 3362 3363 default: 3364 + if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) { 3365 + switch (device->chipset) { 3366 + case 0x170: device->chip = &nv170_chipset; break; 3367 + default: 3368 + break; 3369 + } 3370 + } 3371 + 3363 3372 if (!device->chip) { 3364 3373 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 3365 3374 ret = -ENODEV;
+4
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
··· 41 41 static const struct nvkm_gsp_func 42 42 ga100_gsp = { 43 43 .flcn = &ga100_gsp_flcn, 44 + .fwsec = &tu102_gsp_fwsec, 44 45 45 46 .sig_section = ".fwsignature_ga100", 46 47 47 48 .booter.ctor = tu102_gsp_booter_ctor, 49 + 50 + .fwsec_sb.ctor = tu102_gsp_fwsec_sb_ctor, 51 + .fwsec_sb.dtor = tu102_gsp_fwsec_sb_dtor, 48 52 49 53 .dtor = r535_gsp_dtor, 50 54 .oneinit = tu102_gsp_oneinit,
+5 -13
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
··· 318 318 if (ret) 319 319 return ret; 320 320 321 - /* 322 - * Calculate FB layout. FRTS is a memory region created by the FWSEC-FRTS firmware. 323 - * FWSEC comes from VBIOS. So on systems with no VBIOS (e.g. GA100), the FRTS does 324 - * not exist. Therefore, use the existence of VBIOS to determine whether to reserve 325 - * an FRTS region. 326 - */ 327 - gsp->fb.wpr2.frts.size = device->bios ? 0x100000 : 0; 321 + /* Calculate FB layout. */ 322 + gsp->fb.wpr2.frts.size = 0x100000; 328 323 gsp->fb.wpr2.frts.addr = ALIGN_DOWN(gsp->fb.bios.addr, 0x20000) - gsp->fb.wpr2.frts.size; 329 324 330 325 gsp->fb.wpr2.boot.size = gsp->boot.fw.size; ··· 343 348 if (ret) 344 349 return ret; 345 350 346 - /* Only boot FWSEC-FRTS if it actually exists */ 347 - if (gsp->fb.wpr2.frts.size) { 348 - ret = nvkm_gsp_fwsec_frts(gsp); 349 - if (WARN_ON(ret)) 350 - return ret; 351 - } 351 + ret = nvkm_gsp_fwsec_frts(gsp); 352 + if (WARN_ON(ret)) 353 + return ret; 352 354 353 355 /* Reset GSP into RISC-V mode. */ 354 356 ret = gsp->func->reset(gsp);