Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.17-rc5' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"nouveau, amdgpu, i915, vc4, omap, exynos and atomic fixes.
As last week seemed a bit slow, we got a few more fixes this week.
The main stuff is two weeks of fixes for amdgpu, some missing bits of
vega12 atom firmware support were added, and some power management
fixes.
Nouveau got two regression fixes for an DP MST deadlock and a random
oops fix.
i915 got an LVDS panel timeout fix 2 WARN fixes.
exynos fixed a pagefault issue in the mixer driver.
vc4 has an oops fix.
omap had a bunch of uninit var and error-checking fixes. Two atomic
modesetting state fixes.
One minor agp cleanup patch"
* tag 'drm-fixes-for-v4.17-rc5' of git://people.freedesktop.org/~airlied/linux: (30 commits)
drm/amd/pp: Fix performance drop on Fiji
drm/nouveau: Fix deadlock in nv50_mstm_register_connector()
drm/nouveau/ttm: don't dereference nvbo::cli, it can outlive client
agp: uninorth: make two functions static
drm/amd/pp: Refine the output of pp_power_profile_mode on VI
drm/amdgpu: Switch to interruptable wait to recover from ring hang.
drm/ttm: Use GFP_TRANSHUGE_LIGHT for allocating huge pages
drm/amd/display: Use kvzalloc for potentially large allocations
drm/amd/display: Don't return ddc result and read_bytes in same return value
drm/amd/display: Add get_firmware_info_v3_2 for VG12
drm/amd: Add BIOS smu_info v3_3 required struct def.
drm/amd/display: Add VG12 ASIC IDs
drm/vc4: Fix scaling of uni-planar formats
drm/exynos: hdmi: avoid duplicating drm_bridge_attach
drm/i915: Fix drm:intel_enable_lvds ERROR message in kernel log
drm/i915: Correctly populate user mode h/vdisplay with pipe src size during readout
drm/i915: Adjust eDP's logical vco in a reliable place.
drm/bridge/sii8620: add Kconfig dependency on extcon
drm/omap: handle alloc failures in omap_connector
drm/omap: add missing linefeeds to prints
...
+501
-158
+2
-2
drivers/char/agp/uninorth-agp.c
+2
-2
drivers/char/agp/uninorth-agp.c
···
195
195
return 0;
196
196
}
197
197
198
-
int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
198
+
static int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
199
199
{
200
200
size_t i;
201
201
u32 *gp;
···
470
470
return 0;
471
471
}
472
472
473
-
void null_cache_flush(void)
473
+
static void null_cache_flush(void)
474
474
{
475
475
mb();
476
476
}
+4
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+4
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
···
419
419
420
420
if (other) {
421
421
signed long r;
422
-
r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
422
+
r = dma_fence_wait(other, true);
423
423
if (r < 0) {
424
-
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
424
+
if (r != -ERESTARTSYS)
425
+
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
426
+
425
427
return r;
426
428
}
427
429
}
+12
-8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+12
-8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
···
83
83
enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
84
84
I2C_MOT_TRUE : I2C_MOT_FALSE;
85
85
enum ddc_result res;
86
-
ssize_t read_bytes;
86
+
uint32_t read_bytes = msg->size;
87
87
88
88
if (WARN_ON(msg->size > 16))
89
89
return -E2BIG;
90
90
91
91
switch (msg->request & ~DP_AUX_I2C_MOT) {
92
92
case DP_AUX_NATIVE_READ:
93
-
read_bytes = dal_ddc_service_read_dpcd_data(
93
+
res = dal_ddc_service_read_dpcd_data(
94
94
TO_DM_AUX(aux)->ddc_service,
95
95
false,
96
96
I2C_MOT_UNDEF,
97
97
msg->address,
98
98
msg->buffer,
99
-
msg->size);
100
-
return read_bytes;
99
+
msg->size,
100
+
&read_bytes);
101
+
break;
101
102
case DP_AUX_NATIVE_WRITE:
102
103
res = dal_ddc_service_write_dpcd_data(
103
104
TO_DM_AUX(aux)->ddc_service,
···
109
108
msg->size);
110
109
break;
111
110
case DP_AUX_I2C_READ:
112
-
read_bytes = dal_ddc_service_read_dpcd_data(
111
+
res = dal_ddc_service_read_dpcd_data(
113
112
TO_DM_AUX(aux)->ddc_service,
114
113
true,
115
114
mot,
116
115
msg->address,
117
116
msg->buffer,
118
-
msg->size);
119
-
return read_bytes;
117
+
msg->size,
118
+
&read_bytes);
119
+
break;
120
120
case DP_AUX_I2C_WRITE:
121
121
res = dal_ddc_service_write_dpcd_data(
122
122
TO_DM_AUX(aux)->ddc_service,
···
139
137
r == DDC_RESULT_SUCESSFULL);
140
138
#endif
141
139
142
-
return msg->size;
140
+
if (res != DDC_RESULT_SUCESSFULL)
141
+
return -EIO;
142
+
return read_bytes;
143
143
}
144
144
145
145
static enum drm_connector_status
+85
-1
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+85
-1
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
···
70
70
struct bios_parser *bp,
71
71
struct dc_firmware_info *info);
72
72
73
+
static enum bp_result get_firmware_info_v3_2(
74
+
struct bios_parser *bp,
75
+
struct dc_firmware_info *info);
76
+
73
77
static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
74
78
struct atom_display_object_path_v2 *object);
75
79
···
1325
1321
case 3:
1326
1322
switch (revision.minor) {
1327
1323
case 1:
1328
-
case 2:
1329
1324
result = get_firmware_info_v3_1(bp, info);
1325
+
break;
1326
+
case 2:
1327
+
result = get_firmware_info_v3_2(bp, info);
1330
1328
break;
1331
1329
default:
1332
1330
break;
···
1384
1378
/* VBIOS gives in 10KHz */
1385
1379
info->smu_gpu_pll_output_freq =
1386
1380
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1381
+
}
1382
+
1383
+
return BP_RESULT_OK;
1384
+
}
1385
+
1386
+
static enum bp_result get_firmware_info_v3_2(
1387
+
struct bios_parser *bp,
1388
+
struct dc_firmware_info *info)
1389
+
{
1390
+
struct atom_firmware_info_v3_2 *firmware_info;
1391
+
struct atom_display_controller_info_v4_1 *dce_info = NULL;
1392
+
struct atom_common_table_header *header;
1393
+
struct atom_data_revision revision;
1394
+
struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1395
+
struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1396
+
1397
+
if (!info)
1398
+
return BP_RESULT_BADINPUT;
1399
+
1400
+
firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1401
+
DATA_TABLES(firmwareinfo));
1402
+
1403
+
dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1404
+
DATA_TABLES(dce_info));
1405
+
1406
+
if (!firmware_info || !dce_info)
1407
+
return BP_RESULT_BADBIOSTABLE;
1408
+
1409
+
memset(info, 0, sizeof(*info));
1410
+
1411
+
header = GET_IMAGE(struct atom_common_table_header,
1412
+
DATA_TABLES(smu_info));
1413
+
get_atom_data_table_revision(header, &revision);
1414
+
1415
+
if (revision.minor == 2) {
1416
+
/* Vega12 */
1417
+
smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1418
+
DATA_TABLES(smu_info));
1419
+
1420
+
if (!smu_info_v3_2)
1421
+
return BP_RESULT_BADBIOSTABLE;
1422
+
1423
+
info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1424
+
} else if (revision.minor == 3) {
1425
+
/* Vega20 */
1426
+
smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1427
+
DATA_TABLES(smu_info));
1428
+
1429
+
if (!smu_info_v3_3)
1430
+
return BP_RESULT_BADBIOSTABLE;
1431
+
1432
+
info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1433
+
}
1434
+
1435
+
// We need to convert from 10KHz units into KHz units.
1436
+
info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1437
+
1438
+
/* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1439
+
info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1440
+
/* Hardcode frequency if BIOS gives no DCE Ref Clk */
1441
+
if (info->pll_info.crystal_frequency == 0) {
1442
+
if (revision.minor == 2)
1443
+
info->pll_info.crystal_frequency = 27000;
1444
+
else if (revision.minor == 3)
1445
+
info->pll_info.crystal_frequency = 100000;
1446
+
}
1447
+
/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1448
+
info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1449
+
info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1450
+
1451
+
/* Get GPU PLL VCO Clock */
1452
+
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1453
+
if (revision.minor == 2)
1454
+
info->smu_gpu_pll_output_freq =
1455
+
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1456
+
else if (revision.minor == 3)
1457
+
info->smu_gpu_pll_output_freq =
1458
+
bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1387
1459
}
1388
1460
1389
1461
return BP_RESULT_OK;
+7
-3
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+7
-3
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
···
629
629
return ret;
630
630
}
631
631
632
-
ssize_t dal_ddc_service_read_dpcd_data(
632
+
enum ddc_result dal_ddc_service_read_dpcd_data(
633
633
struct ddc_service *ddc,
634
634
bool i2c,
635
635
enum i2c_mot_mode mot,
636
636
uint32_t address,
637
637
uint8_t *data,
638
-
uint32_t len)
638
+
uint32_t len,
639
+
uint32_t *read)
639
640
{
640
641
struct aux_payload read_payload = {
641
642
.i2c_over_aux = i2c,
···
653
652
.mot = mot
654
653
};
655
654
655
+
*read = 0;
656
+
656
657
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
657
658
BREAK_TO_DEBUGGER();
658
659
return DDC_RESULT_FAILED_INVALID_OPERATION;
···
664
661
ddc->ctx->i2caux,
665
662
ddc->ddc_pin,
666
663
&command)) {
667
-
return (ssize_t)command.payloads->length;
664
+
*read = command.payloads->length;
665
+
return DDC_RESULT_SUCESSFULL;
668
666
}
669
667
670
668
return DDC_RESULT_FAILED_OPERATION;
+7
-7
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+7
-7
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
···
66
66
{
67
67
struct dc *core_dc = dc;
68
68
69
-
struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
70
-
GFP_KERNEL);
69
+
struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
70
+
GFP_KERNEL);
71
71
72
72
if (NULL == plane_state)
73
73
return NULL;
···
120
120
{
121
121
struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
122
122
destruct(plane_state);
123
-
kfree(plane_state);
123
+
kvfree(plane_state);
124
124
}
125
125
126
126
void dc_plane_state_release(struct dc_plane_state *plane_state)
···
136
136
static void dc_gamma_free(struct kref *kref)
137
137
{
138
138
struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
139
-
kfree(gamma);
139
+
kvfree(gamma);
140
140
}
141
141
142
142
void dc_gamma_release(struct dc_gamma **gamma)
···
147
147
148
148
struct dc_gamma *dc_create_gamma(void)
149
149
{
150
-
struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
150
+
struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
151
151
152
152
if (gamma == NULL)
153
153
goto alloc_fail;
···
167
167
static void dc_transfer_func_free(struct kref *kref)
168
168
{
169
169
struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
170
-
kfree(tf);
170
+
kvfree(tf);
171
171
}
172
172
173
173
void dc_transfer_func_release(struct dc_transfer_func *tf)
···
177
177
178
178
struct dc_transfer_func *dc_create_transfer_func(void)
179
179
{
180
-
struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
180
+
struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
181
181
182
182
if (tf == NULL)
183
183
goto alloc_fail;
+3
-2
drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+3
-2
drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
···
102
102
uint8_t *read_buf,
103
103
uint32_t read_size);
104
104
105
-
ssize_t dal_ddc_service_read_dpcd_data(
105
+
enum ddc_result dal_ddc_service_read_dpcd_data(
106
106
struct ddc_service *ddc,
107
107
bool i2c,
108
108
enum i2c_mot_mode mot,
109
109
uint32_t address,
110
110
uint8_t *data,
111
-
uint32_t len);
111
+
uint32_t len,
112
+
uint32_t *read);
112
113
113
114
enum ddc_result dal_ddc_service_write_dpcd_data(
114
115
struct ddc_service *ddc,
+7
-2
drivers/gpu/drm/amd/display/include/dal_asic_id.h
+7
-2
drivers/gpu/drm/amd/display/include/dal_asic_id.h
···
113
113
114
114
#define AI_GREENLAND_P_A0 1
115
115
#define AI_GREENLAND_P_A1 2
116
+
#define AI_UNKNOWN 0xFF
116
117
117
-
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_UNKNOWN)
118
-
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_UNKNOWN)
118
+
#define AI_VEGA12_P_A0 20
119
+
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
120
+
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
121
+
122
+
#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
123
+
#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
119
124
120
125
/* DCN1_0 */
121
126
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
+38
-34
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+38
-34
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
···
1093
1093
1094
1094
output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1095
1095
1096
-
rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1097
-
GFP_KERNEL);
1096
+
rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1097
+
GFP_KERNEL);
1098
1098
if (!rgb_user)
1099
1099
goto rgb_user_alloc_fail;
1100
-
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1101
-
GFP_KERNEL);
1100
+
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1101
+
GFP_KERNEL);
1102
1102
if (!rgb_regamma)
1103
1103
goto rgb_regamma_alloc_fail;
1104
-
axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
1105
-
GFP_KERNEL);
1104
+
axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
1105
+
GFP_KERNEL);
1106
1106
if (!axix_x)
1107
1107
goto axix_x_alloc_fail;
1108
-
coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1108
+
coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1109
1109
if (!coeff)
1110
1110
goto coeff_alloc_fail;
1111
1111
···
1157
1157
1158
1158
ret = true;
1159
1159
1160
-
kfree(coeff);
1160
+
kvfree(coeff);
1161
1161
coeff_alloc_fail:
1162
-
kfree(axix_x);
1162
+
kvfree(axix_x);
1163
1163
axix_x_alloc_fail:
1164
-
kfree(rgb_regamma);
1164
+
kvfree(rgb_regamma);
1165
1165
rgb_regamma_alloc_fail:
1166
-
kfree(rgb_user);
1166
+
kvfree(rgb_user);
1167
1167
rgb_user_alloc_fail:
1168
1168
return ret;
1169
1169
}
···
1192
1192
1193
1193
input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1194
1194
1195
-
rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1196
-
GFP_KERNEL);
1195
+
rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1196
+
GFP_KERNEL);
1197
1197
if (!rgb_user)
1198
1198
goto rgb_user_alloc_fail;
1199
-
curve = kzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
1200
-
GFP_KERNEL);
1199
+
curve = kvzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
1200
+
GFP_KERNEL);
1201
1201
if (!curve)
1202
1202
goto curve_alloc_fail;
1203
-
axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
1204
-
GFP_KERNEL);
1203
+
axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
1204
+
GFP_KERNEL);
1205
1205
if (!axix_x)
1206
1206
goto axix_x_alloc_fail;
1207
-
coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1207
+
coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1208
1208
if (!coeff)
1209
1209
goto coeff_alloc_fail;
1210
1210
···
1246
1246
1247
1247
ret = true;
1248
1248
1249
-
kfree(coeff);
1249
+
kvfree(coeff);
1250
1250
coeff_alloc_fail:
1251
-
kfree(axix_x);
1251
+
kvfree(axix_x);
1252
1252
axix_x_alloc_fail:
1253
-
kfree(curve);
1253
+
kvfree(curve);
1254
1254
curve_alloc_fail:
1255
-
kfree(rgb_user);
1255
+
kvfree(rgb_user);
1256
1256
rgb_user_alloc_fail:
1257
1257
1258
1258
return ret;
···
1281
1281
}
1282
1282
ret = true;
1283
1283
} else if (trans == TRANSFER_FUNCTION_PQ) {
1284
-
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
1285
-
_EXTRA_POINTS), GFP_KERNEL);
1284
+
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1285
+
(MAX_HW_POINTS + _EXTRA_POINTS),
1286
+
GFP_KERNEL);
1286
1287
if (!rgb_regamma)
1287
1288
goto rgb_regamma_alloc_fail;
1288
1289
points->end_exponent = 7;
···
1303
1302
}
1304
1303
ret = true;
1305
1304
1306
-
kfree(rgb_regamma);
1305
+
kvfree(rgb_regamma);
1307
1306
} else if (trans == TRANSFER_FUNCTION_SRGB ||
1308
1307
trans == TRANSFER_FUNCTION_BT709) {
1309
-
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
1310
-
_EXTRA_POINTS), GFP_KERNEL);
1308
+
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1309
+
(MAX_HW_POINTS + _EXTRA_POINTS),
1310
+
GFP_KERNEL);
1311
1311
if (!rgb_regamma)
1312
1312
goto rgb_regamma_alloc_fail;
1313
1313
points->end_exponent = 0;
···
1326
1324
}
1327
1325
ret = true;
1328
1326
1329
-
kfree(rgb_regamma);
1327
+
kvfree(rgb_regamma);
1330
1328
}
1331
1329
rgb_regamma_alloc_fail:
1332
1330
return ret;
···
1350
1348
}
1351
1349
ret = true;
1352
1350
} else if (trans == TRANSFER_FUNCTION_PQ) {
1353
-
rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
1354
-
_EXTRA_POINTS), GFP_KERNEL);
1351
+
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1352
+
(MAX_HW_POINTS + _EXTRA_POINTS),
1353
+
GFP_KERNEL);
1355
1354
if (!rgb_degamma)
1356
1355
goto rgb_degamma_alloc_fail;
1357
1356
···
1367
1364
}
1368
1365
ret = true;
1369
1366
1370
-
kfree(rgb_degamma);
1367
+
kvfree(rgb_degamma);
1371
1368
} else if (trans == TRANSFER_FUNCTION_SRGB ||
1372
1369
trans == TRANSFER_FUNCTION_BT709) {
1373
-
rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
1374
-
_EXTRA_POINTS), GFP_KERNEL);
1370
+
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1371
+
(MAX_HW_POINTS + _EXTRA_POINTS),
1372
+
GFP_KERNEL);
1375
1373
if (!rgb_degamma)
1376
1374
goto rgb_degamma_alloc_fail;
1377
1375
···
1386
1382
}
1387
1383
ret = true;
1388
1384
1389
-
kfree(rgb_degamma);
1385
+
kvfree(rgb_degamma);
1390
1386
}
1391
1387
points->end_exponent = 0;
1392
1388
points->x_point_at_y1_red = 1;
+168
-2
drivers/gpu/drm/amd/include/atomfirmware.h
+168
-2
drivers/gpu/drm/amd/include/atomfirmware.h
···
501
501
LIQUID_COOLING = 0x01
502
502
};
503
503
504
+
struct atom_firmware_info_v3_2 {
505
+
struct atom_common_table_header table_header;
506
+
uint32_t firmware_revision;
507
+
uint32_t bootup_sclk_in10khz;
508
+
uint32_t bootup_mclk_in10khz;
509
+
uint32_t firmware_capability; // enum atombios_firmware_capability
510
+
uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511
+
uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512
+
uint16_t bootup_vddc_mv;
513
+
uint16_t bootup_vddci_mv;
514
+
uint16_t bootup_mvddc_mv;
515
+
uint16_t bootup_vddgfx_mv;
516
+
uint8_t mem_module_id;
517
+
uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518
+
uint8_t reserved1[2];
519
+
uint32_t mc_baseaddr_high;
520
+
uint32_t mc_baseaddr_low;
521
+
uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522
+
uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523
+
uint8_t board_i2c_feature_slave_addr;
524
+
uint8_t reserved3;
525
+
uint16_t bootup_mvddq_mv;
526
+
uint16_t bootup_mvpp_mv;
527
+
uint32_t zfbstartaddrin16mb;
528
+
uint32_t reserved2[3];
529
+
};
504
530
505
531
/*
506
532
***************************************************************************
···
1195
1169
uint32_t rlc_gpu_timer_refclk;
1196
1170
};
1197
1171
1198
-
1172
+
struct atom_gfx_info_v2_3 {
1173
+
struct atom_common_table_header table_header;
1174
+
uint8_t gfxip_min_ver;
1175
+
uint8_t gfxip_max_ver;
1176
+
uint8_t max_shader_engines;
1177
+
uint8_t max_tile_pipes;
1178
+
uint8_t max_cu_per_sh;
1179
+
uint8_t max_sh_per_se;
1180
+
uint8_t max_backends_per_se;
1181
+
uint8_t max_texture_channel_caches;
1182
+
uint32_t regaddr_cp_dma_src_addr;
1183
+
uint32_t regaddr_cp_dma_src_addr_hi;
1184
+
uint32_t regaddr_cp_dma_dst_addr;
1185
+
uint32_t regaddr_cp_dma_dst_addr_hi;
1186
+
uint32_t regaddr_cp_dma_command;
1187
+
uint32_t regaddr_cp_status;
1188
+
uint32_t regaddr_rlc_gpu_clock_32;
1189
+
uint32_t rlc_gpu_timer_refclk;
1190
+
uint8_t active_cu_per_sh;
1191
+
uint8_t active_rb_per_se;
1192
+
uint16_t gcgoldenoffset;
1193
+
uint32_t rm21_sram_vmin_value;
1194
+
};
1199
1195
1200
1196
/*
1201
1197
***************************************************************************
···
1244
1196
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1245
1197
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1246
1198
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1199
+
};
1200
+
1201
+
struct atom_smu_info_v3_2 {
1202
+
struct atom_common_table_header table_header;
1203
+
uint8_t smuip_min_ver;
1204
+
uint8_t smuip_max_ver;
1205
+
uint8_t smu_rsd1;
1206
+
uint8_t gpuclk_ss_mode;
1207
+
uint16_t sclk_ss_percentage;
1208
+
uint16_t sclk_ss_rate_10hz;
1209
+
uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1210
+
uint16_t gpuclk_ss_rate_10hz;
1211
+
uint32_t core_refclk_10khz;
1212
+
uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1213
+
uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1214
+
uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1215
+
uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1216
+
uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1217
+
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1218
+
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1219
+
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1220
+
uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1221
+
uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1222
+
uint16_t smugoldenoffset;
1223
+
uint32_t gpupll_vco_freq_10khz;
1224
+
uint32_t bootup_smnclk_10khz;
1225
+
uint32_t bootup_socclk_10khz;
1226
+
uint32_t bootup_mp0clk_10khz;
1227
+
uint32_t bootup_mp1clk_10khz;
1228
+
uint32_t bootup_lclk_10khz;
1229
+
uint32_t bootup_dcefclk_10khz;
1230
+
uint32_t ctf_threshold_override_value;
1231
+
uint32_t reserved[5];
1232
+
};
1233
+
1234
+
struct atom_smu_info_v3_3 {
1235
+
struct atom_common_table_header table_header;
1236
+
uint8_t smuip_min_ver;
1237
+
uint8_t smuip_max_ver;
1238
+
uint8_t smu_rsd1;
1239
+
uint8_t gpuclk_ss_mode;
1240
+
uint16_t sclk_ss_percentage;
1241
+
uint16_t sclk_ss_rate_10hz;
1242
+
uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1243
+
uint16_t gpuclk_ss_rate_10hz;
1244
+
uint32_t core_refclk_10khz;
1245
+
uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1246
+
uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1247
+
uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1248
+
uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1249
+
uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1250
+
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1251
+
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1252
+
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1253
+
uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1254
+
uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1255
+
uint16_t smugoldenoffset;
1256
+
uint32_t gpupll_vco_freq_10khz;
1257
+
uint32_t bootup_smnclk_10khz;
1258
+
uint32_t bootup_socclk_10khz;
1259
+
uint32_t bootup_mp0clk_10khz;
1260
+
uint32_t bootup_mp1clk_10khz;
1261
+
uint32_t bootup_lclk_10khz;
1262
+
uint32_t bootup_dcefclk_10khz;
1263
+
uint32_t ctf_threshold_override_value;
1264
+
uint32_t syspll3_0_vco_freq_10khz;
1265
+
uint32_t syspll3_1_vco_freq_10khz;
1266
+
uint32_t bootup_fclk_10khz;
1267
+
uint32_t bootup_waflclk_10khz;
1268
+
uint32_t reserved[3];
1247
1269
};
1248
1270
1249
1271
/*
···
1400
1282
1401
1283
uint32_t boardreserved[10];
1402
1284
};
1403
-
1404
1285
1405
1286
/*
1406
1287
***************************************************************************
···
1979
1862
SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
1980
1863
SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
1981
1864
SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1865
+
};
1866
+
1867
+
enum atom_smu11_syspll_id {
1868
+
SMU11_SYSPLL0_ID = 0,
1869
+
SMU11_SYSPLL1_0_ID = 1,
1870
+
SMU11_SYSPLL1_1_ID = 2,
1871
+
SMU11_SYSPLL1_2_ID = 3,
1872
+
SMU11_SYSPLL2_ID = 4,
1873
+
SMU11_SYSPLL3_0_ID = 5,
1874
+
SMU11_SYSPLL3_1_ID = 6,
1875
+
};
1876
+
1877
+
1878
+
enum atom_smu11_syspll0_clock_id {
1879
+
SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
1880
+
SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
1881
+
SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
1882
+
SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
1883
+
SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
1884
+
SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
1885
+
};
1886
+
1887
+
1888
+
enum atom_smu11_syspll1_0_clock_id {
1889
+
SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
1890
+
};
1891
+
1892
+
enum atom_smu11_syspll1_1_clock_id {
1893
+
SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
1894
+
};
1895
+
1896
+
enum atom_smu11_syspll1_2_clock_id {
1897
+
SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
1898
+
};
1899
+
1900
+
enum atom_smu11_syspll2_clock_id {
1901
+
SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
1902
+
};
1903
+
1904
+
enum atom_smu11_syspll3_0_clock_id {
1905
+
SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
1906
+
SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
1907
+
SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
1908
+
};
1909
+
1910
+
enum atom_smu11_syspll3_1_clock_id {
1911
+
SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
1912
+
SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
1913
+
SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
1982
1914
};
1983
1915
1984
1916
struct atom_get_smu_clock_info_output_parameters_v3_1
+23
-29
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+23
-29
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
79
79
#define PCIE_BUS_CLK 10000
80
80
#define TCLK (PCIE_BUS_CLK / 10)
81
81
82
-
static const struct profile_mode_setting smu7_profiling[5] =
82
+
static const struct profile_mode_setting smu7_profiling[6] =
83
83
{{1, 0, 100, 30, 1, 0, 100, 10},
84
84
{1, 10, 0, 30, 0, 0, 0, 0},
85
85
{0, 0, 0, 0, 1, 10, 16, 31},
86
86
{1, 0, 11, 50, 1, 0, 100, 10},
87
87
{1, 0, 5, 30, 0, 0, 0, 0},
88
+
{0, 0, 0, 0, 0, 0, 0, 0},
88
89
};
89
90
90
91
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
···
4865
4864
len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
4866
4865
4867
4866
for (i = 0; i < len; i++) {
4867
+
if (i == hwmgr->power_profile_mode) {
4868
+
size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4869
+
i, profile_name[i], "*",
4870
+
data->current_profile_setting.sclk_up_hyst,
4871
+
data->current_profile_setting.sclk_down_hyst,
4872
+
data->current_profile_setting.sclk_activity,
4873
+
data->current_profile_setting.mclk_up_hyst,
4874
+
data->current_profile_setting.mclk_down_hyst,
4875
+
data->current_profile_setting.mclk_activity);
4876
+
continue;
4877
+
}
4868
4878
if (smu7_profiling[i].bupdate_sclk)
4869
4879
size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
4870
4880
i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
···
4894
4882
size += sprintf(buf + size, "%16s %16s %16s\n",
4895
4883
"-", "-", "-");
4896
4884
}
4897
-
4898
-
size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
4899
-
i, profile_name[i],
4900
-
data->custom_profile_setting.sclk_up_hyst,
4901
-
data->custom_profile_setting.sclk_down_hyst,
4902
-
data->custom_profile_setting.sclk_activity,
4903
-
data->custom_profile_setting.mclk_up_hyst,
4904
-
data->custom_profile_setting.mclk_down_hyst,
4905
-
data->custom_profile_setting.mclk_activity);
4906
-
4907
-
size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
4908
-
"*", "CURRENT",
4909
-
data->current_profile_setting.sclk_up_hyst,
4910
-
data->current_profile_setting.sclk_down_hyst,
4911
-
data->current_profile_setting.sclk_activity,
4912
-
data->current_profile_setting.mclk_up_hyst,
4913
-
data->current_profile_setting.mclk_down_hyst,
4914
-
data->current_profile_setting.mclk_activity);
4915
4885
4916
4886
return size;
4917
4887
}
···
4933
4939
if (size < 8)
4934
4940
return -EINVAL;
4935
4941
4936
-
data->custom_profile_setting.bupdate_sclk = input[0];
4937
-
data->custom_profile_setting.sclk_up_hyst = input[1];
4938
-
data->custom_profile_setting.sclk_down_hyst = input[2];
4939
-
data->custom_profile_setting.sclk_activity = input[3];
4940
-
data->custom_profile_setting.bupdate_mclk = input[4];
4941
-
data->custom_profile_setting.mclk_up_hyst = input[5];
4942
-
data->custom_profile_setting.mclk_down_hyst = input[6];
4943
-
data->custom_profile_setting.mclk_activity = input[7];
4944
-
if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting)) {
4945
-
memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
4942
+
tmp.bupdate_sclk = input[0];
4943
+
tmp.sclk_up_hyst = input[1];
4944
+
tmp.sclk_down_hyst = input[2];
4945
+
tmp.sclk_activity = input[3];
4946
+
tmp.bupdate_mclk = input[4];
4947
+
tmp.mclk_up_hyst = input[5];
4948
+
tmp.mclk_down_hyst = input[6];
4949
+
tmp.mclk_activity = input[7];
4950
+
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
4951
+
memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
4946
4952
hwmgr->power_profile_mode = mode;
4947
4953
}
4948
4954
break;
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+1
-3
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+1
-3
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
···
852
852
{
853
853
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
854
854
855
-
n = (n & 0xff) << 8;
856
-
857
855
if (data->power_containment_features &
858
856
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
859
857
return smum_send_msg_to_smc_with_parameter(hwmgr,
860
-
PPSMC_MSG_PkgPwrSetLimit, n);
858
+
PPSMC_MSG_PkgPwrSetLimit, n<<8);
861
859
return 0;
862
860
}
863
861
+1
drivers/gpu/drm/bridge/Kconfig
+1
drivers/gpu/drm/bridge/Kconfig
+8
drivers/gpu/drm/drm_atomic.c
+8
drivers/gpu/drm/drm_atomic.c
···
155
155
state->connectors[i].state);
156
156
state->connectors[i].ptr = NULL;
157
157
state->connectors[i].state = NULL;
158
+
state->connectors[i].old_state = NULL;
159
+
state->connectors[i].new_state = NULL;
158
160
drm_connector_put(connector);
159
161
}
160
162
···
171
169
172
170
state->crtcs[i].ptr = NULL;
173
171
state->crtcs[i].state = NULL;
172
+
state->crtcs[i].old_state = NULL;
173
+
state->crtcs[i].new_state = NULL;
174
174
}
175
175
176
176
for (i = 0; i < config->num_total_plane; i++) {
···
185
181
state->planes[i].state);
186
182
state->planes[i].ptr = NULL;
187
183
state->planes[i].state = NULL;
184
+
state->planes[i].old_state = NULL;
185
+
state->planes[i].new_state = NULL;
188
186
}
189
187
190
188
for (i = 0; i < state->num_private_objs; i++) {
···
196
190
state->private_objs[i].state);
197
191
state->private_objs[i].ptr = NULL;
198
192
state->private_objs[i].state = NULL;
193
+
state->private_objs[i].old_state = NULL;
194
+
state->private_objs[i].new_state = NULL;
199
195
}
200
196
state->num_private_objs = 0;
201
197
-2
drivers/gpu/drm/exynos/exynos_hdmi.c
-2
drivers/gpu/drm/exynos/exynos_hdmi.c
···
954
954
drm_mode_connector_attach_encoder(connector, encoder);
955
955
956
956
if (hdata->bridge) {
957
-
encoder->bridge = hdata->bridge;
958
-
hdata->bridge->encoder = encoder;
959
957
ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
960
958
if (ret)
961
959
DRM_ERROR("Failed to attach bridge\n");
+17
-5
drivers/gpu/drm/exynos/exynos_mixer.c
+17
-5
drivers/gpu/drm/exynos/exynos_mixer.c
···
473
473
chroma_addr[1] = chroma_addr[0] + 0x40;
474
474
} else {
475
475
luma_addr[1] = luma_addr[0] + fb->pitches[0];
476
-
chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
476
+
chroma_addr[1] = chroma_addr[0] + fb->pitches[1];
477
477
}
478
478
} else {
479
479
luma_addr[1] = 0;
···
482
482
483
483
spin_lock_irqsave(&ctx->reg_slock, flags);
484
484
485
+
vp_reg_write(ctx, VP_SHADOW_UPDATE, 1);
485
486
/* interlace or progressive scan mode */
486
487
val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
487
488
vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
···
496
495
vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
497
496
VP_IMG_VSIZE(fb->height));
498
497
/* chroma plane for NV12/NV21 is half the height of the luma plane */
499
-
vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
498
+
vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) |
500
499
VP_IMG_VSIZE(fb->height / 2));
501
500
502
501
vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
503
-
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
504
502
vp_reg_write(ctx, VP_SRC_H_POSITION,
505
503
VP_SRC_H_POSITION_VAL(state->src.x));
506
-
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
507
-
508
504
vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
509
505
vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
506
+
510
507
if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
508
+
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h / 2);
509
+
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y / 2);
511
510
vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
512
511
vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
513
512
} else {
513
+
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
514
+
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
514
515
vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
515
516
vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
516
517
}
···
702
699
703
700
/* interlace scan need to check shadow register */
704
701
if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
702
+
if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
703
+
vp_reg_read(ctx, VP_SHADOW_UPDATE))
704
+
goto out;
705
+
706
+
base = mixer_reg_read(ctx, MXR_CFG);
707
+
shadow = mixer_reg_read(ctx, MXR_CFG_S);
708
+
if (base != shadow)
709
+
goto out;
710
+
705
711
base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
706
712
shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
707
713
if (base != shadow)
+1
drivers/gpu/drm/exynos/regs-mixer.h
+1
drivers/gpu/drm/exynos/regs-mixer.h
+37
-4
drivers/gpu/drm/i915/intel_cdclk.c
+37
-4
drivers/gpu/drm/i915/intel_cdclk.c
···
2302
2302
return 0;
2303
2303
}
2304
2304
2305
+
static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2306
+
{
2307
+
struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2308
+
struct intel_crtc *crtc;
2309
+
struct intel_crtc_state *crtc_state;
2310
+
int vco, i;
2311
+
2312
+
vco = intel_state->cdclk.logical.vco;
2313
+
if (!vco)
2314
+
vco = dev_priv->skl_preferred_vco_freq;
2315
+
2316
+
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2317
+
if (!crtc_state->base.enable)
2318
+
continue;
2319
+
2320
+
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2321
+
continue;
2322
+
2323
+
/*
2324
+
* DPLL0 VCO may need to be adjusted to get the correct
2325
+
* clock for eDP. This will affect cdclk as well.
2326
+
*/
2327
+
switch (crtc_state->port_clock / 2) {
2328
+
case 108000:
2329
+
case 216000:
2330
+
vco = 8640000;
2331
+
break;
2332
+
default:
2333
+
vco = 8100000;
2334
+
break;
2335
+
}
2336
+
}
2337
+
2338
+
return vco;
2339
+
}
2340
+
2305
2341
static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2306
2342
{
2307
-
struct drm_i915_private *dev_priv = to_i915(state->dev);
2308
2343
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2309
2344
int min_cdclk, cdclk, vco;
2310
2345
···
2347
2312
if (min_cdclk < 0)
2348
2313
return min_cdclk;
2349
2314
2350
-
vco = intel_state->cdclk.logical.vco;
2351
-
if (!vco)
2352
-
vco = dev_priv->skl_preferred_vco_freq;
2315
+
vco = skl_dpll0_vco(intel_state);
2353
2316
2354
2317
/*
2355
2318
* FIXME should also account for plane ratio
+2
drivers/gpu/drm/i915/intel_display.c
+2
drivers/gpu/drm/i915/intel_display.c
···
15178
15178
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15179
15179
if (crtc_state->base.active) {
15180
15180
intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15181
+
crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15182
+
crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15181
15183
intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15182
15184
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15183
15185
-20
drivers/gpu/drm/i915/intel_dp.c
-20
drivers/gpu/drm/i915/intel_dp.c
···
1881
1881
reduce_m_n);
1882
1882
}
1883
1883
1884
-
/*
1885
-
* DPLL0 VCO may need to be adjusted to get the correct
1886
-
* clock for eDP. This will affect cdclk as well.
1887
-
*/
1888
-
if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1889
-
int vco;
1890
-
1891
-
switch (pipe_config->port_clock / 2) {
1892
-
case 108000:
1893
-
case 216000:
1894
-
vco = 8640000;
1895
-
break;
1896
-
default:
1897
-
vco = 8100000;
1898
-
break;
1899
-
}
1900
-
1901
-
to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1902
-
}
1903
-
1904
1884
if (!HAS_DDI(dev_priv))
1905
1885
intel_dp_set_clock(encoder, pipe_config);
1906
1886
+2
-1
drivers/gpu/drm/i915/intel_lvds.c
+2
-1
drivers/gpu/drm/i915/intel_lvds.c
···
326
326
327
327
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
328
328
POSTING_READ(lvds_encoder->reg);
329
-
if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
329
+
330
+
if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
330
331
DRM_ERROR("timed out waiting for panel to power on\n");
331
332
332
333
intel_panel_enable_backlight(pipe_config, conn_state);
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
···
214
214
INIT_LIST_HEAD(&nvbo->entry);
215
215
INIT_LIST_HEAD(&nvbo->vma_list);
216
216
nvbo->bo.bdev = &drm->ttm.bdev;
217
-
nvbo->cli = cli;
218
217
219
218
/* This is confusing, and doesn't actually mean we want an uncached
220
219
* mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
-2
drivers/gpu/drm/nouveau/nouveau_bo.h
-2
drivers/gpu/drm/nouveau/nouveau_bo.h
+3
-3
drivers/gpu/drm/nouveau/nouveau_ttm.c
+3
-3
drivers/gpu/drm/nouveau/nouveau_ttm.c
···
63
63
struct ttm_mem_reg *reg)
64
64
{
65
65
struct nouveau_bo *nvbo = nouveau_bo(bo);
66
-
struct nouveau_drm *drm = nvbo->cli->drm;
66
+
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
67
67
struct nouveau_mem *mem;
68
68
int ret;
69
69
···
103
103
struct ttm_mem_reg *reg)
104
104
{
105
105
struct nouveau_bo *nvbo = nouveau_bo(bo);
106
-
struct nouveau_drm *drm = nvbo->cli->drm;
106
+
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
107
107
struct nouveau_mem *mem;
108
108
int ret;
109
109
···
131
131
struct ttm_mem_reg *reg)
132
132
{
133
133
struct nouveau_bo *nvbo = nouveau_bo(bo);
134
-
struct nouveau_drm *drm = nvbo->cli->drm;
134
+
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
135
135
struct nouveau_mem *mem;
136
136
int ret;
137
137
+3
-4
drivers/gpu/drm/nouveau/nv50_display.c
+3
-4
drivers/gpu/drm/nouveau/nv50_display.c
···
3264
3264
3265
3265
drm_connector_unregister(&mstc->connector);
3266
3266
3267
-
drm_modeset_lock_all(drm->dev);
3268
3267
drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3268
+
3269
+
drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
3269
3270
mstc->port = NULL;
3270
-
drm_modeset_unlock_all(drm->dev);
3271
+
drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
3271
3272
3272
3273
drm_connector_unreference(&mstc->connector);
3273
3274
}
···
3278
3277
{
3279
3278
struct nouveau_drm *drm = nouveau_drm(connector->dev);
3280
3279
3281
-
drm_modeset_lock_all(drm->dev);
3282
3280
drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3283
-
drm_modeset_unlock_all(drm->dev);
3284
3281
3285
3282
drm_connector_register(connector);
3286
3283
}
+13
-7
drivers/gpu/drm/omapdrm/dss/dispc.c
+13
-7
drivers/gpu/drm/omapdrm/dss/dispc.c
···
828
828
h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
829
829
v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
830
830
831
+
if (!h_coef || !v_coef) {
832
+
dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n",
833
+
__func__);
834
+
return;
835
+
}
836
+
831
837
for (i = 0; i < 8; i++) {
832
838
u32 h, hv;
833
839
···
2348
2342
}
2349
2343
2350
2344
if (in_width > maxsinglelinewidth) {
2351
-
DSSERR("Cannot scale max input width exceeded");
2345
+
DSSERR("Cannot scale max input width exceeded\n");
2352
2346
return -EINVAL;
2353
2347
}
2354
2348
return 0;
···
2430
2424
}
2431
2425
2432
2426
if (in_width > (maxsinglelinewidth * 2)) {
2433
-
DSSERR("Cannot setup scaling");
2434
-
DSSERR("width exceeds maximum width possible");
2427
+
DSSERR("Cannot setup scaling\n");
2428
+
DSSERR("width exceeds maximum width possible\n");
2435
2429
return -EINVAL;
2436
2430
}
2437
2431
2438
2432
if (in_width > maxsinglelinewidth && *five_taps) {
2439
-
DSSERR("cannot setup scaling with five taps");
2433
+
DSSERR("cannot setup scaling with five taps\n");
2440
2434
return -EINVAL;
2441
2435
}
2442
2436
return 0;
···
2478
2472
in_width > maxsinglelinewidth && ++*decim_x);
2479
2473
2480
2474
if (in_width > maxsinglelinewidth) {
2481
-
DSSERR("Cannot scale width exceeds max line width");
2475
+
DSSERR("Cannot scale width exceeds max line width\n");
2482
2476
return -EINVAL;
2483
2477
}
2484
2478
···
2496
2490
* bandwidth. Despite what theory says this appears to
2497
2491
* be true also for 16-bit color formats.
2498
2492
*/
2499
-
DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)", *decim_x);
2493
+
DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x);
2500
2494
2501
2495
return -EINVAL;
2502
2496
}
···
4639
4633
i734_buf.size, &i734_buf.paddr,
4640
4634
GFP_KERNEL);
4641
4635
if (!i734_buf.vaddr) {
4642
-
dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed",
4636
+
dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed\n",
4643
4637
__func__);
4644
4638
return -ENOMEM;
4645
4639
}
+1
-1
drivers/gpu/drm/omapdrm/dss/hdmi4.c
+1
-1
drivers/gpu/drm/omapdrm/dss/hdmi4.c
+6
-1
drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+6
-1
drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
···
922
922
{
923
923
const struct hdmi4_features *features;
924
924
struct resource *res;
925
+
const struct soc_device_attribute *soc;
925
926
926
-
features = soc_device_match(hdmi4_soc_devices)->data;
927
+
soc = soc_device_match(hdmi4_soc_devices);
928
+
if (!soc)
929
+
return -ENODEV;
930
+
931
+
features = soc->data;
927
932
core->cts_swmode = features->cts_swmode;
928
933
core->audio_use_mclk = features->audio_use_mclk;
929
934
+1
-1
drivers/gpu/drm/omapdrm/dss/hdmi5.c
+1
-1
drivers/gpu/drm/omapdrm/dss/hdmi5.c
+10
drivers/gpu/drm/omapdrm/omap_connector.c
+10
drivers/gpu/drm/omapdrm/omap_connector.c
···
121
121
if (dssdrv->read_edid) {
122
122
void *edid = kzalloc(MAX_EDID, GFP_KERNEL);
123
123
124
+
if (!edid)
125
+
return 0;
126
+
124
127
if ((dssdrv->read_edid(dssdev, edid, MAX_EDID) > 0) &&
125
128
drm_edid_is_valid(edid)) {
126
129
drm_mode_connector_update_edid_property(
···
141
138
} else {
142
139
struct drm_display_mode *mode = drm_mode_create(dev);
143
140
struct videomode vm = {0};
141
+
142
+
if (!mode)
143
+
return 0;
144
144
145
145
dssdrv->get_timings(dssdev, &vm);
146
146
···
206
200
if (!r) {
207
201
/* check if vrefresh is still valid */
208
202
new_mode = drm_mode_duplicate(dev, mode);
203
+
204
+
if (!new_mode)
205
+
return MODE_BAD;
206
+
209
207
new_mode->clock = vm.pixelclock / 1000;
210
208
new_mode->vrefresh = 0;
211
209
if (mode->vrefresh == drm_mode_vrefresh(new_mode))
+5
-1
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+5
-1
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
···
401
401
struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,
402
402
u16 h, u16 align)
403
403
{
404
-
struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
404
+
struct tiler_block *block;
405
405
u32 min_align = 128;
406
406
int ret;
407
407
unsigned long flags;
408
408
u32 slot_bytes;
409
+
410
+
block = kzalloc(sizeof(*block), GFP_KERNEL);
411
+
if (!block)
412
+
return ERR_PTR(-ENOMEM);
409
413
410
414
BUG_ON(!validfmt(fmt));
411
415
+1
-1
drivers/gpu/drm/omapdrm/tcm-sita.c
+1
-1
drivers/gpu/drm/omapdrm/tcm-sita.c
+8
-3
drivers/gpu/drm/ttm/ttm_page_alloc.c
+8
-3
drivers/gpu/drm/ttm/ttm_page_alloc.c
···
910
910
while (npages >= HPAGE_PMD_NR) {
911
911
gfp_t huge_flags = gfp_flags;
912
912
913
-
huge_flags |= GFP_TRANSHUGE;
913
+
huge_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
914
+
__GFP_KSWAPD_RECLAIM;
914
915
huge_flags &= ~__GFP_MOVABLE;
915
916
huge_flags &= ~__GFP_COMP;
916
917
p = alloc_pages(huge_flags, HPAGE_PMD_ORDER);
···
1028
1027
GFP_USER | GFP_DMA32, "uc dma", 0);
1029
1028
1030
1029
ttm_page_pool_init_locked(&_manager->wc_pool_huge,
1031
-
GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP),
1030
+
(GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
1031
+
__GFP_KSWAPD_RECLAIM) &
1032
+
~(__GFP_MOVABLE | __GFP_COMP),
1032
1033
"wc huge", order);
1033
1034
1034
1035
ttm_page_pool_init_locked(&_manager->uc_pool_huge,
1035
-
GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP)
1036
+
(GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
1037
+
__GFP_KSWAPD_RECLAIM) &
1038
+
~(__GFP_MOVABLE | __GFP_COMP)
1036
1039
, "uc huge", order);
1037
1040
1038
1041
_manager->options.max_size = max_pages;
+2
-1
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+2
-1
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+22
-3
drivers/gpu/drm/vc4/vc4_dpi.c
+22
-3
drivers/gpu/drm/vc4/vc4_dpi.c
···
96
96
struct platform_device *pdev;
97
97
98
98
struct drm_encoder *encoder;
99
-
struct drm_connector *connector;
100
99
101
100
void __iomem *regs;
102
101
···
163
164
164
165
static void vc4_dpi_encoder_enable(struct drm_encoder *encoder)
165
166
{
167
+
struct drm_device *dev = encoder->dev;
166
168
struct drm_display_mode *mode = &encoder->crtc->mode;
167
169
struct vc4_dpi_encoder *vc4_encoder = to_vc4_dpi_encoder(encoder);
168
170
struct vc4_dpi *dpi = vc4_encoder->dpi;
171
+
struct drm_connector_list_iter conn_iter;
172
+
struct drm_connector *connector = NULL, *connector_scan;
169
173
u32 dpi_c = DPI_ENABLE | DPI_OUTPUT_ENABLE_MODE;
170
174
int ret;
171
175
172
-
if (dpi->connector->display_info.num_bus_formats) {
173
-
u32 bus_format = dpi->connector->display_info.bus_formats[0];
176
+
/* Look up the connector attached to DPI so we can get the
177
+
* bus_format. Ideally the bridge would tell us the
178
+
* bus_format we want, but it doesn't yet, so assume that it's
179
+
* uniform throughout the bridge chain.
180
+
*/
181
+
drm_connector_list_iter_begin(dev, &conn_iter);
182
+
drm_for_each_connector_iter(connector_scan, &conn_iter) {
183
+
if (connector_scan->encoder == encoder) {
184
+
connector = connector_scan;
185
+
break;
186
+
}
187
+
}
188
+
drm_connector_list_iter_end(&conn_iter);
189
+
190
+
if (connector && connector->display_info.num_bus_formats) {
191
+
u32 bus_format = connector->display_info.bus_formats[0];
174
192
175
193
switch (bus_format) {
176
194
case MEDIA_BUS_FMT_RGB888_1X24:
···
215
199
DRM_ERROR("Unknown media bus format %d\n", bus_format);
216
200
break;
217
201
}
202
+
} else {
203
+
/* Default to 24bit if no connector found. */
204
+
dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);
218
205
}
219
206
220
207
if (mode->flags & DRM_MODE_FLAG_NHSYNC)