Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-gt-next-2025-07-02' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes:
Fixes/improvements/new stuff:
- Avoid GuC scheduling stalls [guc] (Julia Filipchuk)
- Remove force_probe requirement for DG1 (Ville Syrjälä)
- Handle errors correctly to avoid losing GuC-2-Host messages [guc] (Jesus Narvaez)
- Avoid double wakeref put if GuC context deregister failed [guc] (Jesus Narvaez)
- Avoid timeline memory leak with signals and legacy platforms [ringbuf] (Janusz Krzysztofik)
- Fix MEI (discrete) interrupt handler on RT kernels [gsc] (Junxiao Chang)
Miscellaneous:
- Allow larger memory allocation [selftest] (Mikolaj Wasiak)
- Use provided dma_fence_is_chain (Tvrtko Ursulin)
- Fix build error with GCOV and AutoFDO enabled [pmu] (Tzung-Bi Shih)
- Fix build error some more (Arnd Bergmann)
- Reduce stack usage in igt_vma_pin1() (Arnd Bergmann)
- Move out engine related macros from i915_drv.h (Krzysztof Karas)
- Move GEM_QUIRK_PIN_SWIZZLED_PAGES to i915_gem.h (Krzysztof Karas)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://lore.kernel.org/r/aGTjUBeOQFw26bRT@linux
+71
-77
+1
-6
drivers/gpu/drm/i915/gem/i915_gem_wait.c
+1
-6
drivers/gpu/drm/i915/gem/i915_gem_wait.c
···
106
106
rcu_read_unlock();
107
107
}
108
108
109
-
static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
110
-
{
111
-
return fence->ops == &dma_fence_chain_ops;
112
-
}
113
-
114
109
void i915_gem_fence_wait_priority(struct dma_fence *fence,
115
110
const struct i915_sched_attr *attr)
116
111
{
···
121
126
122
127
for (i = 0; i < array->num_fences; i++)
123
128
fence_set_priority(array->fences[i], attr);
124
-
} else if (__dma_fence_is_chain(fence)) {
129
+
} else if (dma_fence_is_chain(fence)) {
125
130
struct dma_fence *iter;
126
131
127
132
/* The chain is ordered; if we boost the last, we boost all */
+31
drivers/gpu/drm/i915/gt/intel_engine.h
+31
drivers/gpu/drm/i915/gt/intel_engine.h
···
79
79
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
80
80
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
81
81
82
+
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
83
+
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
84
+
85
+
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
86
+
unsigned int first__ = (first); \
87
+
unsigned int count__ = (count); \
88
+
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
89
+
})
90
+
91
+
#define ENGINE_INSTANCES_MASK(gt, first, count) \
92
+
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
93
+
94
+
#define RCS_MASK(gt) \
95
+
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
96
+
#define BCS_MASK(gt) \
97
+
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
98
+
#define VDBOX_MASK(gt) \
99
+
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
100
+
#define VEBOX_MASK(gt) \
101
+
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
102
+
#define CCS_MASK(gt) \
103
+
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
104
+
82
105
#define GEN6_RING_FAULT_REG_READ(engine__) \
83
106
intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
84
107
···
377
354
u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value);
378
355
u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);
379
356
u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);
357
+
358
+
#define rb_to_uabi_engine(rb) \
359
+
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
360
+
361
+
#define for_each_uabi_engine(engine__, i915__) \
362
+
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
363
+
(engine__); \
364
+
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
380
365
381
366
#endif /* _INTEL_RINGBUFFER_H_ */
+1
-1
drivers/gpu/drm/i915/gt/intel_gsc.c
+1
-1
drivers/gpu/drm/i915/gt/intel_gsc.c
+2
-1
drivers/gpu/drm/i915/gt/intel_ring_submission.c
+2
-1
drivers/gpu/drm/i915/gt/intel_ring_submission.c
···
610
610
/* One ringbuffer to rule them all */
611
611
GEM_BUG_ON(!engine->legacy.ring);
612
612
ce->ring = engine->legacy.ring;
613
-
ce->timeline = intel_timeline_get(engine->legacy.timeline);
614
613
615
614
GEM_BUG_ON(ce->state);
616
615
if (engine->context_size) {
···
621
622
622
623
ce->state = vma;
623
624
}
625
+
626
+
ce->timeline = intel_timeline_get(engine->legacy.timeline);
624
627
625
628
return 0;
626
629
}
+6
-1
drivers/gpu/drm/i915/gt/uc/intel_guc.c
+6
-1
drivers/gpu/drm/i915/gt/uc/intel_guc.c
···
313
313
*
314
314
* The same WA bit is used for both and 22011391025 is applicable to
315
315
* all DG2.
316
+
*
317
+
* Platforms post DG2 prevent this issue in hardware by stalling
318
+
* submissions. With this flag GuC will schedule as to avoid such
319
+
* stalls.
316
320
*/
317
-
if (IS_DG2(gt->i915))
321
+
if (IS_DG2(gt->i915) ||
322
+
(CCS_MASK(gt) && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)))
318
323
flags |= GUC_WA_DUAL_QUEUE;
319
324
320
325
/* Wa_22011802037: graphics version 11/12 */
-33
drivers/gpu/drm/i915/i915_drv.h
-33
drivers/gpu/drm/i915/i915_drv.h
···
66
66
struct intel_pxp;
67
67
struct vlv_s0ix_state;
68
68
69
-
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
70
-
71
69
/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
72
70
struct i915_dsm {
73
71
/*
···
352
354
return i915->gt[0];
353
355
}
354
356
355
-
#define rb_to_uabi_engine(rb) \
356
-
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
357
-
358
-
#define for_each_uabi_engine(engine__, i915__) \
359
-
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
360
-
(engine__); \
361
-
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
362
-
363
357
#define INTEL_INFO(i915) ((i915)->__info)
364
358
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
365
359
#define DRIVER_CAPS(i915) (&(i915)->caps)
···
559
569
560
570
#define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
561
571
#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))
562
-
563
-
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
564
-
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
565
-
566
-
#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
567
-
unsigned int first__ = (first); \
568
-
unsigned int count__ = (count); \
569
-
((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
570
-
})
571
-
572
-
#define ENGINE_INSTANCES_MASK(gt, first, count) \
573
-
__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
574
-
575
-
#define RCS_MASK(gt) \
576
-
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
577
-
#define BCS_MASK(gt) \
578
-
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
579
-
#define VDBOX_MASK(gt) \
580
-
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
581
-
#define VEBOX_MASK(gt) \
582
-
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
583
-
#define CCS_MASK(gt) \
584
-
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
585
572
586
573
#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
587
574
+2
drivers/gpu/drm/i915/i915_gem.h
+2
drivers/gpu/drm/i915/i915_gem.h
-1
drivers/gpu/drm/i915/i915_pci.c
-1
drivers/gpu/drm/i915/i915_pci.c
+3
-3
drivers/gpu/drm/i915/i915_pmu.c
+3
-3
drivers/gpu/drm/i915/i915_pmu.c
···
108
108
return other_bit(config);
109
109
}
110
110
111
-
static u32 config_mask(const u64 config)
111
+
static __always_inline u32 config_mask(const u64 config)
112
112
{
113
113
unsigned int bit = config_bit(config);
114
114
115
-
if (__builtin_constant_p(config))
115
+
if (__builtin_constant_p(bit))
116
116
BUILD_BUG_ON(bit >
117
117
BITS_PER_TYPE(typeof_member(struct i915_pmu,
118
118
enable)) - 1);
···
121
121
BITS_PER_TYPE(typeof_member(struct i915_pmu,
122
122
enable)) - 1);
123
123
124
-
return BIT(config_bit(config));
124
+
return BIT(bit);
125
125
}
126
126
127
127
static bool is_engine_event(struct perf_event *event)
+20
drivers/gpu/drm/i915/i915_vma.c
+20
drivers/gpu/drm/i915/i915_vma.c
···
1607
1607
return err;
1608
1608
}
1609
1609
1610
+
int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
1611
+
{
1612
+
struct i915_gem_ww_ctx ww;
1613
+
int err;
1614
+
1615
+
i915_gem_ww_ctx_init(&ww, true);
1616
+
retry:
1617
+
err = i915_gem_object_lock(vma->obj, &ww);
1618
+
if (!err)
1619
+
err = i915_vma_pin_ww(vma, &ww, size, alignment, flags);
1620
+
if (err == -EDEADLK) {
1621
+
err = i915_gem_ww_ctx_backoff(&ww);
1622
+
if (!err)
1623
+
goto retry;
1624
+
}
1625
+
i915_gem_ww_ctx_fini(&ww);
1626
+
1627
+
return err;
1628
+
}
1629
+
1610
1630
static void flush_idle_contexts(struct intel_gt *gt)
1611
1631
{
1612
1632
struct intel_engine_cs *engine;
+2
-20
drivers/gpu/drm/i915/i915_vma.h
+2
-20
drivers/gpu/drm/i915/i915_vma.h
···
289
289
i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
290
290
u64 size, u64 alignment, u64 flags);
291
291
292
-
static inline int __must_check
293
-
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
294
-
{
295
-
struct i915_gem_ww_ctx ww;
296
-
int err;
297
-
298
-
i915_gem_ww_ctx_init(&ww, true);
299
-
retry:
300
-
err = i915_gem_object_lock(vma->obj, &ww);
301
-
if (!err)
302
-
err = i915_vma_pin_ww(vma, &ww, size, alignment, flags);
303
-
if (err == -EDEADLK) {
304
-
err = i915_gem_ww_ctx_backoff(&ww);
305
-
if (!err)
306
-
goto retry;
307
-
}
308
-
i915_gem_ww_ctx_fini(&ww);
309
-
310
-
return err;
311
-
}
292
+
int __must_check
293
+
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags);
312
294
313
295
int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
314
296
u32 align, unsigned int flags);
+3
-11
drivers/gpu/drm/i915/selftests/intel_memory_region.c
+3
-11
drivers/gpu/drm/i915/selftests/intel_memory_region.c
···
413
413
414
414
close_objects(mem, &objects);
415
415
416
-
/*
417
-
* While we should be able allocate everything without any flag
418
-
* restrictions, if we consider I915_BO_ALLOC_CONTIGUOUS then we are
419
-
* actually limited to the largest power-of-two for the region size i.e
420
-
* max_order, due to the inner workings of the buddy allocator. So make
421
-
* sure that does indeed hold true.
422
-
*/
423
-
424
-
obj = igt_object_create(mem, &objects, size, I915_BO_ALLOC_CONTIGUOUS);
416
+
obj = igt_object_create(mem, &objects, roundup_pow_of_two(size),
417
+
I915_BO_ALLOC_CONTIGUOUS);
425
418
if (!IS_ERR(obj)) {
426
419
pr_err("%s too large contiguous allocation was not rejected\n",
427
420
__func__);
···
422
429
goto out_close;
423
430
}
424
431
425
-
obj = igt_object_create(mem, &objects, rounddown_pow_of_two(size),
426
-
I915_BO_ALLOC_CONTIGUOUS);
432
+
obj = igt_object_create(mem, &objects, size, I915_BO_ALLOC_CONTIGUOUS);
427
433
if (IS_ERR(obj)) {
428
434
pr_err("%s largest possible contiguous allocation failed\n",
429
435
__func__);