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cxl/pci: Remove unnecessary CXL Endpoint handling helper functions

The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras()
are unnecessary helper functions used only for Endpoints. Remove these
functions as they are not common for all CXL devices and do not provide
value for EP handling.

Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras()
to cxl_handle_cor_ras().

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Joshua Hahn <joshua.hahnjy@gmail.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20260114182055.46029-5-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Terry Bowman and committed by
Dave Jiang ca3d1a53 7c29ba02

+8 -18
+8 -18
drivers/cxl/core/pci.c
··· 632 632 } 633 633 EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); 634 634 635 - static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, 636 - void __iomem *ras_base) 635 + static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, 636 + void __iomem *ras_base) 637 637 { 638 638 void __iomem *addr; 639 639 u32 status; ··· 647 647 writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); 648 648 trace_cxl_aer_correctable_error(cxlds->cxlmd, status); 649 649 } 650 - } 651 - 652 - static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) 653 - { 654 - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); 655 650 } 656 651 657 652 /* CXL spec rev3.0 8.2.4.16.1 */ ··· 670 675 * Log the state of the RAS status registers and prepare them to log the 671 676 * next error status. Return 1 if reset needed. 672 677 */ 673 - static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, 674 - void __iomem *ras_base) 678 + static bool cxl_handle_ras(struct cxl_dev_state *cxlds, 679 + void __iomem *ras_base) 675 680 { 676 681 u32 hl[CXL_HEADERLOG_SIZE_U32]; 677 682 void __iomem *addr; ··· 702 707 writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); 703 708 704 709 return true; 705 - } 706 - 707 - static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) 708 - { 709 - return __cxl_handle_ras(cxlds, cxlds->regs.ras); 710 710 } 711 711 712 712 #ifdef CONFIG_PCIEAER_CXL ··· 782 792 static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, 783 793 struct cxl_dport *dport) 784 794 { 785 - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); 795 + return cxl_handle_cor_ras(cxlds, dport->regs.ras); 786 796 } 787 797 788 798 static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, 789 799 struct cxl_dport *dport) 790 800 { 791 - return __cxl_handle_ras(cxlds, dport->regs.ras); 801 + return cxl_handle_ras(cxlds, dport->regs.ras); 792 802 } 793 803 794 804 /* ··· 885 895 if (cxlds->rcd) 886 896 cxl_handle_rdport_errors(cxlds); 887 897 888 - cxl_handle_endpoint_cor_ras(cxlds); 898 + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); 889 899 } 890 900 } 891 901 EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); ··· 914 924 * chance the situation is recoverable dump the status of the RAS 915 925 * capability registers and bounce the active state of the memdev. 916 926 */ 917 - ue = cxl_handle_endpoint_ras(cxlds); 927 + ue = cxl_handle_ras(cxlds, cxlds->regs.ras); 918 928 } 919 929 920 930