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dt-bindings: usb: ti,dwc3: convert to DT schema

Convert OMAP DWC3 USB Glue Layer binding to DT schema.
Changes made during the conversion:
- Drop the ti,hwmods property, as it is not used by any in-tree DTS files.

Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260127-ti-usb-v2-2-9dd6a65b43df@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Charan Pedumuru and committed by
Greg Kroah-Hartman
ca47d656 70fcdc82

+100 -80
-80
Documentation/devicetree/bindings/usb/omap-usb.txt
··· 1 - OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS 2 - 3 - OMAP MUSB GLUE 4 - - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" 5 - - ti,hwmods : must be "usb_otg_hs" 6 - - multipoint : Should be "1" indicating the musb controller supports 7 - multipoint. This is a MUSB configuration-specific setting. 8 - - num-eps : Specifies the number of endpoints. This is also a 9 - MUSB configuration-specific setting. Should be set to "16" 10 - - ram-bits : Specifies the ram address size. Should be set to "12" 11 - - interface-type : This is a board specific setting to describe the type of 12 - interface between the controller and the phy. It should be "0" or "1" 13 - specifying ULPI and UTMI respectively. 14 - - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" 15 - represents PERIPHERAL. 16 - - power : Should be "50". This signifies the controller can supply up to 17 - 100mA when operating in host mode. 18 - - usb-phy : the phandle for the PHY device 19 - - phys : the phandle for the PHY device (used by generic PHY framework) 20 - - phy-names : the names of the PHY corresponding to the PHYs present in the 21 - *phy* phandle. 22 - 23 - Optional properties: 24 - - ctrl-module : phandle of the control module this glue uses to write to 25 - mailbox 26 - 27 - SOC specific device node entry 28 - usb_otg_hs: usb_otg_hs@4a0ab000 { 29 - compatible = "ti,omap4-musb"; 30 - ti,hwmods = "usb_otg_hs"; 31 - multipoint = <1>; 32 - num-eps = <16>; 33 - ram-bits = <12>; 34 - ctrl-module = <&omap_control_usb>; 35 - phys = <&usb2_phy>; 36 - phy-names = "usb2-phy"; 37 - }; 38 - 39 - Board specific device node entry 40 - &usb_otg_hs { 41 - interface-type = <1>; 42 - mode = <3>; 43 - power = <50>; 44 - }; 45 - 46 - OMAP DWC3 GLUE 47 - - compatible : Should be 48 - * "ti,dwc3" for OMAP5 and DRA7 49 - * "ti,am437x-dwc3" for AM437x 50 - - ti,hwmods : Should be "usb_otg_ss" 51 - - reg : Address and length of the register set for the device. 52 - - interrupts : The irq number of this device that is used to interrupt the 53 - MPU 54 - - #address-cells, #size-cells : Must be present if the device has sub-nodes 55 - - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID. 56 - It should be set to "1" for HW mode and "2" for SW mode. 57 - - ranges: the child address space are mapped 1:1 onto the parent address space 58 - 59 - Optional Properties: 60 - - extcon : phandle for the extcon device omap dwc3 uses to detect 61 - connect/disconnect events. 62 - - vbus-supply : phandle to the regulator device tree node if needed. 63 - 64 - Sub-nodes: 65 - The dwc3 core should be added as subnode to omap dwc3 glue. 66 - - dwc3 : 67 - The binding details of dwc3 can be found in: 68 - Documentation/devicetree/bindings/usb/snps,dwc3.yaml 69 - 70 - omap_dwc3 { 71 - compatible = "ti,dwc3"; 72 - ti,hwmods = "usb_otg_ss"; 73 - reg = <0x4a020000 0x1ff>; 74 - interrupts = <0 93 4>; 75 - #address-cells = <1>; 76 - #size-cells = <1>; 77 - utmi-mode = <2>; 78 - ranges; 79 - }; 80 -
+100
Documentation/devicetree/bindings/usb/ti,dwc3.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/usb/ti,dwc3.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Texas Instruments OMAP DWC3 USB Glue Layer 8 + 9 + maintainers: 10 + - Felipe Balbi <balbi@ti.com> 11 + 12 + description: 13 + Texas Instruments glue layer for Synopsys DesignWare USB3 (DWC3) 14 + controller on OMAP and AM43xx SoCs. Manages SoC-specific integration 15 + including register mapping, interrupt routing, UTMI/PIPE interface mode 16 + selection (HW/SW), and child DWC3 core instantiation via address space 17 + translation. Supports both legacy single-instance and multi-instance 18 + (numbered) configurations. 19 + 20 + properties: 21 + compatible: 22 + enum: 23 + - ti,dwc3 24 + - ti,am437x-dwc3 25 + 26 + reg: 27 + maxItems: 1 28 + 29 + interrupts: 30 + maxItems: 1 31 + 32 + utmi-mode: 33 + $ref: /schemas/types.yaml#/definitions/uint32 34 + description: 35 + Controls the source of UTMI/PIPE status for VBUS and OTG ID. 36 + 1 for HW mode, 2 for SW mode. 37 + enum: [1, 2] 38 + 39 + "#address-cells": 40 + const: 1 41 + 42 + "#size-cells": 43 + const: 1 44 + 45 + ranges: true 46 + 47 + extcon: 48 + $ref: /schemas/types.yaml#/definitions/phandle 49 + description: 50 + Phandle for the extcon device used to detect connect/ 51 + disconnect events. 52 + 53 + vbus-supply: 54 + description: Phandle to the regulator device tree node if needed. 55 + 56 + patternProperties: 57 + "^usb@[0-9a-f]+$": 58 + type: object 59 + $ref: snps,dwc3.yaml# 60 + unevaluatedProperties: false 61 + 62 + required: 63 + - reg 64 + - compatible 65 + - interrupts 66 + - "#address-cells" 67 + - "#size-cells" 68 + - utmi-mode 69 + - ranges 70 + 71 + unevaluatedProperties: false 72 + 73 + examples: 74 + - | 75 + #include <dt-bindings/interrupt-controller/arm-gic.h> 76 + omap_dwc3_1@0 { 77 + compatible = "ti,dwc3"; 78 + reg = <0x0 0x10000>; 79 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 80 + #address-cells = <1>; 81 + #size-cells = <1>; 82 + utmi-mode = <2>; 83 + ranges = <0 0 0x20000>; 84 + 85 + usb@10000 { 86 + compatible = "snps,dwc3"; 87 + reg = <0x10000 0x17000>; 88 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 89 + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 90 + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 91 + interrupt-names = "peripheral", "host", "otg"; 92 + phys = <&usb2_phy1>, <&usb3_phy1>; 93 + phy-names = "usb2-phy", "usb3-phy"; 94 + maximum-speed = "super-speed"; 95 + dr_mode = "otg"; 96 + snps,dis_u3_susphy_quirk; 97 + snps,dis_u2_susphy_quirk; 98 + }; 99 + }; 100 + ...