Merge tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm

+1 -8

drivers/char/agp/isoch.c

··· 84 84 unsigned int cdev = 0; 85 85 u32 mnistat, tnistat, tstatus, mcmd; 86 86 u16 tnicmd, mnicmd; 87 - u8 mcapndx; 88 87 u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async; 89 88 u32 step, rem, rem_isoch, rem_async; 90 89 int ret = 0; ··· 136 137 list_for_each(pos, head) { 137 138 cur = list_entry(pos, struct agp_3_5_dev, list); 138 139 dev = cur->dev; 139 - 140 - mcapndx = cur->capndx; 141 140 142 141 pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat); 143 142 ··· 248 251 cur = master[cdev].dev; 249 252 dev = cur->dev; 250 253 251 - mcapndx = cur->capndx; 252 - 253 254 master[cdev].rq += (cdev == ndevs - 1) 254 255 ? (rem_async + rem_isoch) : step; 255 256 ··· 314 319 { 315 320 struct pci_dev *td = bridge->dev, *dev = NULL; 316 321 u8 mcapndx; 317 - u32 isoch, arqsz; 322 + u32 isoch; 318 323 u32 tstatus, mstatus, ncapid; 319 324 u32 mmajor; 320 325 u16 mpstat; ··· 328 333 isoch = (tstatus >> 17) & 0x1; 329 334 if (isoch == 0) /* isoch xfers not available, bail out. */ 330 335 return -ENODEV; 331 - 332 - arqsz = (tstatus >> 13) & 0x7; 333 336 334 337 /* 335 338 * Allocate a head for our AGP 3.5 device list

+11 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

··· 613 613 bool d3_supported = false; 614 614 struct pci_dev *parent_pdev; 615 615 616 - while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) { 616 + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 617 + vga_count++; 618 + 619 + has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); 620 + 621 + parent_pdev = pci_upstream_bridge(pdev); 622 + d3_supported |= parent_pdev && parent_pdev->bridge_d3; 623 + amdgpu_atpx_get_quirks(pdev); 624 + } 625 + 626 + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 617 627 vga_count++; 618 628 619 629 has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

··· 1488 1488 1489 1489 /* Start rlc autoload after psp recieved all the gfx firmware */ 1490 1490 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 1491 - AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) { 1491 + AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 1492 1492 ret = psp_rlc_autoload(psp); 1493 1493 if (ret) { 1494 1494 DRM_ERROR("Failed to start rlc autoload\n");

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

··· 292 292 AMDGPU_UCODE_ID_CP_MEC2_JT, 293 293 AMDGPU_UCODE_ID_CP_MES, 294 294 AMDGPU_UCODE_ID_CP_MES_DATA, 295 - AMDGPU_UCODE_ID_RLC_G, 296 295 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 297 296 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 298 297 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 298 + AMDGPU_UCODE_ID_RLC_G, 299 299 AMDGPU_UCODE_ID_STORAGE, 300 300 AMDGPU_UCODE_ID_SMC, 301 301 AMDGPU_UCODE_ID_UVD,

+4 -11

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 1052 1052 case CHIP_VEGA20: 1053 1053 break; 1054 1054 case CHIP_RAVEN: 1055 - /* Disable GFXOFF on original raven. There are combinations 1056 - * of sbios and platforms that are not stable. 1057 - */ 1058 - if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)) 1059 - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1060 - else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) 1061 - &&((adev->gfx.rlc_fw_version != 106 && 1062 - adev->gfx.rlc_fw_version < 531) || 1063 - (adev->gfx.rlc_fw_version == 53815) || 1064 - (adev->gfx.rlc_feature_version < 1) || 1065 - !adev->gfx.rlc.is_rlc_v2_1)) 1055 + if (!(adev->rev_id >= 0x8 || 1056 + adev->pdev->device == 0x15d8) && 1057 + (adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */ 1058 + !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */ 1066 1059 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1067 1060 1068 1061 if (adev->pm.pp_feature & PP_GFXOFF_MASK)

+1

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

··· 866 866 smu->smu_baco.platform_support = false; 867 867 868 868 mutex_init(&smu->sensor_lock); 869 + mutex_init(&smu->metrics_lock); 869 870 870 871 smu->watermarks_bitmap = 0; 871 872 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

+3

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

··· 862 862 struct smu_table_context *smu_table= &smu->smu_table; 863 863 int ret = 0; 864 864 865 + mutex_lock(&smu->metrics_lock); 865 866 if (!smu_table->metrics_time || 866 867 time_after(jiffies, smu_table->metrics_time + HZ / 1000)) { 867 868 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, 868 869 (void *)smu_table->metrics_table, false); 869 870 if (ret) { 870 871 pr_info("Failed to export SMU metrics table!\n"); 872 + mutex_unlock(&smu->metrics_lock); 871 873 return ret; 872 874 } 873 875 smu_table->metrics_time = jiffies; 874 876 } 875 877 876 878 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t)); 879 + mutex_unlock(&smu->metrics_lock); 877 880 878 881 return ret; 879 882 }

+1

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

··· 349 349 const struct pptable_funcs *ppt_funcs; 350 350 struct mutex mutex; 351 351 struct mutex sensor_lock; 352 + struct mutex metrics_lock; 352 353 uint64_t pool_size; 353 354 354 355 struct smu_table_context smu_table;

+3

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

··· 562 562 struct smu_table_context *smu_table= &smu->smu_table; 563 563 int ret = 0; 564 564 565 + mutex_lock(&smu->metrics_lock); 565 566 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) { 566 567 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, 567 568 (void *)smu_table->metrics_table, false); 568 569 if (ret) { 569 570 pr_info("Failed to export SMU metrics table!\n"); 571 + mutex_unlock(&smu->metrics_lock); 570 572 return ret; 571 573 } 572 574 smu_table->metrics_time = jiffies; 573 575 } 574 576 575 577 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t)); 578 + mutex_unlock(&smu->metrics_lock); 576 579 577 580 return ret; 578 581 }

+3

drivers/gpu/drm/amd/powerplay/vega20_ppt.c

··· 1678 1678 struct smu_table_context *smu_table= &smu->smu_table; 1679 1679 int ret = 0; 1680 1680 1681 + mutex_lock(&smu->metrics_lock); 1681 1682 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) { 1682 1683 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, 1683 1684 (void *)smu_table->metrics_table, false); 1684 1685 if (ret) { 1685 1686 pr_info("Failed to export SMU metrics table!\n"); 1687 + mutex_unlock(&smu->metrics_lock); 1686 1688 return ret; 1687 1689 } 1688 1690 smu_table->metrics_time = jiffies; 1689 1691 } 1690 1692 1691 1693 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t)); 1694 + mutex_unlock(&smu->metrics_lock); 1692 1695 1693 1696 return ret; 1694 1697 }

+1 -1

drivers/gpu/drm/arm/malidp_mw.c

··· 56 56 return MODE_OK; 57 57 } 58 58 59 - const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = { 59 + static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = { 60 60 .get_modes = malidp_mw_connector_get_modes, 61 61 .mode_valid = malidp_mw_connector_mode_valid, 62 62 };

+12 -6

drivers/gpu/drm/mediatek/mtk_drm_crtc.c

··· 215 215 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 216 216 struct mtk_ddp_comp *comp; 217 217 int i, count = 0; 218 + unsigned int local_index = plane - mtk_crtc->planes; 218 219 219 220 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 220 221 comp = mtk_crtc->ddp_comp[i]; 221 - if (plane->index < (count + mtk_ddp_comp_layer_nr(comp))) { 222 - *local_layer = plane->index - count; 222 + if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 223 + *local_layer = local_index - count; 223 224 return comp; 224 225 } 225 226 count += mtk_ddp_comp_layer_nr(comp); ··· 311 310 312 311 plane_state = to_mtk_plane_state(plane->state); 313 312 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 314 - mtk_ddp_comp_layer_config(comp, local_layer, plane_state); 313 + if (comp) 314 + mtk_ddp_comp_layer_config(comp, local_layer, 315 + plane_state); 315 316 } 316 317 317 318 return 0; ··· 389 386 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 390 387 &local_layer); 391 388 392 - mtk_ddp_comp_layer_config(comp, local_layer, 393 - plane_state); 389 + if (comp) 390 + mtk_ddp_comp_layer_config(comp, local_layer, 391 + plane_state); 394 392 plane_state->pending.config = false; 395 393 } 396 394 mtk_crtc->pending_planes = false; ··· 405 401 struct mtk_ddp_comp *comp; 406 402 407 403 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 408 - return mtk_ddp_comp_layer_check(comp, local_layer, state); 404 + if (comp) 405 + return mtk_ddp_comp_layer_check(comp, local_layer, state); 406 + return 0; 409 407 } 410 408 411 409 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,

+38 -29

drivers/gpu/drm/mediatek/mtk_dsi.c

··· 230 230 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 231 231 { 232 232 u32 timcon0, timcon1, timcon2, timcon3; 233 - u32 ui, cycle_time; 233 + u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); 234 234 struct mtk_phy_timing *timing = &dsi->phy_timing; 235 235 236 - ui = DIV_ROUND_UP(1000000000, dsi->data_rate); 237 - cycle_time = div_u64(8000000000ULL, dsi->data_rate); 236 + timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; 237 + timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; 238 + timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - 239 + timing->da_hs_prepare; 240 + timing->da_hs_trail = timing->da_hs_prepare + 1; 238 241 239 - timing->lpx = NS_TO_CYCLE(60, cycle_time); 240 - timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time); 241 - timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time); 242 - timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time); 242 + timing->ta_go = 4 * timing->lpx - 2; 243 + timing->ta_sure = timing->lpx + 2; 244 + timing->ta_get = 4 * timing->lpx; 245 + timing->da_hs_exit = 2 * timing->lpx + 1; 243 246 244 - timing->ta_go = 4 * timing->lpx; 245 - timing->ta_sure = 3 * timing->lpx / 2; 246 - timing->ta_get = 5 * timing->lpx; 247 - timing->da_hs_exit = 2 * timing->lpx; 248 - 249 - timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time); 250 - timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10; 251 - 252 - timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time); 253 - timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time); 254 - timing->clk_hs_exit = 2 * timing->lpx; 247 + timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); 248 + timing->clk_hs_post = timing->clk_hs_prepare + 8; 249 + timing->clk_hs_trail = timing->clk_hs_prepare; 250 + timing->clk_hs_zero = timing->clk_hs_trail * 4; 251 + timing->clk_hs_exit = 2 * timing->clk_hs_trail; 255 252 256 253 timcon0 = timing->lpx | timing->da_hs_prepare << 8 | 257 254 timing->da_hs_zero << 16 | timing->da_hs_trail << 24; ··· 479 482 dsi_tmp_buf_bpp - 10); 480 483 481 484 data_phy_cycles = timing->lpx + timing->da_hs_prepare + 482 - timing->da_hs_zero + timing->da_hs_exit + 2; 485 + timing->da_hs_zero + timing->da_hs_exit + 3; 483 486 484 487 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 485 - if (vm->hfront_porch * dsi_tmp_buf_bpp > 488 + if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp > 486 489 data_phy_cycles * dsi->lanes + 18) { 487 - horizontal_frontporch_byte = vm->hfront_porch * 488 - dsi_tmp_buf_bpp - 489 - data_phy_cycles * 490 - dsi->lanes - 18; 490 + horizontal_frontporch_byte = 491 + vm->hfront_porch * dsi_tmp_buf_bpp - 492 + (data_phy_cycles * dsi->lanes + 18) * 493 + vm->hfront_porch / 494 + (vm->hfront_porch + vm->hback_porch); 495 + 496 + horizontal_backporch_byte = 497 + horizontal_backporch_byte - 498 + (data_phy_cycles * dsi->lanes + 18) * 499 + vm->hback_porch / 500 + (vm->hfront_porch + vm->hback_porch); 491 501 } else { 492 502 DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n"); 493 503 horizontal_frontporch_byte = vm->hfront_porch * 494 504 dsi_tmp_buf_bpp; 495 505 } 496 506 } else { 497 - if (vm->hfront_porch * dsi_tmp_buf_bpp > 507 + if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp > 498 508 data_phy_cycles * dsi->lanes + 12) { 499 - horizontal_frontporch_byte = vm->hfront_porch * 500 - dsi_tmp_buf_bpp - 501 - data_phy_cycles * 502 - dsi->lanes - 12; 509 + horizontal_frontporch_byte = 510 + vm->hfront_porch * dsi_tmp_buf_bpp - 511 + (data_phy_cycles * dsi->lanes + 12) * 512 + vm->hfront_porch / 513 + (vm->hfront_porch + vm->hback_porch); 514 + horizontal_backporch_byte = horizontal_backporch_byte - 515 + (data_phy_cycles * dsi->lanes + 12) * 516 + vm->hback_porch / 517 + (vm->hfront_porch + vm->hback_porch); 503 518 } else { 504 519 DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n"); 505 520 horizontal_frontporch_byte = vm->hfront_porch *

-2

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

··· 685 685 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 686 686 687 687 cec_unregister_adapter(hdmi->cec_adap); 688 - drm_connector_cleanup(&hdmi->connector); 689 - drm_encoder_cleanup(&hdmi->encoder); 690 688 i2c_del_adapter(hdmi->i2c); 691 689 i2c_put_adapter(hdmi->ddc_i2c); 692 690 clk_disable_unprepare(hdmi->mod_clk);

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