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drm/msm/dpu: Allow configuring multiple active DSC blocks

Just like the active interface and writeback block in ctl_intf_cfg_v1(),
and later the rest of the blocks in followup active-CTL fixes or
reworks, multiple calls to this function should enable additional DSC
blocks instead of overwriting the blocks that are enabled.

This pattern is observed in an active-CTL scenario since DPU 5.0.0 where
for example bonded-DSI uses a single CTL to drive multiple INTFs, and
each encoder calls this function individually with the INTF (hence the
pre-existing update instead of overwrite of this bitmask) and DSC blocks
it wishes to be enabled, and expects them to be OR'd into the bitmask.

The reverse already exists in reset_intf_cfg_v1() where only specified
DSC blocks are removed out of the CTL_DSC_ACTIVE bitmask (same for all
other blocks and ACTIVE bitmasks), leaving the rest enabled.

Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/589902/
Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-4-78ae3ee9a697@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Marijn Suijten and committed by
Dmitry Baryshkov ca97fa41 2b938c3a

+6 -3
+6 -3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
··· 545 545 { 546 546 struct dpu_hw_blk_reg_map *c = &ctx->hw; 547 547 u32 intf_active = 0; 548 + u32 dsc_active = 0; 548 549 u32 wb_active = 0; 549 550 u32 mode_sel = 0; 550 551 ··· 561 560 562 561 intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); 563 562 wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); 563 + dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); 564 564 565 565 if (cfg->intf) 566 566 intf_active |= BIT(cfg->intf - INTF_0); ··· 569 567 if (cfg->wb) 570 568 wb_active |= BIT(cfg->wb - WB_0); 571 569 570 + if (cfg->dsc) 571 + dsc_active |= cfg->dsc; 572 + 572 573 DPU_REG_WRITE(c, CTL_TOP, mode_sel); 573 574 DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); 574 575 DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); 576 + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); 575 577 576 578 if (cfg->merge_3d) 577 579 DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, 578 580 BIT(cfg->merge_3d - MERGE_3D_0)); 579 - 580 - if (cfg->dsc) 581 - DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); 582 581 583 582 if (cfg->cdm) 584 583 DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);