Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+1 -1

drivers/gpu/drm/i915/intel_bios.c

··· 1123 1123 } 1124 1124 } 1125 1125 1126 - static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id) 1126 + static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) 1127 1127 { 1128 1128 DRM_DEBUG_KMS("Falling back to manually reading VBT from " 1129 1129 "VBIOS ROM for %s\n",

+1 -1

drivers/gpu/drm/i915/intel_crt.c

··· 804 804 .destroy = intel_encoder_destroy, 805 805 }; 806 806 807 - static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) 807 + static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 808 808 { 809 809 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 810 810 return 1;

+30 -4

drivers/gpu/drm/i915/intel_display.c

··· 2233 2233 if (need_vtd_wa(dev) && alignment < 256 * 1024) 2234 2234 alignment = 256 * 1024; 2235 2235 2236 + /* 2237 + * Global gtt pte registers are special registers which actually forward 2238 + * writes to a chunk of system memory. Which means that there is no risk 2239 + * that the register values disappear as soon as we call 2240 + * intel_runtime_pm_put(), so it is correct to wrap only the 2241 + * pin/unpin/fence and not more. 2242 + */ 2243 + intel_runtime_pm_get(dev_priv); 2244 + 2236 2245 dev_priv->mm.interruptible = false; 2237 2246 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 2238 2247 if (ret) ··· 2259 2250 i915_gem_object_pin_fence(obj); 2260 2251 2261 2252 dev_priv->mm.interruptible = true; 2253 + intel_runtime_pm_put(dev_priv); 2262 2254 return 0; 2263 2255 2264 2256 err_unpin: 2265 2257 i915_gem_object_unpin_from_display_plane(obj); 2266 2258 err_interruptible: 2267 2259 dev_priv->mm.interruptible = true; 2260 + intel_runtime_pm_put(dev_priv); 2268 2261 return ret; 2269 2262 } 2270 2263 ··· 4199 4188 intel_set_pch_fifo_underrun_reporting(dev, pipe, false); 4200 4189 4201 4190 intel_disable_pipe(dev_priv, pipe); 4202 - 4203 - if (intel_crtc->config.dp_encoder_is_mst) 4204 - intel_ddi_set_vc_payload_alloc(crtc, false); 4205 - 4206 4191 ironlake_pfit_disable(intel_crtc); 4207 4192 4208 4193 for_each_encoder_on_crtc(dev, crtc, encoder) ··· 4262 4255 if (intel_crtc->config.has_pch_encoder) 4263 4256 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); 4264 4257 intel_disable_pipe(dev_priv, pipe); 4258 + 4259 + if (intel_crtc->config.dp_encoder_is_mst) 4260 + intel_ddi_set_vc_payload_alloc(crtc, false); 4265 4261 4266 4262 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 4267 4263 ··· 8250 8240 goto fail_locked; 8251 8241 } 8252 8242 8243 + /* 8244 + * Global gtt pte registers are special registers which actually 8245 + * forward writes to a chunk of system memory. Which means that 8246 + * there is no risk that the register values disappear as soon 8247 + * as we call intel_runtime_pm_put(), so it is correct to wrap 8248 + * only the pin/unpin/fence and not more. 8249 + */ 8250 + intel_runtime_pm_get(dev_priv); 8251 + 8253 8252 /* Note that the w/a also requires 2 PTE of padding following 8254 8253 * the bo. We currently fill all unused PTE with the shadow 8255 8254 * page and so we should always have valid PTE following the ··· 8271 8252 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); 8272 8253 if (ret) { 8273 8254 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); 8255 + intel_runtime_pm_put(dev_priv); 8274 8256 goto fail_locked; 8275 8257 } 8276 8258 8277 8259 ret = i915_gem_object_put_fence(obj); 8278 8260 if (ret) { 8279 8261 DRM_DEBUG_KMS("failed to release fence for cursor"); 8262 + intel_runtime_pm_put(dev_priv); 8280 8263 goto fail_unpin; 8281 8264 } 8282 8265 8283 8266 addr = i915_gem_obj_ggtt_offset(obj); 8267 + 8268 + intel_runtime_pm_put(dev_priv); 8284 8269 } else { 8285 8270 int align = IS_I830(dev) ? 16 * 1024 : 256; 8286 8271 ret = i915_gem_object_attach_phys(obj, align); ··· 12503 12480 12504 12481 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ 12505 12482 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, 12483 + 12484 + /* Acer C720 Chromebook (Core i3 4005U) */ 12485 + { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, 12506 12486 12507 12487 /* Toshiba CB35 Chromebook (Celeron 2955U) */ 12508 12488 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },

+37 -18

drivers/gpu/drm/i915/intel_dp.c

··· 3661 3661 return intel_dp_detect_dpcd(intel_dp); 3662 3662 } 3663 3663 3664 - static enum drm_connector_status 3665 - g4x_dp_detect(struct intel_dp *intel_dp) 3664 + static int g4x_digital_port_connected(struct drm_device *dev, 3665 + struct intel_digital_port *intel_dig_port) 3666 3666 { 3667 - struct drm_device *dev = intel_dp_to_dev(intel_dp); 3668 3667 struct drm_i915_private *dev_priv = dev->dev_private; 3669 - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3670 3668 uint32_t bit; 3671 - 3672 - /* Can't disconnect eDP, but you can close the lid... */ 3673 - if (is_edp(intel_dp)) { 3674 - enum drm_connector_status status; 3675 - 3676 - status = intel_panel_detect(dev); 3677 - if (status == connector_status_unknown) 3678 - status = connector_status_connected; 3679 - return status; 3680 - } 3681 3669 3682 3670 if (IS_VALLEYVIEW(dev)) { 3683 3671 switch (intel_dig_port->port) { ··· 3679 3691 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3680 3692 break; 3681 3693 default: 3682 - return connector_status_unknown; 3694 + return -EINVAL; 3683 3695 } 3684 3696 } else { 3685 3697 switch (intel_dig_port->port) { ··· 3693 3705 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3694 3706 break; 3695 3707 default: 3696 - return connector_status_unknown; 3708 + return -EINVAL; 3697 3709 } 3698 3710 } 3699 3711 3700 3712 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3713 + return 0; 3714 + return 1; 3715 + } 3716 + 3717 + static enum drm_connector_status 3718 + g4x_dp_detect(struct intel_dp *intel_dp) 3719 + { 3720 + struct drm_device *dev = intel_dp_to_dev(intel_dp); 3721 + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3722 + int ret; 3723 + 3724 + /* Can't disconnect eDP, but you can close the lid... */ 3725 + if (is_edp(intel_dp)) { 3726 + enum drm_connector_status status; 3727 + 3728 + status = intel_panel_detect(dev); 3729 + if (status == connector_status_unknown) 3730 + status = connector_status_connected; 3731 + return status; 3732 + } 3733 + 3734 + ret = g4x_digital_port_connected(dev, intel_dig_port); 3735 + if (ret == -EINVAL) 3736 + return connector_status_unknown; 3737 + else if (ret == 0) 3701 3738 return connector_status_disconnected; 3702 3739 3703 3740 return intel_dp_detect_dpcd(intel_dp); ··· 4079 4066 intel_display_power_get(dev_priv, power_domain); 4080 4067 4081 4068 if (long_hpd) { 4082 - if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 4083 - goto mst_fail; 4069 + 4070 + if (HAS_PCH_SPLIT(dev)) { 4071 + if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 4072 + goto mst_fail; 4073 + } else { 4074 + if (g4x_digital_port_connected(dev, intel_dig_port) != 1) 4075 + goto mst_fail; 4076 + } 4084 4077 4085 4078 if (!intel_dp_get_dpcd(intel_dp)) { 4086 4079 goto mst_fail;

+1 -1

drivers/gpu/drm/i915/intel_lvds.c

··· 538 538 .destroy = intel_encoder_destroy, 539 539 }; 540 540 541 - static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 541 + static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 542 542 { 543 543 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 544 544 return 1;

+4 -4

drivers/gpu/drm/i915/intel_panel.c

··· 801 801 802 802 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); 803 803 if (cpu_ctl2 & BLM_PWM_ENABLE) { 804 - WARN(1, "cpu backlight already enabled\n"); 804 + DRM_DEBUG_KMS("cpu backlight already enabled\n"); 805 805 cpu_ctl2 &= ~BLM_PWM_ENABLE; 806 806 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); 807 807 } ··· 845 845 846 846 ctl = I915_READ(BLC_PWM_CTL); 847 847 if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { 848 - WARN(1, "backlight already enabled\n"); 848 + DRM_DEBUG_KMS("backlight already enabled\n"); 849 849 I915_WRITE(BLC_PWM_CTL, 0); 850 850 } 851 851 ··· 876 876 877 877 ctl2 = I915_READ(BLC_PWM_CTL2); 878 878 if (ctl2 & BLM_PWM_ENABLE) { 879 - WARN(1, "backlight already enabled\n"); 879 + DRM_DEBUG_KMS("backlight already enabled\n"); 880 880 ctl2 &= ~BLM_PWM_ENABLE; 881 881 I915_WRITE(BLC_PWM_CTL2, ctl2); 882 882 } ··· 910 910 911 911 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); 912 912 if (ctl2 & BLM_PWM_ENABLE) { 913 - WARN(1, "backlight already enabled\n"); 913 + DRM_DEBUG_KMS("backlight already enabled\n"); 914 914 ctl2 &= ~BLM_PWM_ENABLE; 915 915 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); 916 916 }

+7 -3

drivers/gpu/drm/i915/intel_tv.c

··· 1311 1311 { 1312 1312 struct drm_display_mode mode; 1313 1313 struct intel_tv *intel_tv = intel_attached_tv(connector); 1314 + enum drm_connector_status status; 1314 1315 int type; 1315 1316 1316 1317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", ··· 1329 1328 if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) { 1330 1329 type = intel_tv_detect_type(intel_tv, connector); 1331 1330 intel_release_load_detect_pipe(connector, &tmp); 1331 + status = type < 0 ? 1332 + connector_status_disconnected : 1333 + connector_status_connected; 1332 1334 } else 1333 - return connector_status_unknown; 1335 + status = connector_status_unknown; 1334 1336 1335 1337 drm_modeset_drop_locks(&ctx); 1336 1338 drm_modeset_acquire_fini(&ctx); 1337 1339 } else 1338 1340 return connector->status; 1339 1341 1340 - if (type < 0) 1341 - return connector_status_disconnected; 1342 + if (status != connector_status_connected) 1343 + return status; 1342 1344 1343 1345 intel_tv->type = type; 1344 1346 intel_tv_find_better_format(connector);

+2 -2

drivers/gpu/drm/nouveau/core/core/parent.c

··· 86 86 sclass = nv_parent(parent)->sclass; 87 87 while (sclass) { 88 88 if (++nr < size) 89 - lclass[nr] = sclass->oclass->handle; 89 + lclass[nr] = sclass->oclass->handle & 0xffff; 90 90 sclass = sclass->sclass; 91 91 } 92 92 ··· 96 96 if (engine && (oclass = engine->sclass)) { 97 97 while (oclass->ofuncs) { 98 98 if (++nr < size) 99 - lclass[nr] = oclass->handle; 99 + lclass[nr] = oclass->handle & 0xffff; 100 100 oclass++; 101 101 } 102 102 }

+5 -6

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

··· 450 450 res, 451 451 id_loc - sw_context->buf_start); 452 452 if (unlikely(ret != 0)) 453 - goto out_err; 453 + return ret; 454 454 455 455 ret = vmw_resource_val_add(sw_context, res, &node); 456 456 if (unlikely(ret != 0)) 457 - goto out_err; 457 + return ret; 458 458 459 459 if (res_type == vmw_res_context && dev_priv->has_mob && 460 460 node->first_usage) { ··· 468 468 469 469 ret = vmw_resource_context_res_add(dev_priv, sw_context, res); 470 470 if (unlikely(ret != 0)) 471 - goto out_err; 471 + return ret; 472 472 node->staged_bindings = 473 473 kzalloc(sizeof(*node->staged_bindings), GFP_KERNEL); 474 474 if (node->staged_bindings == NULL) { 475 475 DRM_ERROR("Failed to allocate context binding " 476 476 "information.\n"); 477 - goto out_err; 477 + return -ENOMEM; 478 478 } 479 479 INIT_LIST_HEAD(&node->staged_bindings->list); 480 480 } ··· 482 482 if (p_val) 483 483 *p_val = node; 484 484 485 - out_err: 486 - return ret; 485 + return 0; 487 486 } 488 487 489 488

+2 -1

drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

··· 180 180 181 181 mutex_lock(&dev_priv->hw_mutex); 182 182 183 + vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 183 184 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) 184 - vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 185 + ; 185 186 186 187 dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); 187 188

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