Merge branches 'ib-mfd-misc-pinctrl-regulator-6.10', 'ib-mfd-pinctrl-regulator-6.10' and 'ib-mfd-regulator-6.10' into ibs-for-mfd-merged

+274

Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/rockchip,rk816.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: RK816 Power Management Integrated Circuit 8 + 9 + maintainers: 10 + - Chris Zhong <zyw@rock-chips.com> 11 + - Zhang Qing <zhangqing@rock-chips.com> 12 + 13 + description: 14 + Rockchip RK816 series PMIC. This device consists of an i2c controlled MFD 15 + that includes regulators, a RTC, a GPIO controller, a power button, and a 16 + battery charger manager with fuel gauge. 17 + 18 + properties: 19 + compatible: 20 + enum: 21 + - rockchip,rk816 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupts: 27 + maxItems: 1 28 + 29 + '#clock-cells': 30 + description: 31 + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. 32 + const: 1 33 + 34 + clock-output-names: 35 + maxItems: 2 36 + 37 + gpio-controller: true 38 + 39 + '#gpio-cells': 40 + const: 2 41 + 42 + system-power-controller: 43 + type: boolean 44 + description: 45 + Telling whether or not this PMIC is controlling the system power. 46 + 47 + wakeup-source: 48 + type: boolean 49 + 50 + vcc1-supply: 51 + description: 52 + The input supply for dcdc1. 53 + 54 + vcc2-supply: 55 + description: 56 + The input supply for dcdc2. 57 + 58 + vcc3-supply: 59 + description: 60 + The input supply for dcdc3. 61 + 62 + vcc4-supply: 63 + description: 64 + The input supply for dcdc4. 65 + 66 + vcc5-supply: 67 + description: 68 + The input supply for ldo1, ldo2, and ldo3. 69 + 70 + vcc6-supply: 71 + description: 72 + The input supply for ldo4, ldo5, and ldo6. 73 + 74 + vcc7-supply: 75 + description: 76 + The input supply for boost. 77 + 78 + vcc8-supply: 79 + description: 80 + The input supply for otg-switch. 81 + 82 + regulators: 83 + type: object 84 + patternProperties: 85 + '^(boost|dcdc[1-4]|ldo[1-6]|otg-switch)$': 86 + type: object 87 + $ref: /schemas/regulator/regulator.yaml# 88 + unevaluatedProperties: false 89 + additionalProperties: false 90 + 91 + patternProperties: 92 + '-pins$': 93 + type: object 94 + additionalProperties: false 95 + $ref: /schemas/pinctrl/pinmux-node.yaml 96 + 97 + properties: 98 + function: 99 + enum: [gpio, thermistor] 100 + 101 + pins: 102 + $ref: /schemas/types.yaml#/definitions/string 103 + const: gpio0 104 + 105 + required: 106 + - compatible 107 + - reg 108 + - interrupts 109 + - '#clock-cells' 110 + 111 + additionalProperties: false 112 + 113 + examples: 114 + - | 115 + #include <dt-bindings/pinctrl/rockchip.h> 116 + #include <dt-bindings/interrupt-controller/irq.h> 117 + #include <dt-bindings/gpio/gpio.h> 118 + 119 + i2c { 120 + #address-cells = <1>; 121 + #size-cells = <0>; 122 + 123 + rk816: pmic@1a { 124 + compatible = "rockchip,rk816"; 125 + reg = <0x1a>; 126 + interrupt-parent = <&gpio0>; 127 + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; 128 + clock-output-names = "xin32k", "rk816-clkout2"; 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pmic_int_l>; 131 + gpio-controller; 132 + system-power-controller; 133 + wakeup-source; 134 + #clock-cells = <1>; 135 + #gpio-cells = <2>; 136 + 137 + vcc1-supply = <&vcc_sys>; 138 + vcc2-supply = <&vcc_sys>; 139 + vcc3-supply = <&vcc_sys>; 140 + vcc4-supply = <&vcc_sys>; 141 + vcc5-supply = <&vcc33_io>; 142 + vcc6-supply = <&vcc_sys>; 143 + 144 + regulators { 145 + vdd_cpu: dcdc1 { 146 + regulator-name = "vdd_cpu"; 147 + regulator-min-microvolt = <750000>; 148 + regulator-max-microvolt = <1450000>; 149 + regulator-ramp-delay = <6001>; 150 + regulator-initial-mode = <1>; 151 + regulator-always-on; 152 + regulator-boot-on; 153 + 154 + regulator-state-mem { 155 + regulator-off-in-suspend; 156 + }; 157 + }; 158 + 159 + vdd_logic: dcdc2 { 160 + regulator-name = "vdd_logic"; 161 + regulator-min-microvolt = <800000>; 162 + regulator-max-microvolt = <1250000>; 163 + regulator-ramp-delay = <6001>; 164 + regulator-initial-mode = <1>; 165 + regulator-always-on; 166 + regulator-boot-on; 167 + 168 + regulator-state-mem { 169 + regulator-on-in-suspend; 170 + regulator-suspend-microvolt = <1000000>; 171 + }; 172 + }; 173 + 174 + vcc_ddr: dcdc3 { 175 + regulator-name = "vcc_ddr"; 176 + regulator-initial-mode = <1>; 177 + regulator-always-on; 178 + regulator-boot-on; 179 + 180 + regulator-state-mem { 181 + regulator-on-in-suspend; 182 + }; 183 + }; 184 + 185 + vcc33_io: dcdc4 { 186 + regulator-min-microvolt = <3300000>; 187 + regulator-max-microvolt = <3300000>; 188 + regulator-name = "vcc33_io"; 189 + regulator-initial-mode = <1>; 190 + regulator-always-on; 191 + regulator-boot-on; 192 + 193 + regulator-state-mem { 194 + regulator-on-in-suspend; 195 + regulator-suspend-microvolt = <3300000>; 196 + }; 197 + }; 198 + 199 + vccio_pmu: ldo1 { 200 + regulator-min-microvolt = <3300000>; 201 + regulator-max-microvolt = <3300000>; 202 + regulator-name = "vccio_pmu"; 203 + regulator-always-on; 204 + regulator-boot-on; 205 + 206 + regulator-state-mem { 207 + regulator-on-in-suspend; 208 + regulator-suspend-microvolt = <3300000>; 209 + }; 210 + }; 211 + 212 + vcc_tp: ldo2 { 213 + regulator-min-microvolt = <3300000>; 214 + regulator-max-microvolt = <3300000>; 215 + regulator-name = "vcc_tp"; 216 + 217 + regulator-state-mem { 218 + regulator-off-in-suspend; 219 + }; 220 + }; 221 + 222 + vdd_10: ldo3 { 223 + regulator-min-microvolt = <1000000>; 224 + regulator-max-microvolt = <1000000>; 225 + regulator-name = "vdd_10"; 226 + regulator-always-on; 227 + regulator-boot-on; 228 + 229 + regulator-state-mem { 230 + regulator-on-in-suspend; 231 + regulator-suspend-microvolt = <1000000>; 232 + }; 233 + }; 234 + 235 + vcc18_lcd: ldo4 { 236 + regulator-min-microvolt = <1800000>; 237 + regulator-max-microvolt = <1800000>; 238 + regulator-name = "vcc18_lcd"; 239 + 240 + regulator-state-mem { 241 + regulator-on-in-suspend; 242 + regulator-suspend-microvolt = <1800000>; 243 + }; 244 + }; 245 + 246 + vccio_sd: ldo5 { 247 + regulator-min-microvolt = <1800000>; 248 + regulator-max-microvolt = <3300000>; 249 + regulator-name = "vccio_sd"; 250 + 251 + regulator-state-mem { 252 + regulator-on-in-suspend; 253 + regulator-suspend-microvolt = <3300000>; 254 + }; 255 + }; 256 + 257 + vdd10_lcd: ldo6 { 258 + regulator-min-microvolt = <1000000>; 259 + regulator-max-microvolt = <1000000>; 260 + regulator-name = "vdd10_lcd"; 261 + 262 + regulator-state-mem { 263 + regulator-on-in-suspend; 264 + regulator-suspend-microvolt = <1000000>; 265 + }; 266 + }; 267 + }; 268 + 269 + rk816_gpio_pins: gpio-pins { 270 + function = "gpio"; 271 + pins = "gpio0"; 272 + }; 273 + }; 274 + };

+2

Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml

··· 83 83 enum: 84 84 - x-powers,axp313a 85 85 - x-powers,axp15060 86 + - x-powers,axp717 86 87 87 88 then: 88 89 properties: ··· 100 99 - x-powers,axp221 101 100 - x-powers,axp223 102 101 - x-powers,axp313a 102 + - x-powers,axp717 103 103 - x-powers,axp803 104 104 - x-powers,axp806 105 105 - x-powers,axp809

+2 -2

drivers/mfd/Kconfig

··· 1225 1225 select MFD_CORE 1226 1226 1227 1227 config MFD_RK8XX_I2C 1228 - tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power Management Chip" 1228 + tristate "Rockchip RK805/RK808/RK809/RK816/RK817/RK818 Power Management Chip" 1229 1229 depends on I2C && OF 1230 1230 select MFD_CORE 1231 1231 select REGMAP_I2C ··· 1233 1233 select MFD_RK8XX 1234 1234 help 1235 1235 If you say yes here you get support for the RK805, RK808, RK809, 1236 - RK817 and RK818 Power Management chips. 1236 + RK816, RK817 and RK818 Power Management chips. 1237 1237 This driver provides common support for accessing the device 1238 1238 through I2C interface. The device supports multiple sub-devices 1239 1239 including interrupts, RTC, LDO & DCDC regulators, and onkey.

+2

drivers/mfd/axp20x-i2c.c

··· 65 65 { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID }, 66 66 { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID }, 67 67 { .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID }, 68 + { .compatible = "x-powers,axp717", .data = (void *)AXP717_ID }, 68 69 { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID }, 69 70 { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID }, 70 71 { .compatible = "x-powers,axp15060", .data = (void *)AXP15060_ID }, ··· 82 81 { "axp221", 0 }, 83 82 { "axp223", 0 }, 84 83 { "axp313a", 0 }, 84 + { "axp717", 0 }, 85 85 { "axp803", 0 }, 86 86 { "axp806", 0 }, 87 87 { "axp15060", 0 },

+1

drivers/mfd/axp20x-rsb.c

··· 58 58 59 59 static const struct of_device_id axp20x_rsb_of_match[] = { 60 60 { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID }, 61 + { .compatible = "x-powers,axp717", .data = (void *)AXP717_ID }, 61 62 { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID }, 62 63 { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID }, 63 64 { .compatible = "x-powers,axp809", .data = (void *)AXP809_ID },

+90

drivers/mfd/axp20x.c

··· 42 42 "AXP223", 43 43 "AXP288", 44 44 "AXP313a", 45 + "AXP717", 45 46 "AXP803", 46 47 "AXP806", 47 48 "AXP809", ··· 208 207 .n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges), 209 208 }; 210 209 210 + static const struct regmap_range axp717_writeable_ranges[] = { 211 + regmap_reg_range(AXP717_IRQ0_EN, AXP717_IRQ4_EN), 212 + regmap_reg_range(AXP717_DCDC_OUTPUT_CONTROL, AXP717_CPUSLDO_CONTROL), 213 + }; 214 + 215 + static const struct regmap_range axp717_volatile_ranges[] = { 216 + regmap_reg_range(AXP717_IRQ0_STATE, AXP717_IRQ4_STATE), 217 + }; 218 + 219 + static const struct regmap_access_table axp717_writeable_table = { 220 + .yes_ranges = axp717_writeable_ranges, 221 + .n_yes_ranges = ARRAY_SIZE(axp717_writeable_ranges), 222 + }; 223 + 224 + static const struct regmap_access_table axp717_volatile_table = { 225 + .yes_ranges = axp717_volatile_ranges, 226 + .n_yes_ranges = ARRAY_SIZE(axp717_volatile_ranges), 227 + }; 228 + 211 229 static const struct regmap_range axp806_volatile_ranges[] = { 212 230 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE), 213 231 }; ··· 337 317 DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_FAL_EDGE, "PEK_DBF"), 338 318 }; 339 319 320 + static const struct resource axp717_pek_resources[] = { 321 + DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_RIS_EDGE, "PEK_DBR"), 322 + DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_FAL_EDGE, "PEK_DBF"), 323 + }; 324 + 340 325 static const struct resource axp803_pek_resources[] = { 341 326 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"), 342 327 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"), ··· 414 389 .volatile_table = &axp313a_volatile_table, 415 390 .max_register = AXP313A_IRQ_STATE, 416 391 .cache_type = REGCACHE_MAPLE, 392 + }; 393 + 394 + static const struct regmap_config axp717_regmap_config = { 395 + .reg_bits = 8, 396 + .val_bits = 8, 397 + .wr_table = &axp717_writeable_table, 398 + .volatile_table = &axp717_volatile_table, 399 + .max_register = AXP717_CPUSLDO_CONTROL, 400 + .cache_type = REGCACHE_RBTREE, 417 401 }; 418 402 419 403 static const struct regmap_config axp806_regmap_config = { ··· 623 589 INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0), 624 590 }; 625 591 592 + static const struct regmap_irq axp717_regmap_irqs[] = { 593 + INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL2, 0, 7), 594 + INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL1, 0, 6), 595 + INIT_REGMAP_IRQ(AXP717, GAUGE_NEW_SOC, 0, 4), 596 + INIT_REGMAP_IRQ(AXP717, BOOST_OVER_V, 0, 2), 597 + INIT_REGMAP_IRQ(AXP717, VBUS_OVER_V, 0, 1), 598 + INIT_REGMAP_IRQ(AXP717, VBUS_FAULT, 0, 0), 599 + INIT_REGMAP_IRQ(AXP717, VBUS_PLUGIN, 1, 7), 600 + INIT_REGMAP_IRQ(AXP717, VBUS_REMOVAL, 1, 6), 601 + INIT_REGMAP_IRQ(AXP717, BATT_PLUGIN, 1, 5), 602 + INIT_REGMAP_IRQ(AXP717, BATT_REMOVAL, 1, 4), 603 + INIT_REGMAP_IRQ(AXP717, PEK_SHORT, 1, 3), 604 + INIT_REGMAP_IRQ(AXP717, PEK_LONG, 1, 2), 605 + INIT_REGMAP_IRQ(AXP717, PEK_FAL_EDGE, 1, 1), 606 + INIT_REGMAP_IRQ(AXP717, PEK_RIS_EDGE, 1, 0), 607 + INIT_REGMAP_IRQ(AXP717, WDOG_EXPIRE, 2, 7), 608 + INIT_REGMAP_IRQ(AXP717, LDO_OVER_CURR, 2, 6), 609 + INIT_REGMAP_IRQ(AXP717, BATT_OVER_CURR, 2, 5), 610 + INIT_REGMAP_IRQ(AXP717, CHARG_DONE, 2, 4), 611 + INIT_REGMAP_IRQ(AXP717, CHARG, 2, 3), 612 + INIT_REGMAP_IRQ(AXP717, DIE_TEMP_HIGH, 2, 2), 613 + INIT_REGMAP_IRQ(AXP717, CHARG_TIMER, 2, 1), 614 + INIT_REGMAP_IRQ(AXP717, BATT_OVER_V, 2, 0), 615 + INIT_REGMAP_IRQ(AXP717, BC_USB_DONE, 3, 7), 616 + INIT_REGMAP_IRQ(AXP717, BC_USB_CHNG, 3, 6), 617 + INIT_REGMAP_IRQ(AXP717, BATT_QUIT_TEMP_HIGH, 3, 4), 618 + INIT_REGMAP_IRQ(AXP717, BATT_CHG_TEMP_HIGH, 3, 3), 619 + INIT_REGMAP_IRQ(AXP717, BATT_CHG_TEMP_LOW, 3, 2), 620 + INIT_REGMAP_IRQ(AXP717, BATT_ACT_TEMP_HIGH, 3, 1), 621 + INIT_REGMAP_IRQ(AXP717, BATT_ACT_TEMP_LOW, 3, 0), 622 + INIT_REGMAP_IRQ(AXP717, TYPEC_REMOVE, 4, 6), 623 + INIT_REGMAP_IRQ(AXP717, TYPEC_PLUGIN, 4, 5), 624 + }; 625 + 626 626 static const struct regmap_irq axp803_regmap_irqs[] = { 627 627 INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7), 628 628 INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6), ··· 844 776 .num_regs = 1, 845 777 }; 846 778 779 + static const struct regmap_irq_chip axp717_regmap_irq_chip = { 780 + .name = "axp717_irq_chip", 781 + .status_base = AXP717_IRQ0_STATE, 782 + .ack_base = AXP717_IRQ0_STATE, 783 + .unmask_base = AXP717_IRQ0_EN, 784 + .init_ack_masked = true, 785 + .irqs = axp717_regmap_irqs, 786 + .num_irqs = ARRAY_SIZE(axp717_regmap_irqs), 787 + .num_regs = 5, 788 + }; 789 + 847 790 static const struct regmap_irq_chip axp803_regmap_irq_chip = { 848 791 .name = "axp803", 849 792 .status_base = AXP20X_IRQ1_STATE, ··· 1018 939 static struct mfd_cell axp313a_cells[] = { 1019 940 MFD_CELL_NAME("axp20x-regulator"), 1020 941 MFD_CELL_RES("axp313a-pek", axp313a_pek_resources), 942 + }; 943 + 944 + static struct mfd_cell axp717_cells[] = { 945 + MFD_CELL_NAME("axp20x-regulator"), 946 + MFD_CELL_RES("axp20x-pek", axp717_pek_resources), 1021 947 }; 1022 948 1023 949 static const struct resource axp288_adc_resources[] = { ··· 1264 1180 axp20x->cells = axp313a_cells; 1265 1181 axp20x->regmap_cfg = &axp313a_regmap_config; 1266 1182 axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip; 1183 + break; 1184 + case AXP717_ID: 1185 + axp20x->nr_cells = ARRAY_SIZE(axp717_cells); 1186 + axp20x->cells = axp717_cells; 1187 + axp20x->regmap_cfg = &axp717_regmap_config; 1188 + axp20x->regmap_irq_chip = &axp717_regmap_irq_chip; 1267 1189 break; 1268 1190 case AXP803_ID: 1269 1191 axp20x->nr_cells = ARRAY_SIZE(axp803_cells);

+104

drivers/mfd/rk8xx-core.c

··· 28 28 DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM), 29 29 }; 30 30 31 + static const struct resource rk816_rtc_resources[] = { 32 + DEFINE_RES_IRQ(RK816_IRQ_RTC_ALARM), 33 + }; 34 + 31 35 static const struct resource rk817_rtc_resources[] = { 32 36 DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM), 33 37 }; ··· 88 84 .name = "rk808-rtc", 89 85 .num_resources = ARRAY_SIZE(rtc_resources), 90 86 .resources = rtc_resources, 87 + }, 88 + }; 89 + 90 + static const struct mfd_cell rk816s[] = { 91 + { .name = "rk805-pinctrl", }, 92 + { .name = "rk808-clkout", }, 93 + { .name = "rk808-regulator", }, 94 + { 95 + .name = "rk805-pwrkey", 96 + .num_resources = ARRAY_SIZE(rk805_key_resources), 97 + .resources = rk805_key_resources, 98 + }, 99 + { 100 + .name = "rk808-rtc", 101 + .num_resources = ARRAY_SIZE(rk816_rtc_resources), 102 + .resources = rk816_rtc_resources, 91 103 }, 92 104 }; 93 105 ··· 166 146 { RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE}, 167 147 { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | 168 148 VB_LO_SEL_3500MV }, 149 + }; 150 + 151 + static const struct rk808_reg_data rk816_pre_init_reg[] = { 152 + { RK818_BUCK1_CONFIG_REG, RK817_RAMP_RATE_MASK, 153 + RK817_RAMP_RATE_12_5MV_PER_US }, 154 + { RK818_BUCK2_CONFIG_REG, RK817_RAMP_RATE_MASK, 155 + RK817_RAMP_RATE_12_5MV_PER_US }, 156 + { RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA }, 157 + { RK808_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP105C}, 158 + { RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK, 159 + RK808_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN }, 169 160 }; 170 161 171 162 static const struct rk808_reg_data rk817_pre_init_reg[] = { ··· 381 350 }, 382 351 }; 383 352 353 + static const unsigned int rk816_irq_status_offsets[] = { 354 + RK816_IRQ_STS_OFFSET(RK816_INT_STS_REG1), 355 + RK816_IRQ_STS_OFFSET(RK816_INT_STS_REG2), 356 + RK816_IRQ_STS_OFFSET(RK816_INT_STS_REG3), 357 + }; 358 + 359 + static const unsigned int rk816_irq_mask_offsets[] = { 360 + RK816_IRQ_MSK_OFFSET(RK816_INT_STS_MSK_REG1), 361 + RK816_IRQ_MSK_OFFSET(RK816_INT_STS_MSK_REG2), 362 + RK816_IRQ_MSK_OFFSET(RK816_INT_STS_MSK_REG3), 363 + }; 364 + 365 + static unsigned int rk816_get_irq_reg(struct regmap_irq_chip_data *data, 366 + unsigned int base, int index) 367 + { 368 + unsigned int irq_reg = base; 369 + 370 + switch (base) { 371 + case RK816_INT_STS_REG1: 372 + irq_reg += rk816_irq_status_offsets[index]; 373 + break; 374 + case RK816_INT_STS_MSK_REG1: 375 + irq_reg += rk816_irq_mask_offsets[index]; 376 + break; 377 + } 378 + 379 + return irq_reg; 380 + }; 381 + 382 + static const struct regmap_irq rk816_irqs[] = { 383 + /* INT_STS_REG1 IRQs */ 384 + REGMAP_IRQ_REG(RK816_IRQ_PWRON_FALL, 0, RK816_INT_STS_PWRON_FALL), 385 + REGMAP_IRQ_REG(RK816_IRQ_PWRON_RISE, 0, RK816_INT_STS_PWRON_RISE), 386 + 387 + /* INT_STS_REG2 IRQs */ 388 + REGMAP_IRQ_REG(RK816_IRQ_VB_LOW, 1, RK816_INT_STS_VB_LOW), 389 + REGMAP_IRQ_REG(RK816_IRQ_PWRON, 1, RK816_INT_STS_PWRON), 390 + REGMAP_IRQ_REG(RK816_IRQ_PWRON_LP, 1, RK816_INT_STS_PWRON_LP), 391 + REGMAP_IRQ_REG(RK816_IRQ_HOTDIE, 1, RK816_INT_STS_HOTDIE), 392 + REGMAP_IRQ_REG(RK816_IRQ_RTC_ALARM, 1, RK816_INT_STS_RTC_ALARM), 393 + REGMAP_IRQ_REG(RK816_IRQ_RTC_PERIOD, 1, RK816_INT_STS_RTC_PERIOD), 394 + REGMAP_IRQ_REG(RK816_IRQ_USB_OV, 1, RK816_INT_STS_USB_OV), 395 + 396 + /* INT_STS3 IRQs */ 397 + REGMAP_IRQ_REG(RK816_IRQ_PLUG_IN, 2, RK816_INT_STS_PLUG_IN), 398 + REGMAP_IRQ_REG(RK816_IRQ_PLUG_OUT, 2, RK816_INT_STS_PLUG_OUT), 399 + REGMAP_IRQ_REG(RK816_IRQ_CHG_OK, 2, RK816_INT_STS_CHG_OK), 400 + REGMAP_IRQ_REG(RK816_IRQ_CHG_TE, 2, RK816_INT_STS_CHG_TE), 401 + REGMAP_IRQ_REG(RK816_IRQ_CHG_TS, 2, RK816_INT_STS_CHG_TS), 402 + REGMAP_IRQ_REG(RK816_IRQ_CHG_CVTLIM, 2, RK816_INT_STS_CHG_CVTLIM), 403 + REGMAP_IRQ_REG(RK816_IRQ_DISCHG_ILIM, 2, RK816_INT_STS_DISCHG_ILIM), 404 + }; 405 + 384 406 static const struct regmap_irq rk818_irqs[] = { 385 407 /* INT_STS */ 386 408 [RK818_IRQ_VOUT_LO] = { ··· 566 482 .init_ack_masked = true, 567 483 }; 568 484 485 + static const struct regmap_irq_chip rk816_irq_chip = { 486 + .name = "rk816", 487 + .irqs = rk816_irqs, 488 + .num_irqs = ARRAY_SIZE(rk816_irqs), 489 + .num_regs = 3, 490 + .get_irq_reg = rk816_get_irq_reg, 491 + .status_base = RK816_INT_STS_REG1, 492 + .mask_base = RK816_INT_STS_MSK_REG1, 493 + .ack_base = RK816_INT_STS_REG1, 494 + .init_ack_masked = true, 495 + }; 496 + 569 497 static struct regmap_irq_chip rk817_irq_chip = { 570 498 .name = "rk817", 571 499 .irqs = rk817_irqs, ··· 626 530 reg = RK817_SYS_CFG(3); 627 531 bit = DEV_OFF; 628 532 break; 533 + case RK816_ID: 629 534 case RK818_ID: 630 535 reg = RK818_DEVCTRL_REG; 631 536 bit = DEV_OFF; ··· 733 636 nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg); 734 637 cells = rk808s; 735 638 nr_cells = ARRAY_SIZE(rk808s); 639 + break; 640 + case RK816_ID: 641 + rk808->regmap_irq_chip = &rk816_irq_chip; 642 + pre_init_reg = rk816_pre_init_reg; 643 + nr_pre_init_regs = ARRAY_SIZE(rk816_pre_init_reg); 644 + cells = rk816s; 645 + nr_cells = ARRAY_SIZE(rk816s); 736 646 break; 737 647 case RK818_ID: 738 648 rk808->regmap_irq_chip = &rk818_irq_chip;

+44 -1

drivers/mfd/rk8xx-i2c.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Rockchip RK808/RK818 Core (I2C) driver 3 + * Rockchip RK805/RK808/RK816/RK817/RK818 Core (I2C) driver 4 4 * 5 5 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 6 6 * Copyright (C) 2016 PHYTEC Messtechnik GmbH ··· 43 43 case RK808_DEVCTRL_REG: 44 44 case RK808_INT_STS_REG1: 45 45 case RK808_INT_STS_REG2: 46 + return true; 47 + } 48 + 49 + return false; 50 + } 51 + 52 + static bool rk816_is_volatile_reg(struct device *dev, unsigned int reg) 53 + { 54 + /* 55 + * Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but 56 + * we don't use that feature. It's better to cache. 57 + */ 58 + 59 + switch (reg) { 60 + case RK808_SECONDS_REG ... RK808_WEEKS_REG: 61 + case RK808_RTC_STATUS_REG: 62 + case RK808_VB_MON_REG: 63 + case RK808_THERMAL_REG: 64 + case RK816_DCDC_EN_REG1: 65 + case RK816_DCDC_EN_REG2: 66 + case RK816_INT_STS_REG1: 67 + case RK816_INT_STS_REG2: 68 + case RK816_INT_STS_REG3: 69 + case RK808_DEVCTRL_REG: 70 + case RK816_SUP_STS_REG: 71 + case RK816_GGSTS_REG: 72 + case RK816_ZERO_CUR_ADC_REGH: 73 + case RK816_ZERO_CUR_ADC_REGL: 74 + case RK816_GASCNT_REG(0) ... RK816_BAT_VOL_REGL: 46 75 return true; 47 76 } 48 77 ··· 129 100 .volatile_reg = rk808_is_volatile_reg, 130 101 }; 131 102 103 + static const struct regmap_config rk816_regmap_config = { 104 + .reg_bits = 8, 105 + .val_bits = 8, 106 + .max_register = RK816_DATA_REG(18), 107 + .cache_type = REGCACHE_MAPLE, 108 + .volatile_reg = rk816_is_volatile_reg, 109 + }; 110 + 132 111 static const struct regmap_config rk817_regmap_config = { 133 112 .reg_bits = 8, 134 113 .val_bits = 8, ··· 158 121 static const struct rk8xx_i2c_platform_data rk809_data = { 159 122 .regmap_cfg = &rk817_regmap_config, 160 123 .variant = RK809_ID, 124 + }; 125 + 126 + static const struct rk8xx_i2c_platform_data rk816_data = { 127 + .regmap_cfg = &rk816_regmap_config, 128 + .variant = RK816_ID, 161 129 }; 162 130 163 131 static const struct rk8xx_i2c_platform_data rk817_data = { ··· 203 161 { .compatible = "rockchip,rk805", .data = &rk805_data }, 204 162 { .compatible = "rockchip,rk808", .data = &rk808_data }, 205 163 { .compatible = "rockchip,rk809", .data = &rk809_data }, 164 + { .compatible = "rockchip,rk816", .data = &rk816_data }, 206 165 { .compatible = "rockchip,rk817", .data = &rk817_data }, 207 166 { .compatible = "rockchip,rk818", .data = &rk818_data }, 208 167 { },

+69

drivers/pinctrl/pinctrl-rk805.c

··· 93 93 RK806_PINMUX_FUN5, 94 94 }; 95 95 96 + enum rk816_pinmux_option { 97 + RK816_PINMUX_THERMISTOR, 98 + RK816_PINMUX_GPIO, 99 + }; 100 + 96 101 enum { 97 102 RK805_GPIO0, 98 103 RK805_GPIO1, ··· 107 102 RK806_GPIO_DVS1, 108 103 RK806_GPIO_DVS2, 109 104 RK806_GPIO_DVS3 105 + }; 106 + 107 + enum { 108 + RK816_GPIO0, 110 109 }; 111 110 112 111 static const char *const rk805_gpio_groups[] = { ··· 124 115 "gpio_pwrctrl3", 125 116 }; 126 117 118 + static const char *const rk816_gpio_groups[] = { 119 + "gpio0", 120 + }; 121 + 127 122 /* RK805: 2 output only GPIOs */ 128 123 static const struct pinctrl_pin_desc rk805_pins_desc[] = { 129 124 PINCTRL_PIN(RK805_GPIO0, "gpio0"), ··· 139 126 PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"), 140 127 PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"), 141 128 PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"), 129 + }; 130 + 131 + /* RK816 */ 132 + static const struct pinctrl_pin_desc rk816_pins_desc[] = { 133 + PINCTRL_PIN(RK816_GPIO0, "gpio0"), 142 134 }; 143 135 144 136 static const struct rk805_pin_function rk805_pin_functions[] = { ··· 194 176 }, 195 177 }; 196 178 179 + static const struct rk805_pin_function rk816_pin_functions[] = { 180 + { 181 + .name = "gpio", 182 + .groups = rk816_gpio_groups, 183 + .ngroups = ARRAY_SIZE(rk816_gpio_groups), 184 + .mux_option = RK816_PINMUX_GPIO, 185 + }, 186 + { 187 + .name = "thermistor", 188 + .groups = rk816_gpio_groups, 189 + .ngroups = ARRAY_SIZE(rk816_gpio_groups), 190 + .mux_option = RK816_PINMUX_THERMISTOR, 191 + }, 192 + }; 193 + 197 194 static const struct rk805_pin_group rk805_pin_groups[] = { 198 195 { 199 196 .name = "gpio0", ··· 238 205 .pins = { RK806_GPIO_DVS3 }, 239 206 .npins = 1, 240 207 } 208 + }; 209 + 210 + static const struct rk805_pin_group rk816_pin_groups[] = { 211 + { 212 + .name = "gpio0", 213 + .pins = { RK816_GPIO0 }, 214 + .npins = 1, 215 + }, 241 216 }; 242 217 243 218 #define RK805_GPIO0_VAL_MSK BIT(0) ··· 294 253 .val_msk = RK806_PWRCTRL3_DATA, 295 254 .dir_msk = RK806_PWRCTRL3_DR, 296 255 } 256 + }; 257 + 258 + #define RK816_FUN_MASK BIT(2) 259 + #define RK816_VAL_MASK BIT(3) 260 + #define RK816_DIR_MASK BIT(4) 261 + 262 + static struct rk805_pin_config rk816_gpio_cfgs[] = { 263 + { 264 + .fun_reg = RK818_IO_POL_REG, 265 + .fun_msk = RK816_FUN_MASK, 266 + .reg = RK818_IO_POL_REG, 267 + .val_msk = RK816_VAL_MASK, 268 + .dir_msk = RK816_DIR_MASK, 269 + }, 297 270 }; 298 271 299 272 /* generic gpio chip */ ··· 494 439 return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); 495 440 case RK806_ID: 496 441 return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5); 442 + case RK816_ID: 443 + return _rk805_pinctrl_set_mux(pctldev, offset, RK816_PINMUX_GPIO); 497 444 } 498 445 499 446 return -ENOTSUPP; ··· 644 587 pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc); 645 588 pci->pin_cfg = rk806_gpio_cfgs; 646 589 pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs); 590 + break; 591 + case RK816_ID: 592 + pci->pins = rk816_pins_desc; 593 + pci->num_pins = ARRAY_SIZE(rk816_pins_desc); 594 + pci->functions = rk816_pin_functions; 595 + pci->num_functions = ARRAY_SIZE(rk816_pin_functions); 596 + pci->groups = rk816_pin_groups; 597 + pci->num_pin_groups = ARRAY_SIZE(rk816_pin_groups); 598 + pci->pinctrl_desc.pins = rk816_pins_desc; 599 + pci->pinctrl_desc.npins = ARRAY_SIZE(rk816_pins_desc); 600 + pci->pin_cfg = rk816_gpio_cfgs; 601 + pci->gpio_chip.ngpio = ARRAY_SIZE(rk816_gpio_cfgs); 647 602 break; 648 603 default: 649 604 dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",

+89 -5

drivers/regulator/axp20x-regulator.c

··· 138 138 #define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0) 139 139 #define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0) 140 140 141 + #define AXP717_DCDC1_NUM_VOLTAGES 88 142 + #define AXP717_DCDC2_NUM_VOLTAGES 107 143 + #define AXP717_DCDC3_NUM_VOLTAGES 104 144 + #define AXP717_DCDC_V_OUT_MASK GENMASK(6, 0) 145 + #define AXP717_LDO_V_OUT_MASK GENMASK(4, 0) 146 + 141 147 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) 142 148 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) 143 149 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) ··· 739 733 static const struct regulator_desc axp313a_regulators[] = { 740 734 AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1", 741 735 axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES, 742 - AXP313A_DCDC1_CONRTOL, AXP313A_DCDC_V_OUT_MASK, 736 + AXP313A_DCDC1_CONTROL, AXP313A_DCDC_V_OUT_MASK, 743 737 AXP313A_OUTPUT_CONTROL, BIT(0)), 744 738 AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2", 745 739 axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES, 746 - AXP313A_DCDC2_CONRTOL, AXP313A_DCDC_V_OUT_MASK, 740 + AXP313A_DCDC2_CONTROL, AXP313A_DCDC_V_OUT_MASK, 747 741 AXP313A_OUTPUT_CONTROL, BIT(1)), 748 742 AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3", 749 743 axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES, 750 - AXP313A_DCDC3_CONRTOL, AXP313A_DCDC_V_OUT_MASK, 744 + AXP313A_DCDC3_CONTROL, AXP313A_DCDC_V_OUT_MASK, 751 745 AXP313A_OUTPUT_CONTROL, BIT(2)), 752 746 AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100, 753 - AXP313A_ALDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, 747 + AXP313A_ALDO1_CONTROL, AXP313A_LDO_V_OUT_MASK, 754 748 AXP313A_OUTPUT_CONTROL, BIT(3)), 755 749 AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100, 756 - AXP313A_DLDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, 750 + AXP313A_DLDO1_CONTROL, AXP313A_LDO_V_OUT_MASK, 757 751 AXP313A_OUTPUT_CONTROL, BIT(4)), 758 752 AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800), 753 + }; 754 + 755 + static const struct linear_range axp717_dcdc1_ranges[] = { 756 + REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 757 + REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 758 + }; 759 + 760 + static const struct linear_range axp717_dcdc2_ranges[] = { 761 + REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 762 + REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 763 + REGULATOR_LINEAR_RANGE(1600000, 88, 107, 100000), 764 + }; 765 + 766 + static const struct linear_range axp717_dcdc3_ranges[] = { 767 + REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 768 + REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000), 769 + }; 770 + 771 + static const struct regulator_desc axp717_regulators[] = { 772 + AXP_DESC_RANGES(AXP717, DCDC1, "dcdc1", "vin1", 773 + axp717_dcdc1_ranges, AXP717_DCDC1_NUM_VOLTAGES, 774 + AXP717_DCDC1_CONTROL, AXP717_DCDC_V_OUT_MASK, 775 + AXP717_DCDC_OUTPUT_CONTROL, BIT(0)), 776 + AXP_DESC_RANGES(AXP717, DCDC2, "dcdc2", "vin2", 777 + axp717_dcdc2_ranges, AXP717_DCDC2_NUM_VOLTAGES, 778 + AXP717_DCDC2_CONTROL, AXP717_DCDC_V_OUT_MASK, 779 + AXP717_DCDC_OUTPUT_CONTROL, BIT(1)), 780 + AXP_DESC_RANGES(AXP717, DCDC3, "dcdc3", "vin3", 781 + axp717_dcdc3_ranges, AXP717_DCDC3_NUM_VOLTAGES, 782 + AXP717_DCDC3_CONTROL, AXP717_DCDC_V_OUT_MASK, 783 + AXP717_DCDC_OUTPUT_CONTROL, BIT(2)), 784 + AXP_DESC(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100, 785 + AXP717_DCDC4_CONTROL, AXP717_DCDC_V_OUT_MASK, 786 + AXP717_DCDC_OUTPUT_CONTROL, BIT(3)), 787 + AXP_DESC(AXP717, ALDO1, "aldo1", "vin1", 500, 3500, 100, 788 + AXP717_ALDO1_CONTROL, AXP717_LDO_V_OUT_MASK, 789 + AXP717_LDO0_OUTPUT_CONTROL, BIT(0)), 790 + AXP_DESC(AXP717, ALDO2, "aldo2", "vin1", 500, 3500, 100, 791 + AXP717_ALDO2_CONTROL, AXP717_LDO_V_OUT_MASK, 792 + AXP717_LDO0_OUTPUT_CONTROL, BIT(1)), 793 + AXP_DESC(AXP717, ALDO3, "aldo3", "vin1", 500, 3500, 100, 794 + AXP717_ALDO3_CONTROL, AXP717_LDO_V_OUT_MASK, 795 + AXP717_LDO0_OUTPUT_CONTROL, BIT(2)), 796 + AXP_DESC(AXP717, ALDO4, "aldo4", "vin1", 500, 3500, 100, 797 + AXP717_ALDO4_CONTROL, AXP717_LDO_V_OUT_MASK, 798 + AXP717_LDO0_OUTPUT_CONTROL, BIT(3)), 799 + AXP_DESC(AXP717, BLDO1, "bldo1", "vin1", 500, 3500, 100, 800 + AXP717_BLDO1_CONTROL, AXP717_LDO_V_OUT_MASK, 801 + AXP717_LDO0_OUTPUT_CONTROL, BIT(4)), 802 + AXP_DESC(AXP717, BLDO2, "bldo2", "vin1", 500, 3500, 100, 803 + AXP717_BLDO2_CONTROL, AXP717_LDO_V_OUT_MASK, 804 + AXP717_LDO0_OUTPUT_CONTROL, BIT(5)), 805 + AXP_DESC(AXP717, BLDO3, "bldo3", "vin1", 500, 3500, 100, 806 + AXP717_BLDO3_CONTROL, AXP717_LDO_V_OUT_MASK, 807 + AXP717_LDO0_OUTPUT_CONTROL, BIT(6)), 808 + AXP_DESC(AXP717, BLDO4, "bldo4", "vin1", 500, 3500, 100, 809 + AXP717_BLDO4_CONTROL, AXP717_LDO_V_OUT_MASK, 810 + AXP717_LDO0_OUTPUT_CONTROL, BIT(7)), 811 + AXP_DESC(AXP717, CLDO1, "cldo1", "vin1", 500, 3500, 100, 812 + AXP717_CLDO1_CONTROL, AXP717_LDO_V_OUT_MASK, 813 + AXP717_LDO1_OUTPUT_CONTROL, BIT(0)), 814 + AXP_DESC(AXP717, CLDO2, "cldo2", "vin1", 500, 3500, 100, 815 + AXP717_CLDO2_CONTROL, AXP717_LDO_V_OUT_MASK, 816 + AXP717_LDO1_OUTPUT_CONTROL, BIT(1)), 817 + AXP_DESC(AXP717, CLDO3, "cldo3", "vin1", 500, 3500, 100, 818 + AXP717_CLDO3_CONTROL, AXP717_LDO_V_OUT_MASK, 819 + AXP717_LDO1_OUTPUT_CONTROL, BIT(2)), 820 + AXP_DESC(AXP717, CLDO4, "cldo4", "vin1", 500, 3500, 100, 821 + AXP717_CLDO4_CONTROL, AXP717_LDO_V_OUT_MASK, 822 + AXP717_LDO1_OUTPUT_CONTROL, BIT(3)), 823 + AXP_DESC(AXP717, CPUSLDO, "cpusldo", "vin1", 500, 1400, 50, 824 + AXP717_CPUSLDO_CONTROL, AXP717_LDO_V_OUT_MASK, 825 + AXP717_LDO1_OUTPUT_CONTROL, BIT(4)), 759 826 }; 760 827 761 828 /* DCDC ranges shared with AXP813 */ ··· 1332 1253 step = 150; 1333 1254 break; 1334 1255 case AXP313A_ID: 1256 + case AXP717_ID: 1335 1257 case AXP15060_ID: 1336 1258 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */ 1337 1259 if (dcdcfreq != 0) { ··· 1558 1478 case AXP313A_ID: 1559 1479 regulators = axp313a_regulators; 1560 1480 nregulators = AXP313A_REG_ID_MAX; 1481 + break; 1482 + case AXP717_ID: 1483 + regulators = axp717_regulators; 1484 + nregulators = AXP717_REG_ID_MAX; 1561 1485 break; 1562 1486 case AXP803_ID: 1563 1487 regulators = axp803_regulators;

+214 -4

drivers/regulator/rk808-regulator.c

··· 158 158 RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ 159 159 _vmask, _ereg, _emask, 0, 0, _etime, &rk808_reg_ops) 160 160 161 + #define RK816_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 162 + _vmask, _ereg, _emask, _disval, _etime) \ 163 + RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ 164 + _vmask, _ereg, _emask, _emask, _disval, _etime, &rk816_reg_ops) 165 + 161 166 #define RK817_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 162 167 _vmask, _ereg, _emask, _disval, _etime) \ 163 168 RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ ··· 263 258 2000, 4000, 6000, 10000 264 259 }; 265 260 266 - /* RK817 RK809 */ 261 + /* RK817/RK809/RK816 (buck 1/2 only) */ 267 262 static const unsigned int rk817_buck1_4_ramp_table[] = { 268 263 3000, 6300, 12500, 25000 269 264 }; ··· 539 534 { 540 535 unsigned int reg; 541 536 int sel = regulator_map_voltage_linear_range(rdev, uv, uv); 537 + int ret; 542 538 543 539 if (sel < 0) 544 540 return -EINVAL; 545 541 546 542 reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; 547 543 548 - return regmap_update_bits(rdev->regmap, reg, 549 - rdev->desc->vsel_mask, 550 - sel); 544 + ret = regmap_update_bits(rdev->regmap, reg, 545 + rdev->desc->vsel_mask, 546 + sel); 547 + if (ret) 548 + return ret; 549 + 550 + if (rdev->desc->apply_bit) 551 + ret = regmap_update_bits(rdev->regmap, rdev->desc->apply_reg, 552 + rdev->desc->apply_bit, 553 + rdev->desc->apply_bit); 554 + 555 + return ret; 551 556 } 552 557 553 558 static int rk805_set_suspend_enable(struct regulator_dev *rdev) ··· 643 628 return regmap_update_bits(rdev->regmap, reg, 644 629 rdev->desc->enable_mask, 645 630 rdev->desc->enable_mask); 631 + } 632 + 633 + static const struct rk8xx_register_bit rk816_suspend_bits[] = { 634 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 0), 635 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 1), 636 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 2), 637 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 3), 638 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 0), 639 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 1), 640 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 2), 641 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 3), 642 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 4), 643 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 5), 644 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 5), 645 + RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 6), 646 + }; 647 + 648 + static int rk816_set_suspend_enable(struct regulator_dev *rdev) 649 + { 650 + int rid = rdev_get_id(rdev); 651 + 652 + return regmap_update_bits(rdev->regmap, rk816_suspend_bits[rid].reg, 653 + rk816_suspend_bits[rid].bit, 654 + rk816_suspend_bits[rid].bit); 655 + } 656 + 657 + static int rk816_set_suspend_disable(struct regulator_dev *rdev) 658 + { 659 + int rid = rdev_get_id(rdev); 660 + 661 + return regmap_update_bits(rdev->regmap, rk816_suspend_bits[rid].reg, 662 + rk816_suspend_bits[rid].bit, 0); 646 663 } 647 664 648 665 static int rk817_set_suspend_enable_ctrl(struct regulator_dev *rdev, ··· 948 901 .set_suspend_voltage = rk808_set_suspend_voltage_range, 949 902 .set_suspend_enable = rk817_set_suspend_enable, 950 903 .set_suspend_disable = rk817_set_suspend_disable, 904 + }; 905 + 906 + static const struct regulator_ops rk816_buck1_2_ops_ranges = { 907 + .list_voltage = regulator_list_voltage_linear_range, 908 + .map_voltage = regulator_map_voltage_linear_range, 909 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 910 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 911 + .set_voltage_time_sel = regulator_set_voltage_time_sel, 912 + .enable = regulator_enable_regmap, 913 + .disable = regulator_disable_regmap, 914 + .is_enabled = regulator_is_enabled_regmap, 915 + .set_mode = rk8xx_set_mode, 916 + .get_mode = rk8xx_get_mode, 917 + .set_suspend_mode = rk8xx_set_suspend_mode, 918 + .set_ramp_delay = regulator_set_ramp_delay_regmap, 919 + .set_suspend_voltage = rk808_set_suspend_voltage_range, 920 + .set_suspend_enable = rk816_set_suspend_enable, 921 + .set_suspend_disable = rk816_set_suspend_disable, 922 + }; 923 + 924 + static const struct regulator_ops rk816_buck4_ops_ranges = { 925 + .list_voltage = regulator_list_voltage_linear_range, 926 + .map_voltage = regulator_map_voltage_linear_range, 927 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 928 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 929 + .set_voltage_time_sel = regulator_set_voltage_time_sel, 930 + .enable = regulator_enable_regmap, 931 + .disable = regulator_disable_regmap, 932 + .is_enabled = regulator_is_enabled_regmap, 933 + .set_mode = rk8xx_set_mode, 934 + .get_mode = rk8xx_get_mode, 935 + .set_suspend_mode = rk8xx_set_suspend_mode, 936 + .set_suspend_voltage = rk808_set_suspend_voltage_range, 937 + .set_suspend_enable = rk816_set_suspend_enable, 938 + .set_suspend_disable = rk816_set_suspend_disable, 939 + }; 940 + 941 + static const struct regulator_ops rk816_reg_ops = { 942 + .list_voltage = regulator_list_voltage_linear, 943 + .map_voltage = regulator_map_voltage_linear, 944 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 945 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 946 + .enable = regulator_enable_regmap, 947 + .disable = regulator_disable_regmap, 948 + .is_enabled = rk8xx_is_enabled_wmsk_regmap, 949 + .set_suspend_voltage = rk808_set_suspend_voltage, 950 + .set_suspend_enable = rk816_set_suspend_enable, 951 + .set_suspend_disable = rk816_set_suspend_disable, 951 952 }; 952 953 953 954 static const struct regulator_ops rk817_reg_ops = { ··· 1477 1382 DISABLE_VAL(3)), 1478 1383 }; 1479 1384 1385 + static const struct linear_range rk816_buck_4_voltage_ranges[] = { 1386 + REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000), 1387 + REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0), 1388 + }; 1389 + 1390 + static const struct regulator_desc rk816_reg[] = { 1391 + { 1392 + .name = "dcdc1", 1393 + .supply_name = "vcc1", 1394 + .of_match = of_match_ptr("dcdc1"), 1395 + .regulators_node = of_match_ptr("regulators"), 1396 + .id = RK816_ID_DCDC1, 1397 + .ops = &rk816_buck1_2_ops_ranges, 1398 + .type = REGULATOR_VOLTAGE, 1399 + .n_voltages = 64, 1400 + .linear_ranges = rk805_buck_1_2_voltage_ranges, 1401 + .n_linear_ranges = ARRAY_SIZE(rk805_buck_1_2_voltage_ranges), 1402 + .vsel_reg = RK818_BUCK1_ON_VSEL_REG, 1403 + .vsel_mask = RK818_BUCK_VSEL_MASK, 1404 + .apply_reg = RK816_DCDC_EN_REG2, 1405 + .apply_bit = RK816_BUCK_DVS_CONFIRM, 1406 + .enable_reg = RK816_DCDC_EN_REG1, 1407 + .enable_mask = BIT(4) | BIT(0), 1408 + .enable_val = BIT(4) | BIT(0), 1409 + .disable_val = BIT(4), 1410 + .ramp_reg = RK818_BUCK1_CONFIG_REG, 1411 + .ramp_mask = RK808_RAMP_RATE_MASK, 1412 + .ramp_delay_table = rk817_buck1_4_ramp_table, 1413 + .n_ramp_values = ARRAY_SIZE(rk817_buck1_4_ramp_table), 1414 + .of_map_mode = rk8xx_regulator_of_map_mode, 1415 + .owner = THIS_MODULE, 1416 + }, { 1417 + .name = "dcdc2", 1418 + .supply_name = "vcc2", 1419 + .of_match = of_match_ptr("dcdc2"), 1420 + .regulators_node = of_match_ptr("regulators"), 1421 + .id = RK816_ID_DCDC2, 1422 + .ops = &rk816_buck1_2_ops_ranges, 1423 + .type = REGULATOR_VOLTAGE, 1424 + .n_voltages = 64, 1425 + .linear_ranges = rk805_buck_1_2_voltage_ranges, 1426 + .n_linear_ranges = ARRAY_SIZE(rk805_buck_1_2_voltage_ranges), 1427 + .vsel_reg = RK818_BUCK2_ON_VSEL_REG, 1428 + .vsel_mask = RK818_BUCK_VSEL_MASK, 1429 + .apply_reg = RK816_DCDC_EN_REG2, 1430 + .apply_bit = RK816_BUCK_DVS_CONFIRM, 1431 + .enable_reg = RK816_DCDC_EN_REG1, 1432 + .enable_mask = BIT(5) | BIT(1), 1433 + .enable_val = BIT(5) | BIT(1), 1434 + .disable_val = BIT(5), 1435 + .ramp_reg = RK818_BUCK2_CONFIG_REG, 1436 + .ramp_mask = RK808_RAMP_RATE_MASK, 1437 + .ramp_delay_table = rk817_buck1_4_ramp_table, 1438 + .n_ramp_values = ARRAY_SIZE(rk817_buck1_4_ramp_table), 1439 + .of_map_mode = rk8xx_regulator_of_map_mode, 1440 + .owner = THIS_MODULE, 1441 + }, { 1442 + .name = "dcdc3", 1443 + .supply_name = "vcc3", 1444 + .of_match = of_match_ptr("dcdc3"), 1445 + .regulators_node = of_match_ptr("regulators"), 1446 + .id = RK816_ID_DCDC3, 1447 + .ops = &rk808_switch_ops, 1448 + .type = REGULATOR_VOLTAGE, 1449 + .n_voltages = 1, 1450 + .enable_reg = RK816_DCDC_EN_REG1, 1451 + .enable_mask = BIT(6) | BIT(2), 1452 + .enable_val = BIT(6) | BIT(2), 1453 + .disable_val = BIT(6), 1454 + .of_map_mode = rk8xx_regulator_of_map_mode, 1455 + .owner = THIS_MODULE, 1456 + }, { 1457 + .name = "dcdc4", 1458 + .supply_name = "vcc4", 1459 + .of_match = of_match_ptr("dcdc4"), 1460 + .regulators_node = of_match_ptr("regulators"), 1461 + .id = RK816_ID_DCDC4, 1462 + .ops = &rk816_buck4_ops_ranges, 1463 + .type = REGULATOR_VOLTAGE, 1464 + .n_voltages = 32, 1465 + .linear_ranges = rk816_buck_4_voltage_ranges, 1466 + .n_linear_ranges = ARRAY_SIZE(rk816_buck_4_voltage_ranges), 1467 + .vsel_reg = RK818_BUCK4_ON_VSEL_REG, 1468 + .vsel_mask = RK818_BUCK4_VSEL_MASK, 1469 + .enable_reg = RK816_DCDC_EN_REG1, 1470 + .enable_mask = BIT(7) | BIT(3), 1471 + .enable_val = BIT(7) | BIT(3), 1472 + .disable_val = BIT(7), 1473 + .of_map_mode = rk8xx_regulator_of_map_mode, 1474 + .owner = THIS_MODULE, 1475 + }, 1476 + RK816_DESC(RK816_ID_LDO1, "ldo1", "vcc5", 800, 3400, 100, 1477 + RK818_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK, 1478 + RK816_LDO_EN_REG1, ENABLE_MASK(0), DISABLE_VAL(0), 400), 1479 + RK816_DESC(RK816_ID_LDO2, "ldo2", "vcc5", 800, 3400, 100, 1480 + RK818_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK, 1481 + RK816_LDO_EN_REG1, ENABLE_MASK(1), DISABLE_VAL(1), 400), 1482 + RK816_DESC(RK816_ID_LDO3, "ldo3", "vcc5", 800, 3400, 100, 1483 + RK818_LDO3_ON_VSEL_REG, RK818_LDO_VSEL_MASK, 1484 + RK816_LDO_EN_REG1, ENABLE_MASK(2), DISABLE_VAL(2), 400), 1485 + RK816_DESC(RK816_ID_LDO4, "ldo4", "vcc6", 800, 3400, 100, 1486 + RK818_LDO4_ON_VSEL_REG, RK818_LDO_VSEL_MASK, 1487 + RK816_LDO_EN_REG1, ENABLE_MASK(3), DISABLE_VAL(3), 400), 1488 + RK816_DESC(RK816_ID_LDO5, "ldo5", "vcc6", 800, 3400, 100, 1489 + RK818_LDO5_ON_VSEL_REG, RK818_LDO_VSEL_MASK, 1490 + RK816_LDO_EN_REG2, ENABLE_MASK(0), DISABLE_VAL(0), 400), 1491 + RK816_DESC(RK816_ID_LDO6, "ldo6", "vcc6", 800, 3400, 100, 1492 + RK818_LDO6_ON_VSEL_REG, RK818_LDO_VSEL_MASK, 1493 + RK816_LDO_EN_REG2, ENABLE_MASK(1), DISABLE_VAL(1), 400), 1494 + }; 1495 + 1480 1496 static const struct regulator_desc rk817_reg[] = { 1481 1497 { 1482 1498 .name = "DCDC_REG1", ··· 1909 1703 case RK809_ID: 1910 1704 regulators = rk809_reg; 1911 1705 nregulators = RK809_NUM_REGULATORS; 1706 + break; 1707 + case RK816_ID: 1708 + regulators = rk816_reg; 1709 + nregulators = ARRAY_SIZE(rk816_reg); 1912 1710 break; 1913 1711 case RK817_ID: 1914 1712 regulators = rk817_reg;

+93 -5

include/linux/mfd/axp20x.h

··· 19 19 AXP223_ID, 20 20 AXP288_ID, 21 21 AXP313A_ID, 22 + AXP717_ID, 22 23 AXP803_ID, 23 24 AXP806_ID, 24 25 AXP809_ID, ··· 105 104 106 105 #define AXP313A_ON_INDICATE 0x00 107 106 #define AXP313A_OUTPUT_CONTROL 0x10 108 - #define AXP313A_DCDC1_CONRTOL 0x13 109 - #define AXP313A_DCDC2_CONRTOL 0x14 110 - #define AXP313A_DCDC3_CONRTOL 0x15 111 - #define AXP313A_ALDO1_CONRTOL 0x16 112 - #define AXP313A_DLDO1_CONRTOL 0x17 107 + #define AXP313A_DCDC1_CONTROL 0x13 108 + #define AXP313A_DCDC2_CONTROL 0x14 109 + #define AXP313A_DCDC3_CONTROL 0x15 110 + #define AXP313A_ALDO1_CONTROL 0x16 111 + #define AXP313A_DLDO1_CONTROL 0x17 113 112 #define AXP313A_SHUTDOWN_CTRL 0x1a 114 113 #define AXP313A_IRQ_EN 0x20 115 114 #define AXP313A_IRQ_STATE 0x21 115 + 116 + #define AXP717_ON_INDICATE 0x00 117 + #define AXP717_IRQ0_EN 0x40 118 + #define AXP717_IRQ1_EN 0x41 119 + #define AXP717_IRQ2_EN 0x42 120 + #define AXP717_IRQ3_EN 0x43 121 + #define AXP717_IRQ4_EN 0x44 122 + #define AXP717_IRQ0_STATE 0x48 123 + #define AXP717_IRQ1_STATE 0x49 124 + #define AXP717_IRQ2_STATE 0x4a 125 + #define AXP717_IRQ3_STATE 0x4b 126 + #define AXP717_IRQ4_STATE 0x4c 127 + #define AXP717_DCDC_OUTPUT_CONTROL 0x80 128 + #define AXP717_DCDC1_CONTROL 0x83 129 + #define AXP717_DCDC2_CONTROL 0x84 130 + #define AXP717_DCDC3_CONTROL 0x85 131 + #define AXP717_DCDC4_CONTROL 0x86 132 + #define AXP717_LDO0_OUTPUT_CONTROL 0x90 133 + #define AXP717_LDO1_OUTPUT_CONTROL 0x91 134 + #define AXP717_ALDO1_CONTROL 0x93 135 + #define AXP717_ALDO2_CONTROL 0x94 136 + #define AXP717_ALDO3_CONTROL 0x95 137 + #define AXP717_ALDO4_CONTROL 0x96 138 + #define AXP717_BLDO1_CONTROL 0x97 139 + #define AXP717_BLDO2_CONTROL 0x98 140 + #define AXP717_BLDO3_CONTROL 0x99 141 + #define AXP717_BLDO4_CONTROL 0x9a 142 + #define AXP717_CLDO1_CONTROL 0x9b 143 + #define AXP717_CLDO2_CONTROL 0x9c 144 + #define AXP717_CLDO3_CONTROL 0x9d 145 + #define AXP717_CLDO4_CONTROL 0x9e 146 + #define AXP717_CPUSLDO_CONTROL 0x9f 116 147 117 148 #define AXP806_STARTUP_SRC 0x00 118 149 #define AXP806_CHIP_ID 0x03 ··· 467 434 }; 468 435 469 436 enum { 437 + AXP717_DCDC1 = 0, 438 + AXP717_DCDC2, 439 + AXP717_DCDC3, 440 + AXP717_DCDC4, 441 + AXP717_ALDO1, 442 + AXP717_ALDO2, 443 + AXP717_ALDO3, 444 + AXP717_ALDO4, 445 + AXP717_BLDO1, 446 + AXP717_BLDO2, 447 + AXP717_BLDO3, 448 + AXP717_BLDO4, 449 + AXP717_CLDO1, 450 + AXP717_CLDO2, 451 + AXP717_CLDO3, 452 + AXP717_CLDO4, 453 + AXP717_CPUSLDO, 454 + AXP717_REG_ID_MAX, 455 + }; 456 + 457 + enum { 470 458 AXP806_DCDCA = 0, 471 459 AXP806_DCDCB, 472 460 AXP806_DCDCC, ··· 784 730 AXP313A_IRQ_PEK_SHORT, 785 731 AXP313A_IRQ_PEK_FAL_EDGE, 786 732 AXP313A_IRQ_PEK_RIS_EDGE, 733 + }; 734 + 735 + enum axp717_irqs { 736 + AXP717_IRQ_VBUS_FAULT, 737 + AXP717_IRQ_VBUS_OVER_V, 738 + AXP717_IRQ_BOOST_OVER_V, 739 + AXP717_IRQ_GAUGE_NEW_SOC = 4, 740 + AXP717_IRQ_SOC_DROP_LVL1 = 6, 741 + AXP717_IRQ_SOC_DROP_LVL2, 742 + AXP717_IRQ_PEK_RIS_EDGE, 743 + AXP717_IRQ_PEK_FAL_EDGE, 744 + AXP717_IRQ_PEK_LONG, 745 + AXP717_IRQ_PEK_SHORT, 746 + AXP717_IRQ_BATT_REMOVAL, 747 + AXP717_IRQ_BATT_PLUGIN, 748 + AXP717_IRQ_VBUS_REMOVAL, 749 + AXP717_IRQ_VBUS_PLUGIN, 750 + AXP717_IRQ_BATT_OVER_V, 751 + AXP717_IRQ_CHARG_TIMER, 752 + AXP717_IRQ_DIE_TEMP_HIGH, 753 + AXP717_IRQ_CHARG, 754 + AXP717_IRQ_CHARG_DONE, 755 + AXP717_IRQ_BATT_OVER_CURR, 756 + AXP717_IRQ_LDO_OVER_CURR, 757 + AXP717_IRQ_WDOG_EXPIRE, 758 + AXP717_IRQ_BATT_ACT_TEMP_LOW, 759 + AXP717_IRQ_BATT_ACT_TEMP_HIGH, 760 + AXP717_IRQ_BATT_CHG_TEMP_LOW, 761 + AXP717_IRQ_BATT_CHG_TEMP_HIGH, 762 + AXP717_IRQ_BATT_QUIT_TEMP_HIGH, 763 + AXP717_IRQ_BC_USB_CHNG = 30, 764 + AXP717_IRQ_BC_USB_DONE, 765 + AXP717_IRQ_TYPEC_PLUGIN = 37, 766 + AXP717_IRQ_TYPEC_REMOVE, 787 767 }; 788 768 789 769 enum axp803_irqs {

+144

include/linux/mfd/rk808.h

··· 113 113 #define RK808_INT_STS_MSK_REG2 0x4f 114 114 #define RK808_IO_POL_REG 0x50 115 115 116 + /* RK816 */ 117 + enum rk816_reg { 118 + RK816_ID_DCDC1, 119 + RK816_ID_DCDC2, 120 + RK816_ID_DCDC3, 121 + RK816_ID_DCDC4, 122 + RK816_ID_LDO1, 123 + RK816_ID_LDO2, 124 + RK816_ID_LDO3, 125 + RK816_ID_LDO4, 126 + RK816_ID_LDO5, 127 + RK816_ID_LDO6, 128 + RK816_ID_BOOST, 129 + RK816_ID_OTG_SW, 130 + }; 131 + 132 + enum rk816_irqs { 133 + /* INT_STS_REG1 */ 134 + RK816_IRQ_PWRON_FALL, 135 + RK816_IRQ_PWRON_RISE, 136 + 137 + /* INT_STS_REG2 */ 138 + RK816_IRQ_VB_LOW, 139 + RK816_IRQ_PWRON, 140 + RK816_IRQ_PWRON_LP, 141 + RK816_IRQ_HOTDIE, 142 + RK816_IRQ_RTC_ALARM, 143 + RK816_IRQ_RTC_PERIOD, 144 + RK816_IRQ_USB_OV, 145 + 146 + /* INT_STS_REG3 */ 147 + RK816_IRQ_PLUG_IN, 148 + RK816_IRQ_PLUG_OUT, 149 + RK816_IRQ_CHG_OK, 150 + RK816_IRQ_CHG_TE, 151 + RK816_IRQ_CHG_TS, 152 + RK816_IRQ_CHG_CVTLIM, 153 + RK816_IRQ_DISCHG_ILIM, 154 + }; 155 + 156 + /* power channel registers */ 157 + #define RK816_DCDC_EN_REG1 0x23 158 + 159 + #define RK816_DCDC_EN_REG2 0x24 160 + #define RK816_BOOST_EN BIT(1) 161 + #define RK816_OTG_EN BIT(2) 162 + #define RK816_BOOST_EN_MSK BIT(5) 163 + #define RK816_OTG_EN_MSK BIT(6) 164 + #define RK816_BUCK_DVS_CONFIRM BIT(7) 165 + 166 + #define RK816_LDO_EN_REG1 0x27 167 + 168 + #define RK816_LDO_EN_REG2 0x28 169 + 170 + /* interrupt registers and irq definitions */ 171 + #define RK816_INT_STS_REG1 0x49 172 + #define RK816_INT_STS_MSK_REG1 0x4a 173 + #define RK816_INT_STS_PWRON_FALL BIT(5) 174 + #define RK816_INT_STS_PWRON_RISE BIT(6) 175 + 176 + #define RK816_INT_STS_REG2 0x4c 177 + #define RK816_INT_STS_MSK_REG2 0x4d 178 + #define RK816_INT_STS_VB_LOW BIT(1) 179 + #define RK816_INT_STS_PWRON BIT(2) 180 + #define RK816_INT_STS_PWRON_LP BIT(3) 181 + #define RK816_INT_STS_HOTDIE BIT(4) 182 + #define RK816_INT_STS_RTC_ALARM BIT(5) 183 + #define RK816_INT_STS_RTC_PERIOD BIT(6) 184 + #define RK816_INT_STS_USB_OV BIT(7) 185 + 186 + #define RK816_INT_STS_REG3 0x4e 187 + #define RK816_INT_STS_MSK_REG3 0x4f 188 + #define RK816_INT_STS_PLUG_IN BIT(0) 189 + #define RK816_INT_STS_PLUG_OUT BIT(1) 190 + #define RK816_INT_STS_CHG_OK BIT(2) 191 + #define RK816_INT_STS_CHG_TE BIT(3) 192 + #define RK816_INT_STS_CHG_TS BIT(4) 193 + #define RK816_INT_STS_CHG_CVTLIM BIT(6) 194 + #define RK816_INT_STS_DISCHG_ILIM BIT(7) 195 + 196 + #define RK816_IRQ_STS_OFFSET(x) ((x) - RK816_INT_STS_REG1) 197 + #define RK816_IRQ_MSK_OFFSET(x) ((x) - RK816_INT_STS_MSK_REG1) 198 + 199 + /* charger, boost and OTG registers */ 200 + #define RK816_OTG_BUCK_LDO_CONFIG_REG 0x2a 201 + #define RK816_CHRG_CONFIG_REG 0x2b 202 + #define RK816_BOOST_ON_VESL_REG 0x54 203 + #define RK816_BOOST_SLP_VSEL_REG 0x55 204 + #define RK816_CHRG_BOOST_CONFIG_REG 0x9a 205 + #define RK816_SUP_STS_REG 0xa0 206 + #define RK816_USB_CTRL_REG 0xa1 207 + #define RK816_CHRG_CTRL(x) (0xa3 + (x)) 208 + #define RK816_BAT_CTRL_REG 0xa6 209 + #define RK816_BAT_HTS_TS_REG 0xa8 210 + #define RK816_BAT_LTS_TS_REG 0xa9 211 + 212 + /* adc and fuel gauge registers */ 213 + #define RK816_TS_CTRL_REG 0xac 214 + #define RK816_ADC_CTRL_REG 0xad 215 + #define RK816_GGCON_REG 0xb0 216 + #define RK816_GGSTS_REG 0xb1 217 + #define RK816_ZERO_CUR_ADC_REGH 0xb2 218 + #define RK816_ZERO_CUR_ADC_REGL 0xb3 219 + #define RK816_GASCNT_CAL_REG(x) (0xb7 - (x)) 220 + #define RK816_GASCNT_REG(x) (0xbb - (x)) 221 + #define RK816_BAT_CUR_AVG_REGH 0xbc 222 + #define RK816_BAT_CUR_AVG_REGL 0xbd 223 + #define RK816_TS_ADC_REGH 0xbe 224 + #define RK816_TS_ADC_REGL 0xbf 225 + #define RK816_USB_ADC_REGH 0xc0 226 + #define RK816_USB_ADC_REGL 0xc1 227 + #define RK816_BAT_OCV_REGH 0xc2 228 + #define RK816_BAT_OCV_REGL 0xc3 229 + #define RK816_BAT_VOL_REGH 0xc4 230 + #define RK816_BAT_VOL_REGL 0xc5 231 + #define RK816_RELAX_ENTRY_THRES_REGH 0xc6 232 + #define RK816_RELAX_ENTRY_THRES_REGL 0xc7 233 + #define RK816_RELAX_EXIT_THRES_REGH 0xc8 234 + #define RK816_RELAX_EXIT_THRES_REGL 0xc9 235 + #define RK816_RELAX_VOL1_REGH 0xca 236 + #define RK816_RELAX_VOL1_REGL 0xcb 237 + #define RK816_RELAX_VOL2_REGH 0xcc 238 + #define RK816_RELAX_VOL2_REGL 0xcd 239 + #define RK816_RELAX_CUR1_REGH 0xce 240 + #define RK816_RELAX_CUR1_REGL 0xcf 241 + #define RK816_RELAX_CUR2_REGH 0xd0 242 + #define RK816_RELAX_CUR2_REGL 0xd1 243 + #define RK816_CAL_OFFSET_REGH 0xd2 244 + #define RK816_CAL_OFFSET_REGL 0xd3 245 + #define RK816_NON_ACT_TIMER_CNT_REG 0xd4 246 + #define RK816_VCALIB0_REGH 0xd5 247 + #define RK816_VCALIB0_REGL 0xd6 248 + #define RK816_VCALIB1_REGH 0xd7 249 + #define RK816_VCALIB1_REGL 0xd8 250 + #define RK816_FCC_GASCNT_REG(x) (0xdc - (x)) 251 + #define RK816_IOFFSET_REGH 0xdd 252 + #define RK816_IOFFSET_REGL 0xde 253 + #define RK816_SLEEP_CON_SAMP_CUR_REG 0xdf 254 + 255 + /* general purpose data registers 0xe0 ~ 0xf2 */ 256 + #define RK816_DATA_REG(x) (0xe0 + (x)) 257 + 116 258 /* RK818 */ 117 259 #define RK818_DCDC1 0 118 260 #define RK818_LDO1 4 ··· 933 791 #define VOUT_LO_INT BIT(0) 934 792 #define CLK32KOUT2_EN BIT(0) 935 793 794 + #define TEMP105C 0x08 936 795 #define TEMP115C 0x0c 937 796 #define TEMP_HOTDIE_MSK 0x0c 938 797 #define SLP_SD_MSK (0x3 << 2) ··· 1334 1191 RK806_ID = 0x8060, 1335 1192 RK808_ID = 0x0000, 1336 1193 RK809_ID = 0x8090, 1194 + RK816_ID = 0x8160, 1337 1195 RK817_ID = 0x8170, 1338 1196 RK818_ID = 0x8180, 1339 1197 };

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