drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation

+5 -13

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

··· 1286 1286 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 1287 1287 struct dpu_global_state *global_state; 1288 1288 struct dpu_crtc_state *cstate; 1289 - struct drm_encoder *drm_enc; 1290 1289 struct msm_display_topology topology; 1291 1290 int ret; 1292 - 1293 - /* 1294 - * For now, grab the first encoder in the crtc state as we don't 1295 - * support clone mode yet 1296 - */ 1297 - drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) 1298 - break; 1299 1291 1300 1292 /* 1301 1293 * Release and Allocate resources on every modeset ··· 1296 1304 if (IS_ERR(global_state)) 1297 1305 return PTR_ERR(global_state); 1298 1306 1299 - dpu_rm_release(global_state, drm_enc); 1307 + dpu_rm_release(global_state, crtc); 1300 1308 1301 1309 if (!crtc_state->enable) 1302 1310 return 0; 1303 1311 1304 1312 topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state); 1305 1313 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 1306 - drm_enc, crtc_state, &topology); 1314 + crtc_state->crtc, &topology); 1307 1315 if (ret) 1308 1316 return ret; 1309 1317 1310 1318 cstate = to_dpu_crtc_state(crtc_state); 1311 1319 1312 1320 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1313 - drm_enc->base.id, 1321 + crtc_state->crtc, 1314 1322 DPU_HW_BLK_CTL, hw_ctl, 1315 1323 ARRAY_SIZE(hw_ctl)); 1316 1324 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1317 - drm_enc->base.id, 1325 + crtc_state->crtc, 1318 1326 DPU_HW_BLK_LM, hw_lm, 1319 1327 ARRAY_SIZE(hw_lm)); 1320 1328 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1321 - drm_enc->base.id, 1329 + crtc_state->crtc, 1322 1330 DPU_HW_BLK_DSPP, hw_dspp, 1323 1331 ARRAY_SIZE(hw_dspp)); 1324 1332

+5 -5

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

··· 1174 1174 1175 1175 /* Query resource that have been reserved in atomic check step. */ 1176 1176 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1177 - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1177 + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, 1178 1178 ARRAY_SIZE(hw_pp)); 1179 1179 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1180 - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1180 + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1181 1181 1182 1182 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1183 1183 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1184 1184 : NULL; 1185 1185 1186 1186 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1187 - drm_enc->base.id, DPU_HW_BLK_DSC, 1187 + drm_enc->crtc, DPU_HW_BLK_DSC, 1188 1188 hw_dsc, ARRAY_SIZE(hw_dsc)); 1189 1189 for (i = 0; i < num_dsc; i++) { 1190 1190 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); ··· 1198 1198 struct dpu_hw_blk *hw_cdm = NULL; 1199 1199 1200 1200 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1201 - drm_enc->base.id, DPU_HW_BLK_CDM, 1201 + drm_enc->crtc, DPU_HW_BLK_CDM, 1202 1202 &hw_cdm, 1); 1203 1203 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; 1204 1204 } ··· 2116 2116 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 2117 2117 2118 2118 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 2119 - phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 2119 + phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 2120 2120 2121 2121 for (i = 0; i < num_lm; i++) { 2122 2122 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);

+6 -6

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

··· 124 124 125 125 struct dpu_rm *rm; 126 126 127 - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; 128 - uint32_t mixer_to_enc_id[LM_MAX - LM_0]; 129 - uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; 130 - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; 131 - uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; 132 - uint32_t cdm_to_enc_id; 127 + uint32_t pingpong_to_crtc_id[PINGPONG_MAX - PINGPONG_0]; 128 + uint32_t mixer_to_crtc_id[LM_MAX - LM_0]; 129 + uint32_t ctl_to_crtc_id[CTL_MAX - CTL_0]; 130 + uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0]; 131 + uint32_t dsc_to_crtc_id[DSC_MAX - DSC_0]; 132 + uint32_t cdm_to_crtc_id; 133 133 134 134 uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; 135 135 };

+91 -98

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

··· 22 22 23 23 24 24 static inline bool reserved_by_other(uint32_t *res_map, int idx, 25 - uint32_t enc_id) 25 + uint32_t crtc_id) 26 26 { 27 - return res_map[idx] && res_map[idx] != enc_id; 27 + return res_map[idx] && res_map[idx] != crtc_id; 28 28 } 29 29 30 30 /** ··· 239 239 * pingpong 240 240 * @rm: dpu resource manager handle 241 241 * @global_state: resources shared across multiple kms objects 242 - * @enc_id: encoder id requesting for allocation 242 + * @crtc_id: crtc id requesting for allocation 243 243 * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function checks 244 244 * if lm, and all other hardwired blocks connected to the lm (pp) is 245 245 * available and appropriate ··· 252 252 */ 253 253 static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, 254 254 struct dpu_global_state *global_state, 255 - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, 255 + uint32_t crtc_id, int lm_idx, int *pp_idx, int *dspp_idx, 256 256 struct msm_display_topology *topology) 257 257 { 258 258 const struct dpu_lm_cfg *lm_cfg; 259 259 int idx; 260 260 261 261 /* Already reserved? */ 262 - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { 262 + if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) { 263 263 DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); 264 264 return false; 265 265 } ··· 271 271 return false; 272 272 } 273 273 274 - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { 274 + if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) { 275 275 DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, 276 276 lm_cfg->pingpong); 277 277 return false; ··· 287 287 return false; 288 288 } 289 289 290 - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { 290 + if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) { 291 291 DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, 292 292 lm_cfg->dspp); 293 293 return false; ··· 299 299 300 300 static int _dpu_rm_reserve_lms(struct dpu_rm *rm, 301 301 struct dpu_global_state *global_state, 302 - uint32_t enc_id, 302 + uint32_t crtc_id, 303 303 struct msm_display_topology *topology) 304 304 305 305 { ··· 323 323 lm_idx[lm_count] = i; 324 324 325 325 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, 326 - enc_id, i, &pp_idx[lm_count], 326 + crtc_id, i, &pp_idx[lm_count], 327 327 &dspp_idx[lm_count], topology)) { 328 328 continue; 329 329 } ··· 342 342 continue; 343 343 344 344 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, 345 - global_state, enc_id, j, 345 + global_state, crtc_id, j, 346 346 &pp_idx[lm_count], &dspp_idx[lm_count], 347 347 topology)) { 348 348 continue; ··· 359 359 } 360 360 361 361 for (i = 0; i < lm_count; i++) { 362 - global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; 363 - global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; 364 - global_state->dspp_to_enc_id[dspp_idx[i]] = 365 - topology->num_dspp ? enc_id : 0; 362 + global_state->mixer_to_crtc_id[lm_idx[i]] = crtc_id; 363 + global_state->pingpong_to_crtc_id[pp_idx[i]] = crtc_id; 364 + global_state->dspp_to_crtc_id[dspp_idx[i]] = 365 + topology->num_dspp ? crtc_id : 0; 366 366 367 - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, 367 + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, crtc_id, 368 368 pp_idx[i] + PINGPONG_0); 369 369 } 370 370 ··· 374 374 static int _dpu_rm_reserve_ctls( 375 375 struct dpu_rm *rm, 376 376 struct dpu_global_state *global_state, 377 - uint32_t enc_id, 377 + uint32_t crtc_id, 378 378 const struct msm_display_topology *top) 379 379 { 380 380 int ctl_idx[MAX_BLOCKS]; ··· 393 393 394 394 if (!rm->ctl_blks[j]) 395 395 continue; 396 - if (reserved_by_other(global_state->ctl_to_enc_id, j, enc_id)) 396 + if (reserved_by_other(global_state->ctl_to_crtc_id, j, crtc_id)) 397 397 continue; 398 398 399 399 ctl = to_dpu_hw_ctl(rm->ctl_blks[j]); ··· 417 417 return -ENAVAIL; 418 418 419 419 for (i = 0; i < ARRAY_SIZE(ctl_idx) && i < num_ctls; i++) { 420 - global_state->ctl_to_enc_id[ctl_idx[i]] = enc_id; 421 - trace_dpu_rm_reserve_ctls(i + CTL_0, enc_id); 420 + global_state->ctl_to_crtc_id[ctl_idx[i]] = crtc_id; 421 + trace_dpu_rm_reserve_ctls(i + CTL_0, crtc_id); 422 422 } 423 423 424 424 return 0; ··· 426 426 427 427 static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_state, 428 428 int start, 429 - uint32_t enc_id) 429 + uint32_t crtc_id) 430 430 { 431 431 int i; 432 432 433 433 for (i = start; i < (PINGPONG_MAX - PINGPONG_0); i++) { 434 - if (global_state->pingpong_to_enc_id[i] == enc_id) 434 + if (global_state->pingpong_to_crtc_id[i] == crtc_id) 435 435 return i; 436 436 } 437 437 ··· 452 452 453 453 static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, 454 454 struct dpu_global_state *global_state, 455 - uint32_t enc_id, 455 + uint32_t crtc_id, 456 456 const struct msm_display_topology *top) 457 457 { 458 458 int num_dsc = 0; ··· 465 465 if (!rm->dsc_blks[dsc_idx]) 466 466 continue; 467 467 468 - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) 468 + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id)) 469 469 continue; 470 470 471 - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); 471 + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); 472 472 if (pp_idx < 0) 473 473 return -ENAVAIL; 474 474 ··· 476 476 if (ret) 477 477 return -ENAVAIL; 478 478 479 - global_state->dsc_to_enc_id[dsc_idx] = enc_id; 479 + global_state->dsc_to_crtc_id[dsc_idx] = crtc_id; 480 480 num_dsc++; 481 481 pp_idx++; 482 482 } ··· 492 492 493 493 static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, 494 494 struct dpu_global_state *global_state, 495 - uint32_t enc_id, 495 + uint32_t crtc_id, 496 496 const struct msm_display_topology *top) 497 497 { 498 498 int num_dsc = 0; ··· 507 507 continue; 508 508 509 509 /* consective dsc index to be paired */ 510 - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || 511 - reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) 510 + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id) || 511 + reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx + 1, crtc_id)) 512 512 continue; 513 513 514 - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); 514 + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); 515 515 if (pp_idx < 0) 516 516 return -ENAVAIL; 517 517 ··· 521 521 continue; 522 522 } 523 523 524 - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); 524 + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, crtc_id); 525 525 if (pp_idx < 0) 526 526 return -ENAVAIL; 527 527 ··· 531 531 continue; 532 532 } 533 533 534 - global_state->dsc_to_enc_id[dsc_idx] = enc_id; 535 - global_state->dsc_to_enc_id[dsc_idx + 1] = enc_id; 534 + global_state->dsc_to_crtc_id[dsc_idx] = crtc_id; 535 + global_state->dsc_to_crtc_id[dsc_idx + 1] = crtc_id; 536 536 num_dsc += 2; 537 537 pp_idx++; /* start for next pair */ 538 538 } ··· 548 548 549 549 static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, 550 550 struct dpu_global_state *global_state, 551 - struct drm_encoder *enc, 551 + uint32_t crtc_id, 552 552 const struct msm_display_topology *top) 553 553 { 554 - uint32_t enc_id = enc->base.id; 555 - 556 554 if (!top->num_dsc || !top->num_intf) 557 555 return 0; 558 556 ··· 566 568 567 569 /* num_dsc should be either 1, 2 or 4 */ 568 570 if (top->num_dsc > top->num_intf) /* merge mode */ 569 - return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); 571 + return _dpu_rm_dsc_alloc_pair(rm, global_state, crtc_id, top); 570 572 else 571 - return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); 573 + return _dpu_rm_dsc_alloc(rm, global_state, crtc_id, top); 572 574 573 575 return 0; 574 576 } 575 577 576 578 static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, 577 579 struct dpu_global_state *global_state, 578 - struct drm_encoder *enc) 580 + uint32_t crtc_id) 579 581 { 580 582 /* try allocating only one CDM block */ 581 583 if (!rm->cdm_blk) { ··· 583 585 return -EIO; 584 586 } 585 587 586 - if (global_state->cdm_to_enc_id) { 588 + if (global_state->cdm_to_crtc_id) { 587 589 DPU_ERROR("CDM_0 is already allocated\n"); 588 590 return -EIO; 589 591 } 590 592 591 - global_state->cdm_to_enc_id = enc->base.id; 593 + global_state->cdm_to_crtc_id = crtc_id; 592 594 593 595 return 0; 594 596 } ··· 596 598 static int _dpu_rm_make_reservation( 597 599 struct dpu_rm *rm, 598 600 struct dpu_global_state *global_state, 599 - struct drm_encoder *enc, 601 + uint32_t crtc_id, 600 602 struct msm_display_topology *topology) 601 603 { 602 604 int ret; 603 605 604 - ret = _dpu_rm_reserve_lms(rm, global_state, enc->base.id, topology); 606 + ret = _dpu_rm_reserve_lms(rm, global_state, crtc_id, topology); 605 607 if (ret) { 606 608 DPU_ERROR("unable to find appropriate mixers\n"); 607 609 return ret; 608 610 } 609 611 610 - ret = _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, 612 + 613 + ret = _dpu_rm_reserve_ctls(rm, global_state, crtc_id, 611 614 topology); 612 615 if (ret) { 613 616 DPU_ERROR("unable to find appropriate CTL\n"); 614 617 return ret; 615 618 } 616 619 617 - ret = _dpu_rm_reserve_dsc(rm, global_state, enc, topology); 620 + ret = _dpu_rm_reserve_dsc(rm, global_state, crtc_id, topology); 618 621 if (ret) 619 622 return ret; 620 623 621 624 if (topology->needs_cdm) { 622 - ret = _dpu_rm_reserve_cdm(rm, global_state, enc); 625 + ret = _dpu_rm_reserve_cdm(rm, global_state, crtc_id); 623 626 if (ret) { 624 627 DPU_ERROR("unable to find CDM blk\n"); 625 628 return ret; ··· 631 632 } 632 633 633 634 static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, 634 - uint32_t enc_id) 635 + uint32_t crtc_id) 635 636 { 636 637 int i; 637 638 638 639 for (i = 0; i < cnt; i++) { 639 - if (res_mapping[i] == enc_id) 640 + if (res_mapping[i] == crtc_id) 640 641 res_mapping[i] = 0; 641 642 } 642 643 } ··· 645 646 * dpu_rm_release - Given the encoder for the display chain, release any 646 647 * HW blocks previously reserved for that use case. 647 648 * @global_state: resources shared across multiple kms objects 648 - * @enc: DRM Encoder handle 649 + * @crtc: DRM CRTC handle 649 650 * @return: 0 on Success otherwise -ERROR 650 651 */ 651 652 void dpu_rm_release(struct dpu_global_state *global_state, 652 - struct drm_encoder *enc) 653 + struct drm_crtc *crtc) 653 654 { 654 - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, 655 - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); 656 - _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, 657 - ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); 658 - _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, 659 - ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); 660 - _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, 661 - ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); 662 - _dpu_rm_clear_mapping(global_state->dspp_to_enc_id, 663 - ARRAY_SIZE(global_state->dspp_to_enc_id), enc->base.id); 664 - _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); 655 + uint32_t crtc_id = crtc->base.id; 656 + 657 + _dpu_rm_clear_mapping(global_state->pingpong_to_crtc_id, 658 + ARRAY_SIZE(global_state->pingpong_to_crtc_id), crtc_id); 659 + _dpu_rm_clear_mapping(global_state->mixer_to_crtc_id, 660 + ARRAY_SIZE(global_state->mixer_to_crtc_id), crtc_id); 661 + _dpu_rm_clear_mapping(global_state->ctl_to_crtc_id, 662 + ARRAY_SIZE(global_state->ctl_to_crtc_id), crtc_id); 663 + _dpu_rm_clear_mapping(global_state->dsc_to_crtc_id, 664 + ARRAY_SIZE(global_state->dsc_to_crtc_id), crtc_id); 665 + _dpu_rm_clear_mapping(global_state->dspp_to_crtc_id, 666 + ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id); 667 + _dpu_rm_clear_mapping(&global_state->cdm_to_crtc_id, 1, crtc_id); 665 668 } 666 669 667 670 /** ··· 675 674 * HW Reservations should be released via dpu_rm_release_hw. 676 675 * @rm: DPU Resource Manager handle 677 676 * @global_state: resources shared across multiple kms objects 678 - * @enc: DRM Encoder handle 679 - * @crtc_state: Proposed Atomic DRM CRTC State handle 677 + * @crtc: DRM CRTC handle 680 678 * @topology: Pointer to topology info for the display 681 679 * @return: 0 on Success otherwise -ERROR 682 680 */ 683 681 int dpu_rm_reserve( 684 682 struct dpu_rm *rm, 685 683 struct dpu_global_state *global_state, 686 - struct drm_encoder *enc, 687 - struct drm_crtc_state *crtc_state, 684 + struct drm_crtc *crtc, 688 685 struct msm_display_topology *topology) 689 686 { 690 687 int ret; 691 - 692 - /* Check if this is just a page-flip */ 693 - if (!drm_atomic_crtc_needs_modeset(crtc_state)) 694 - return 0; 695 688 696 689 if (IS_ERR(global_state)) { 697 690 DPU_ERROR("failed to global state\n"); 698 691 return PTR_ERR(global_state); 699 692 } 700 693 701 - DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", 702 - enc->base.id, crtc_state->crtc->base.id); 694 + DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc->base.id); 703 695 704 696 DRM_DEBUG_KMS("num_lm: %d num_dsc: %d num_intf: %d\n", 705 697 topology->num_lm, topology->num_dsc, 706 698 topology->num_intf); 707 699 708 - ret = _dpu_rm_make_reservation(rm, global_state, enc, topology); 700 + ret = _dpu_rm_make_reservation(rm, global_state, crtc->base.id, topology); 709 701 if (ret) 710 702 DPU_ERROR("failed to reserve hw resources: %d\n", ret); 711 - 712 - 713 703 714 704 return ret; 715 705 } ··· 792 800 * assigned to this encoder 793 801 * @rm: DPU Resource Manager handle 794 802 * @global_state: resources shared across multiple kms objects 795 - * @enc_id: encoder id requesting for allocation 803 + * @crtc: DRM CRTC handle 796 804 * @type: resource type to return data for 797 805 * @blks: pointer to the array to be filled by HW resources 798 806 * @blks_size: size of the @blks array 799 807 */ 800 808 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 801 - struct dpu_global_state *global_state, uint32_t enc_id, 809 + struct dpu_global_state *global_state, struct drm_crtc *crtc, 802 810 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) 803 811 { 812 + uint32_t crtc_id = crtc->base.id; 804 813 struct dpu_hw_blk **hw_blks; 805 - uint32_t *hw_to_enc_id; 814 + uint32_t *hw_to_crtc_id; 806 815 int i, num_blks, max_blks; 807 816 808 817 switch (type) { 809 818 case DPU_HW_BLK_PINGPONG: 810 819 hw_blks = rm->pingpong_blks; 811 - hw_to_enc_id = global_state->pingpong_to_enc_id; 820 + hw_to_crtc_id = global_state->pingpong_to_crtc_id; 812 821 max_blks = ARRAY_SIZE(rm->pingpong_blks); 813 822 break; 814 823 case DPU_HW_BLK_LM: 815 824 hw_blks = rm->mixer_blks; 816 - hw_to_enc_id = global_state->mixer_to_enc_id; 825 + hw_to_crtc_id = global_state->mixer_to_crtc_id; 817 826 max_blks = ARRAY_SIZE(rm->mixer_blks); 818 827 break; 819 828 case DPU_HW_BLK_CTL: 820 829 hw_blks = rm->ctl_blks; 821 - hw_to_enc_id = global_state->ctl_to_enc_id; 830 + hw_to_crtc_id = global_state->ctl_to_crtc_id; 822 831 max_blks = ARRAY_SIZE(rm->ctl_blks); 823 832 break; 824 833 case DPU_HW_BLK_DSPP: 825 834 hw_blks = rm->dspp_blks; 826 - hw_to_enc_id = global_state->dspp_to_enc_id; 835 + hw_to_crtc_id = global_state->dspp_to_crtc_id; 827 836 max_blks = ARRAY_SIZE(rm->dspp_blks); 828 837 break; 829 838 case DPU_HW_BLK_DSC: 830 839 hw_blks = rm->dsc_blks; 831 - hw_to_enc_id = global_state->dsc_to_enc_id; 840 + hw_to_crtc_id = global_state->dsc_to_crtc_id; 832 841 max_blks = ARRAY_SIZE(rm->dsc_blks); 833 842 break; 834 843 case DPU_HW_BLK_CDM: 835 844 hw_blks = &rm->cdm_blk; 836 - hw_to_enc_id = &global_state->cdm_to_enc_id; 845 + hw_to_crtc_id = &global_state->cdm_to_crtc_id; 837 846 max_blks = 1; 838 847 break; 839 848 default: ··· 844 851 845 852 num_blks = 0; 846 853 for (i = 0; i < max_blks; i++) { 847 - if (hw_to_enc_id[i] != enc_id) 854 + if (hw_to_crtc_id[i] != crtc_id) 848 855 continue; 849 856 850 857 if (num_blks == blks_size) { 851 - DPU_ERROR("More than %d resources assigned to enc %d\n", 852 - blks_size, enc_id); 858 + DPU_ERROR("More than %d resources assigned to crtc %d\n", 859 + blks_size, crtc_id); 853 860 break; 854 861 } 855 862 if (!hw_blks[i]) { 856 - DPU_ERROR("Allocated resource %d unavailable to assign to enc %d\n", 857 - type, enc_id); 863 + DPU_ERROR("Allocated resource %d unavailable to assign to crtc %d\n", 864 + type, crtc_id); 858 865 break; 859 866 } 860 867 blks[num_blks++] = hw_blks[i]; ··· 889 896 890 897 drm_puts(p, "resource mapping:\n"); 891 898 drm_puts(p, "\tpingpong="); 892 - for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) 899 + for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_crtc_id); i++) 893 900 dpu_rm_print_state_helper(p, rm->pingpong_blks[i], 894 - global_state->pingpong_to_enc_id[i]); 901 + global_state->pingpong_to_crtc_id[i]); 895 902 drm_puts(p, "\n"); 896 903 897 904 drm_puts(p, "\tmixer="); 898 - for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) 905 + for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_crtc_id); i++) 899 906 dpu_rm_print_state_helper(p, rm->mixer_blks[i], 900 - global_state->mixer_to_enc_id[i]); 907 + global_state->mixer_to_crtc_id[i]); 901 908 drm_puts(p, "\n"); 902 909 903 910 drm_puts(p, "\tctl="); 904 - for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) 911 + for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_crtc_id); i++) 905 912 dpu_rm_print_state_helper(p, rm->ctl_blks[i], 906 - global_state->ctl_to_enc_id[i]); 913 + global_state->ctl_to_crtc_id[i]); 907 914 drm_puts(p, "\n"); 908 915 909 916 drm_puts(p, "\tdspp="); 910 - for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) 917 + for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_crtc_id); i++) 911 918 dpu_rm_print_state_helper(p, rm->dspp_blks[i], 912 - global_state->dspp_to_enc_id[i]); 919 + global_state->dspp_to_crtc_id[i]); 913 920 drm_puts(p, "\n"); 914 921 915 922 drm_puts(p, "\tdsc="); 916 - for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) 923 + for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_crtc_id); i++) 917 924 dpu_rm_print_state_helper(p, rm->dsc_blks[i], 918 - global_state->dsc_to_enc_id[i]); 925 + global_state->dsc_to_crtc_id[i]); 919 926 drm_puts(p, "\n"); 920 927 921 928 drm_puts(p, "\tcdm="); 922 929 dpu_rm_print_state_helper(p, rm->cdm_blk, 923 - global_state->cdm_to_enc_id); 930 + global_state->cdm_to_crtc_id); 924 931 drm_puts(p, "\n"); 925 932 926 933 drm_puts(p, "\tsspp=");

+3 -4

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

··· 69 69 70 70 int dpu_rm_reserve(struct dpu_rm *rm, 71 71 struct dpu_global_state *global_state, 72 - struct drm_encoder *drm_enc, 73 - struct drm_crtc_state *crtc_state, 72 + struct drm_crtc *crtc, 74 73 struct msm_display_topology *topology); 75 74 76 75 void dpu_rm_release(struct dpu_global_state *global_state, 77 - struct drm_encoder *enc); 76 + struct drm_crtc *crtc); 78 77 79 78 struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, 80 79 struct dpu_global_state *global_state, ··· 84 85 struct drm_crtc *crtc); 85 86 86 87 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 87 - struct dpu_global_state *global_state, uint32_t enc_id, 88 + struct dpu_global_state *global_state, struct drm_crtc *crtc, 88 89 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 89 90 90 91 void dpu_rm_print_state(struct drm_printer *p,

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