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arm64: dts: lg: Refactor common LG1312 and LG1313 parts

The LG1312 and LG1313 DT are almost identical with the exception of the
ethernet node. Refactor the common parts into a separate .dtsi file and
include it.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-1-e210e797c2d7@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

Rob Herring (Arm) and committed by
Arnd Bergmann caec3157 86731a2a

+337 -644
+2 -322
arch/arm64/boot/dts/lg/lg1312.dtsi
··· 5 5 * Copyright (C) 2016, LG Electronics 6 6 */ 7 7 8 - #include <dt-bindings/gpio/gpio.h> 9 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 9 10 + #include "lg131x.dtsi" 11 + 11 12 / { 12 - #address-cells = <2>; 13 - #size-cells = <2>; 14 - 15 13 compatible = "lge,lg1312"; 16 - interrupt-parent = <&gic>; 17 - 18 - cpus { 19 - #address-cells = <2>; 20 - #size-cells = <0>; 21 - 22 - cpu0: cpu@0 { 23 - device_type = "cpu"; 24 - compatible = "arm,cortex-a53"; 25 - reg = <0x0 0x0>; 26 - next-level-cache = <&L2_0>; 27 - }; 28 - cpu1: cpu@1 { 29 - device_type = "cpu"; 30 - compatible = "arm,cortex-a53"; 31 - reg = <0x0 0x1>; 32 - enable-method = "psci"; 33 - next-level-cache = <&L2_0>; 34 - }; 35 - cpu2: cpu@2 { 36 - device_type = "cpu"; 37 - compatible = "arm,cortex-a53"; 38 - reg = <0x0 0x2>; 39 - enable-method = "psci"; 40 - next-level-cache = <&L2_0>; 41 - }; 42 - cpu3: cpu@3 { 43 - device_type = "cpu"; 44 - compatible = "arm,cortex-a53"; 45 - reg = <0x0 0x3>; 46 - enable-method = "psci"; 47 - next-level-cache = <&L2_0>; 48 - }; 49 - L2_0: l2-cache0 { 50 - compatible = "cache"; 51 - cache-level = <2>; 52 - cache-unified; 53 - }; 54 - }; 55 - 56 - psci { 57 - compatible = "arm,psci-0.2", "arm,psci"; 58 - method = "smc"; 59 - cpu_suspend = <0x84000001>; 60 - cpu_off = <0x84000002>; 61 - cpu_on = <0x84000003>; 62 - }; 63 - 64 - gic: interrupt-controller@c0001000 { 65 - #interrupt-cells = <3>; 66 - compatible = "arm,gic-400"; 67 - interrupt-controller; 68 - reg = <0x0 0xc0001000 0x1000>, 69 - <0x0 0xc0002000 0x2000>, 70 - <0x0 0xc0004000 0x2000>, 71 - <0x0 0xc0006000 0x2000>; 72 - }; 73 - 74 - pmu { 75 - compatible = "arm,cortex-a53-pmu"; 76 - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 77 - <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 78 - <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 79 - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 80 - interrupt-affinity = <&cpu0>, 81 - <&cpu1>, 82 - <&cpu2>, 83 - <&cpu3>; 84 - }; 85 - 86 - timer { 87 - compatible = "arm,armv8-timer"; 88 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | 89 - IRQ_TYPE_LEVEL_LOW)>, 90 - <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | 91 - IRQ_TYPE_LEVEL_LOW)>, 92 - <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | 93 - IRQ_TYPE_LEVEL_LOW)>, 94 - <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | 95 - IRQ_TYPE_LEVEL_LOW)>; 96 - }; 97 - 98 - clk_bus: clk_bus { 99 - #clock-cells = <0>; 100 - 101 - compatible = "fixed-clock"; 102 - clock-frequency = <198000000>; 103 - clock-output-names = "BUSCLK"; 104 - }; 105 14 106 15 soc { 107 16 #address-cells = <2>; ··· 29 120 phy-mode = "rmii"; 30 121 /* Filled in by boot */ 31 122 mac-address = [ 00 00 00 00 00 00 ]; 32 - }; 33 - }; 34 - 35 - amba { 36 - #address-cells = <2>; 37 - #size-cells = <1>; 38 - 39 - compatible = "simple-bus"; 40 - interrupt-parent = <&gic>; 41 - ranges; 42 - 43 - timers: timer@fd100000 { 44 - compatible = "arm,sp804", "arm,primecell"; 45 - reg = <0x0 0xfd100000 0x1000>; 46 - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 47 - clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; 48 - clock-names = "timer0clk", "timer1clk", "apb_pclk"; 49 - }; 50 - wdog: watchdog@fd200000 { 51 - compatible = "arm,sp805", "arm,primecell"; 52 - reg = <0x0 0xfd200000 0x1000>; 53 - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 54 - clocks = <&clk_bus>, <&clk_bus>; 55 - clock-names = "wdog_clk", "apb_pclk"; 56 - }; 57 - uart0: serial@fe000000 { 58 - compatible = "arm,pl011", "arm,primecell"; 59 - reg = <0x0 0xfe000000 0x1000>; 60 - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 61 - clocks = <&clk_bus>; 62 - clock-names = "apb_pclk"; 63 - status = "disabled"; 64 - }; 65 - uart1: serial@fe100000 { 66 - compatible = "arm,pl011", "arm,primecell"; 67 - reg = <0x0 0xfe100000 0x1000>; 68 - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 69 - clocks = <&clk_bus>; 70 - clock-names = "apb_pclk"; 71 - status = "disabled"; 72 - }; 73 - uart2: serial@fe200000 { 74 - compatible = "arm,pl011", "arm,primecell"; 75 - reg = <0x0 0xfe200000 0x1000>; 76 - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 77 - clocks = <&clk_bus>; 78 - clock-names = "apb_pclk"; 79 - status = "disabled"; 80 - }; 81 - spi0: spi@fe800000 { 82 - compatible = "arm,pl022", "arm,primecell"; 83 - reg = <0x0 0xfe800000 0x1000>; 84 - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 85 - clocks = <&clk_bus>, <&clk_bus>; 86 - clock-names = "sspclk", "apb_pclk"; 87 - }; 88 - spi1: spi@fe900000 { 89 - compatible = "arm,pl022", "arm,primecell"; 90 - reg = <0x0 0xfe900000 0x1000>; 91 - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 92 - clocks = <&clk_bus>, <&clk_bus>; 93 - clock-names = "sspclk", "apb_pclk"; 94 - }; 95 - dmac0: dma-controller@c1128000 { 96 - compatible = "arm,pl330", "arm,primecell"; 97 - reg = <0x0 0xc1128000 0x1000>; 98 - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 99 - clocks = <&clk_bus>; 100 - clock-names = "apb_pclk"; 101 - #dma-cells = <1>; 102 - }; 103 - gpio0: gpio@fd400000 { 104 - #gpio-cells = <2>; 105 - compatible = "arm,pl061", "arm,primecell"; 106 - gpio-controller; 107 - reg = <0x0 0xfd400000 0x1000>; 108 - clocks = <&clk_bus>; 109 - clock-names = "apb_pclk"; 110 - status = "disabled"; 111 - }; 112 - gpio1: gpio@fd410000 { 113 - #gpio-cells = <2>; 114 - compatible = "arm,pl061", "arm,primecell"; 115 - gpio-controller; 116 - reg = <0x0 0xfd410000 0x1000>; 117 - clocks = <&clk_bus>; 118 - clock-names = "apb_pclk"; 119 - status = "disabled"; 120 - }; 121 - gpio2: gpio@fd420000 { 122 - #gpio-cells = <2>; 123 - compatible = "arm,pl061", "arm,primecell"; 124 - gpio-controller; 125 - reg = <0x0 0xfd420000 0x1000>; 126 - clocks = <&clk_bus>; 127 - clock-names = "apb_pclk"; 128 - status = "disabled"; 129 - }; 130 - gpio3: gpio@fd430000 { 131 - #gpio-cells = <2>; 132 - compatible = "arm,pl061", "arm,primecell"; 133 - gpio-controller; 134 - reg = <0x0 0xfd430000 0x1000>; 135 - clocks = <&clk_bus>; 136 - clock-names = "apb_pclk"; 137 - }; 138 - gpio4: gpio@fd440000 { 139 - #gpio-cells = <2>; 140 - compatible = "arm,pl061", "arm,primecell"; 141 - gpio-controller; 142 - reg = <0x0 0xfd440000 0x1000>; 143 - clocks = <&clk_bus>; 144 - clock-names = "apb_pclk"; 145 - status = "disabled"; 146 - }; 147 - gpio5: gpio@fd450000 { 148 - #gpio-cells = <2>; 149 - compatible = "arm,pl061", "arm,primecell"; 150 - gpio-controller; 151 - reg = <0x0 0xfd450000 0x1000>; 152 - clocks = <&clk_bus>; 153 - clock-names = "apb_pclk"; 154 - status = "disabled"; 155 - }; 156 - gpio6: gpio@fd460000 { 157 - #gpio-cells = <2>; 158 - compatible = "arm,pl061", "arm,primecell"; 159 - gpio-controller; 160 - reg = <0x0 0xfd460000 0x1000>; 161 - clocks = <&clk_bus>; 162 - clock-names = "apb_pclk"; 163 - status = "disabled"; 164 - }; 165 - gpio7: gpio@fd470000 { 166 - #gpio-cells = <2>; 167 - compatible = "arm,pl061", "arm,primecell"; 168 - gpio-controller; 169 - reg = <0x0 0xfd470000 0x1000>; 170 - clocks = <&clk_bus>; 171 - clock-names = "apb_pclk"; 172 - status = "disabled"; 173 - }; 174 - gpio8: gpio@fd480000 { 175 - #gpio-cells = <2>; 176 - compatible = "arm,pl061", "arm,primecell"; 177 - gpio-controller; 178 - reg = <0x0 0xfd480000 0x1000>; 179 - clocks = <&clk_bus>; 180 - clock-names = "apb_pclk"; 181 - status = "disabled"; 182 - }; 183 - gpio9: gpio@fd490000 { 184 - #gpio-cells = <2>; 185 - compatible = "arm,pl061", "arm,primecell"; 186 - gpio-controller; 187 - reg = <0x0 0xfd490000 0x1000>; 188 - clocks = <&clk_bus>; 189 - clock-names = "apb_pclk"; 190 - status = "disabled"; 191 - }; 192 - gpio10: gpio@fd4a0000 { 193 - #gpio-cells = <2>; 194 - compatible = "arm,pl061", "arm,primecell"; 195 - gpio-controller; 196 - reg = <0x0 0xfd4a0000 0x1000>; 197 - clocks = <&clk_bus>; 198 - clock-names = "apb_pclk"; 199 - status = "disabled"; 200 - }; 201 - gpio11: gpio@fd4b0000 { 202 - #gpio-cells = <2>; 203 - compatible = "arm,pl061", "arm,primecell"; 204 - gpio-controller; 205 - reg = <0x0 0xfd4b0000 0x1000>; 206 - clocks = <&clk_bus>; 207 - clock-names = "apb_pclk"; 208 - }; 209 - gpio12: gpio@fd4c0000 { 210 - #gpio-cells = <2>; 211 - compatible = "arm,pl061", "arm,primecell"; 212 - gpio-controller; 213 - reg = <0x0 0xfd4c0000 0x1000>; 214 - clocks = <&clk_bus>; 215 - clock-names = "apb_pclk"; 216 - status = "disabled"; 217 - }; 218 - gpio13: gpio@fd4d0000 { 219 - #gpio-cells = <2>; 220 - compatible = "arm,pl061", "arm,primecell"; 221 - gpio-controller; 222 - reg = <0x0 0xfd4d0000 0x1000>; 223 - clocks = <&clk_bus>; 224 - clock-names = "apb_pclk"; 225 - status = "disabled"; 226 - }; 227 - gpio14: gpio@fd4e0000 { 228 - #gpio-cells = <2>; 229 - compatible = "arm,pl061", "arm,primecell"; 230 - gpio-controller; 231 - reg = <0x0 0xfd4e0000 0x1000>; 232 - clocks = <&clk_bus>; 233 - clock-names = "apb_pclk"; 234 - status = "disabled"; 235 - }; 236 - gpio15: gpio@fd4f0000 { 237 - #gpio-cells = <2>; 238 - compatible = "arm,pl061", "arm,primecell"; 239 - gpio-controller; 240 - reg = <0x0 0xfd4f0000 0x1000>; 241 - clocks = <&clk_bus>; 242 - clock-names = "apb_pclk"; 243 - status = "disabled"; 244 - }; 245 - gpio16: gpio@fd500000 { 246 - #gpio-cells = <2>; 247 - compatible = "arm,pl061", "arm,primecell"; 248 - gpio-controller; 249 - reg = <0x0 0xfd500000 0x1000>; 250 - clocks = <&clk_bus>; 251 - clock-names = "apb_pclk"; 252 - status = "disabled"; 253 - }; 254 - gpio17: gpio@fd510000 { 255 - #gpio-cells = <2>; 256 - compatible = "arm,pl061", "arm,primecell"; 257 - gpio-controller; 258 - reg = <0x0 0xfd510000 0x1000>; 259 - clocks = <&clk_bus>; 260 - clock-names = "apb_pclk"; 261 123 }; 262 124 }; 263 125 };
+2 -322
arch/arm64/boot/dts/lg/lg1313.dtsi
··· 5 5 * Copyright (C) 2016, LG Electronics 6 6 */ 7 7 8 - #include <dt-bindings/gpio/gpio.h> 9 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 9 10 + #include "lg131x.dtsi" 11 + 11 12 / { 12 - #address-cells = <2>; 13 - #size-cells = <2>; 14 - 15 13 compatible = "lge,lg1313"; 16 - interrupt-parent = <&gic>; 17 - 18 - cpus { 19 - #address-cells = <2>; 20 - #size-cells = <0>; 21 - 22 - cpu0: cpu@0 { 23 - device_type = "cpu"; 24 - compatible = "arm,cortex-a53"; 25 - reg = <0x0 0x0>; 26 - next-level-cache = <&L2_0>; 27 - }; 28 - cpu1: cpu@1 { 29 - device_type = "cpu"; 30 - compatible = "arm,cortex-a53"; 31 - reg = <0x0 0x1>; 32 - enable-method = "psci"; 33 - next-level-cache = <&L2_0>; 34 - }; 35 - cpu2: cpu@2 { 36 - device_type = "cpu"; 37 - compatible = "arm,cortex-a53"; 38 - reg = <0x0 0x2>; 39 - enable-method = "psci"; 40 - next-level-cache = <&L2_0>; 41 - }; 42 - cpu3: cpu@3 { 43 - device_type = "cpu"; 44 - compatible = "arm,cortex-a53"; 45 - reg = <0x0 0x3>; 46 - enable-method = "psci"; 47 - next-level-cache = <&L2_0>; 48 - }; 49 - L2_0: l2-cache0 { 50 - compatible = "cache"; 51 - cache-level = <2>; 52 - cache-unified; 53 - }; 54 - }; 55 - 56 - psci { 57 - compatible = "arm,psci-0.2", "arm,psci"; 58 - method = "smc"; 59 - cpu_suspend = <0x84000001>; 60 - cpu_off = <0x84000002>; 61 - cpu_on = <0x84000003>; 62 - }; 63 - 64 - gic: interrupt-controller@c0001000 { 65 - #interrupt-cells = <3>; 66 - compatible = "arm,gic-400"; 67 - interrupt-controller; 68 - reg = <0x0 0xc0001000 0x1000>, 69 - <0x0 0xc0002000 0x2000>, 70 - <0x0 0xc0004000 0x2000>, 71 - <0x0 0xc0006000 0x2000>; 72 - }; 73 - 74 - pmu { 75 - compatible = "arm,cortex-a53-pmu"; 76 - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 77 - <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 78 - <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 79 - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 80 - interrupt-affinity = <&cpu0>, 81 - <&cpu1>, 82 - <&cpu2>, 83 - <&cpu3>; 84 - }; 85 - 86 - timer { 87 - compatible = "arm,armv8-timer"; 88 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | 89 - IRQ_TYPE_LEVEL_LOW)>, 90 - <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | 91 - IRQ_TYPE_LEVEL_LOW)>, 92 - <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | 93 - IRQ_TYPE_LEVEL_LOW)>, 94 - <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | 95 - IRQ_TYPE_LEVEL_LOW)>; 96 - }; 97 - 98 - clk_bus: clk_bus { 99 - #clock-cells = <0>; 100 - 101 - compatible = "fixed-clock"; 102 - clock-frequency = <198000000>; 103 - clock-output-names = "BUSCLK"; 104 - }; 105 14 106 15 soc { 107 16 #address-cells = <2>; ··· 29 120 phy-mode = "rmii"; 30 121 /* Filled in by boot */ 31 122 mac-address = [ 00 00 00 00 00 00 ]; 32 - }; 33 - }; 34 - 35 - amba { 36 - #address-cells = <2>; 37 - #size-cells = <1>; 38 - 39 - compatible = "simple-bus"; 40 - interrupt-parent = <&gic>; 41 - ranges; 42 - 43 - timers: timer@fd100000 { 44 - compatible = "arm,sp804", "arm,primecell"; 45 - reg = <0x0 0xfd100000 0x1000>; 46 - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 47 - clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; 48 - clock-names = "timer0clk", "timer1clk", "apb_pclk"; 49 - }; 50 - wdog: watchdog@fd200000 { 51 - compatible = "arm,sp805", "arm,primecell"; 52 - reg = <0x0 0xfd200000 0x1000>; 53 - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 54 - clocks = <&clk_bus>, <&clk_bus>; 55 - clock-names = "wdog_clk", "apb_pclk"; 56 - }; 57 - uart0: serial@fe000000 { 58 - compatible = "arm,pl011", "arm,primecell"; 59 - reg = <0x0 0xfe000000 0x1000>; 60 - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 61 - clocks = <&clk_bus>; 62 - clock-names = "apb_pclk"; 63 - status = "disabled"; 64 - }; 65 - uart1: serial@fe100000 { 66 - compatible = "arm,pl011", "arm,primecell"; 67 - reg = <0x0 0xfe100000 0x1000>; 68 - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 69 - clocks = <&clk_bus>; 70 - clock-names = "apb_pclk"; 71 - status = "disabled"; 72 - }; 73 - uart2: serial@fe200000 { 74 - compatible = "arm,pl011", "arm,primecell"; 75 - reg = <0x0 0xfe200000 0x1000>; 76 - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 77 - clocks = <&clk_bus>; 78 - clock-names = "apb_pclk"; 79 - status = "disabled"; 80 - }; 81 - spi0: spi@fe800000 { 82 - compatible = "arm,pl022", "arm,primecell"; 83 - reg = <0x0 0xfe800000 0x1000>; 84 - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 85 - clocks = <&clk_bus>, <&clk_bus>; 86 - clock-names = "sspclk", "apb_pclk"; 87 - }; 88 - spi1: spi@fe900000 { 89 - compatible = "arm,pl022", "arm,primecell"; 90 - reg = <0x0 0xfe900000 0x1000>; 91 - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 92 - clocks = <&clk_bus>, <&clk_bus>; 93 - clock-names = "sspclk", "apb_pclk"; 94 - }; 95 - dmac0: dma-controller@c1128000 { 96 - compatible = "arm,pl330", "arm,primecell"; 97 - reg = <0x0 0xc1128000 0x1000>; 98 - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 99 - clocks = <&clk_bus>; 100 - clock-names = "apb_pclk"; 101 - #dma-cells = <1>; 102 - }; 103 - gpio0: gpio@fd400000 { 104 - #gpio-cells = <2>; 105 - compatible = "arm,pl061", "arm,primecell"; 106 - gpio-controller; 107 - reg = <0x0 0xfd400000 0x1000>; 108 - clocks = <&clk_bus>; 109 - clock-names = "apb_pclk"; 110 - status = "disabled"; 111 - }; 112 - gpio1: gpio@fd410000 { 113 - #gpio-cells = <2>; 114 - compatible = "arm,pl061", "arm,primecell"; 115 - gpio-controller; 116 - reg = <0x0 0xfd410000 0x1000>; 117 - clocks = <&clk_bus>; 118 - clock-names = "apb_pclk"; 119 - status = "disabled"; 120 - }; 121 - gpio2: gpio@fd420000 { 122 - #gpio-cells = <2>; 123 - compatible = "arm,pl061", "arm,primecell"; 124 - gpio-controller; 125 - reg = <0x0 0xfd420000 0x1000>; 126 - clocks = <&clk_bus>; 127 - clock-names = "apb_pclk"; 128 - status = "disabled"; 129 - }; 130 - gpio3: gpio@fd430000 { 131 - #gpio-cells = <2>; 132 - compatible = "arm,pl061", "arm,primecell"; 133 - gpio-controller; 134 - reg = <0x0 0xfd430000 0x1000>; 135 - clocks = <&clk_bus>; 136 - clock-names = "apb_pclk"; 137 - }; 138 - gpio4: gpio@fd440000 { 139 - #gpio-cells = <2>; 140 - compatible = "arm,pl061", "arm,primecell"; 141 - gpio-controller; 142 - reg = <0x0 0xfd440000 0x1000>; 143 - clocks = <&clk_bus>; 144 - clock-names = "apb_pclk"; 145 - status = "disabled"; 146 - }; 147 - gpio5: gpio@fd450000 { 148 - #gpio-cells = <2>; 149 - compatible = "arm,pl061", "arm,primecell"; 150 - gpio-controller; 151 - reg = <0x0 0xfd450000 0x1000>; 152 - clocks = <&clk_bus>; 153 - clock-names = "apb_pclk"; 154 - status = "disabled"; 155 - }; 156 - gpio6: gpio@fd460000 { 157 - #gpio-cells = <2>; 158 - compatible = "arm,pl061", "arm,primecell"; 159 - gpio-controller; 160 - reg = <0x0 0xfd460000 0x1000>; 161 - clocks = <&clk_bus>; 162 - clock-names = "apb_pclk"; 163 - status = "disabled"; 164 - }; 165 - gpio7: gpio@fd470000 { 166 - #gpio-cells = <2>; 167 - compatible = "arm,pl061", "arm,primecell"; 168 - gpio-controller; 169 - reg = <0x0 0xfd470000 0x1000>; 170 - clocks = <&clk_bus>; 171 - clock-names = "apb_pclk"; 172 - status = "disabled"; 173 - }; 174 - gpio8: gpio@fd480000 { 175 - #gpio-cells = <2>; 176 - compatible = "arm,pl061", "arm,primecell"; 177 - gpio-controller; 178 - reg = <0x0 0xfd480000 0x1000>; 179 - clocks = <&clk_bus>; 180 - clock-names = "apb_pclk"; 181 - status = "disabled"; 182 - }; 183 - gpio9: gpio@fd490000 { 184 - #gpio-cells = <2>; 185 - compatible = "arm,pl061", "arm,primecell"; 186 - gpio-controller; 187 - reg = <0x0 0xfd490000 0x1000>; 188 - clocks = <&clk_bus>; 189 - clock-names = "apb_pclk"; 190 - status = "disabled"; 191 - }; 192 - gpio10: gpio@fd4a0000 { 193 - #gpio-cells = <2>; 194 - compatible = "arm,pl061", "arm,primecell"; 195 - gpio-controller; 196 - reg = <0x0 0xfd4a0000 0x1000>; 197 - clocks = <&clk_bus>; 198 - clock-names = "apb_pclk"; 199 - status = "disabled"; 200 - }; 201 - gpio11: gpio@fd4b0000 { 202 - #gpio-cells = <2>; 203 - compatible = "arm,pl061", "arm,primecell"; 204 - gpio-controller; 205 - reg = <0x0 0xfd4b0000 0x1000>; 206 - clocks = <&clk_bus>; 207 - clock-names = "apb_pclk"; 208 - }; 209 - gpio12: gpio@fd4c0000 { 210 - #gpio-cells = <2>; 211 - compatible = "arm,pl061", "arm,primecell"; 212 - gpio-controller; 213 - reg = <0x0 0xfd4c0000 0x1000>; 214 - clocks = <&clk_bus>; 215 - clock-names = "apb_pclk"; 216 - status = "disabled"; 217 - }; 218 - gpio13: gpio@fd4d0000 { 219 - #gpio-cells = <2>; 220 - compatible = "arm,pl061", "arm,primecell"; 221 - gpio-controller; 222 - reg = <0x0 0xfd4d0000 0x1000>; 223 - clocks = <&clk_bus>; 224 - clock-names = "apb_pclk"; 225 - status = "disabled"; 226 - }; 227 - gpio14: gpio@fd4e0000 { 228 - #gpio-cells = <2>; 229 - compatible = "arm,pl061", "arm,primecell"; 230 - gpio-controller; 231 - reg = <0x0 0xfd4e0000 0x1000>; 232 - clocks = <&clk_bus>; 233 - clock-names = "apb_pclk"; 234 - status = "disabled"; 235 - }; 236 - gpio15: gpio@fd4f0000 { 237 - #gpio-cells = <2>; 238 - compatible = "arm,pl061", "arm,primecell"; 239 - gpio-controller; 240 - reg = <0x0 0xfd4f0000 0x1000>; 241 - clocks = <&clk_bus>; 242 - clock-names = "apb_pclk"; 243 - status = "disabled"; 244 - }; 245 - gpio16: gpio@fd500000 { 246 - #gpio-cells = <2>; 247 - compatible = "arm,pl061", "arm,primecell"; 248 - gpio-controller; 249 - reg = <0x0 0xfd500000 0x1000>; 250 - clocks = <&clk_bus>; 251 - clock-names = "apb_pclk"; 252 - status = "disabled"; 253 - }; 254 - gpio17: gpio@fd510000 { 255 - #gpio-cells = <2>; 256 - compatible = "arm,pl061", "arm,primecell"; 257 - gpio-controller; 258 - reg = <0x0 0xfd510000 0x1000>; 259 - clocks = <&clk_bus>; 260 - clock-names = "apb_pclk"; 261 123 }; 262 124 }; 263 125 };
+333
arch/arm64/boot/dts/lg/lg131x.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for lg131x SoCs 4 + * 5 + * Copyright (C) 2016, LG Electronics 6 + */ 7 + 8 + #include <dt-bindings/gpio/gpio.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 10 + 11 + / { 12 + #address-cells = <2>; 13 + #size-cells = <2>; 14 + 15 + interrupt-parent = <&gic>; 16 + 17 + cpus { 18 + #address-cells = <2>; 19 + #size-cells = <0>; 20 + 21 + cpu0: cpu@0 { 22 + device_type = "cpu"; 23 + compatible = "arm,cortex-a53"; 24 + reg = <0x0 0x0>; 25 + next-level-cache = <&L2_0>; 26 + }; 27 + cpu1: cpu@1 { 28 + device_type = "cpu"; 29 + compatible = "arm,cortex-a53"; 30 + reg = <0x0 0x1>; 31 + enable-method = "psci"; 32 + next-level-cache = <&L2_0>; 33 + }; 34 + cpu2: cpu@2 { 35 + device_type = "cpu"; 36 + compatible = "arm,cortex-a53"; 37 + reg = <0x0 0x2>; 38 + enable-method = "psci"; 39 + next-level-cache = <&L2_0>; 40 + }; 41 + cpu3: cpu@3 { 42 + device_type = "cpu"; 43 + compatible = "arm,cortex-a53"; 44 + reg = <0x0 0x3>; 45 + enable-method = "psci"; 46 + next-level-cache = <&L2_0>; 47 + }; 48 + L2_0: l2-cache0 { 49 + compatible = "cache"; 50 + cache-level = <2>; 51 + cache-unified; 52 + }; 53 + }; 54 + 55 + psci { 56 + compatible = "arm,psci-0.2", "arm,psci"; 57 + method = "smc"; 58 + cpu_suspend = <0x84000001>; 59 + cpu_off = <0x84000002>; 60 + cpu_on = <0x84000003>; 61 + }; 62 + 63 + gic: interrupt-controller@c0001000 { 64 + #interrupt-cells = <3>; 65 + compatible = "arm,gic-400"; 66 + interrupt-controller; 67 + reg = <0x0 0xc0001000 0x1000>, 68 + <0x0 0xc0002000 0x2000>, 69 + <0x0 0xc0004000 0x2000>, 70 + <0x0 0xc0006000 0x2000>; 71 + }; 72 + 73 + pmu { 74 + compatible = "arm,cortex-a53-pmu"; 75 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 76 + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 77 + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 78 + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 79 + interrupt-affinity = <&cpu0>, 80 + <&cpu1>, 81 + <&cpu2>, 82 + <&cpu3>; 83 + }; 84 + 85 + timer { 86 + compatible = "arm,armv8-timer"; 87 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | 88 + IRQ_TYPE_LEVEL_LOW)>, 89 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | 90 + IRQ_TYPE_LEVEL_LOW)>, 91 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | 92 + IRQ_TYPE_LEVEL_LOW)>, 93 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | 94 + IRQ_TYPE_LEVEL_LOW)>; 95 + }; 96 + 97 + clk_bus: clk_bus { 98 + #clock-cells = <0>; 99 + 100 + compatible = "fixed-clock"; 101 + clock-frequency = <198000000>; 102 + clock-output-names = "BUSCLK"; 103 + }; 104 + 105 + amba { 106 + #address-cells = <2>; 107 + #size-cells = <1>; 108 + 109 + compatible = "simple-bus"; 110 + interrupt-parent = <&gic>; 111 + ranges; 112 + 113 + timers: timer@fd100000 { 114 + compatible = "arm,sp804", "arm,primecell"; 115 + reg = <0x0 0xfd100000 0x1000>; 116 + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 117 + clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; 118 + clock-names = "timer0clk", "timer1clk", "apb_pclk"; 119 + }; 120 + wdog: watchdog@fd200000 { 121 + compatible = "arm,sp805", "arm,primecell"; 122 + reg = <0x0 0xfd200000 0x1000>; 123 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 124 + clocks = <&clk_bus>, <&clk_bus>; 125 + clock-names = "wdog_clk", "apb_pclk"; 126 + }; 127 + uart0: serial@fe000000 { 128 + compatible = "arm,pl011", "arm,primecell"; 129 + reg = <0x0 0xfe000000 0x1000>; 130 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 131 + clocks = <&clk_bus>; 132 + clock-names = "apb_pclk"; 133 + status = "disabled"; 134 + }; 135 + uart1: serial@fe100000 { 136 + compatible = "arm,pl011", "arm,primecell"; 137 + reg = <0x0 0xfe100000 0x1000>; 138 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 + clocks = <&clk_bus>; 140 + clock-names = "apb_pclk"; 141 + status = "disabled"; 142 + }; 143 + uart2: serial@fe200000 { 144 + compatible = "arm,pl011", "arm,primecell"; 145 + reg = <0x0 0xfe200000 0x1000>; 146 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 147 + clocks = <&clk_bus>; 148 + clock-names = "apb_pclk"; 149 + status = "disabled"; 150 + }; 151 + spi0: spi@fe800000 { 152 + compatible = "arm,pl022", "arm,primecell"; 153 + reg = <0x0 0xfe800000 0x1000>; 154 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 155 + clocks = <&clk_bus>, <&clk_bus>; 156 + clock-names = "sspclk", "apb_pclk"; 157 + }; 158 + spi1: spi@fe900000 { 159 + compatible = "arm,pl022", "arm,primecell"; 160 + reg = <0x0 0xfe900000 0x1000>; 161 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 162 + clocks = <&clk_bus>, <&clk_bus>; 163 + clock-names = "sspclk", "apb_pclk"; 164 + }; 165 + dmac0: dma-controller@c1128000 { 166 + compatible = "arm,pl330", "arm,primecell"; 167 + reg = <0x0 0xc1128000 0x1000>; 168 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 169 + clocks = <&clk_bus>; 170 + clock-names = "apb_pclk"; 171 + #dma-cells = <1>; 172 + }; 173 + gpio0: gpio@fd400000 { 174 + #gpio-cells = <2>; 175 + compatible = "arm,pl061", "arm,primecell"; 176 + gpio-controller; 177 + reg = <0x0 0xfd400000 0x1000>; 178 + clocks = <&clk_bus>; 179 + clock-names = "apb_pclk"; 180 + status = "disabled"; 181 + }; 182 + gpio1: gpio@fd410000 { 183 + #gpio-cells = <2>; 184 + compatible = "arm,pl061", "arm,primecell"; 185 + gpio-controller; 186 + reg = <0x0 0xfd410000 0x1000>; 187 + clocks = <&clk_bus>; 188 + clock-names = "apb_pclk"; 189 + status = "disabled"; 190 + }; 191 + gpio2: gpio@fd420000 { 192 + #gpio-cells = <2>; 193 + compatible = "arm,pl061", "arm,primecell"; 194 + gpio-controller; 195 + reg = <0x0 0xfd420000 0x1000>; 196 + clocks = <&clk_bus>; 197 + clock-names = "apb_pclk"; 198 + status = "disabled"; 199 + }; 200 + gpio3: gpio@fd430000 { 201 + #gpio-cells = <2>; 202 + compatible = "arm,pl061", "arm,primecell"; 203 + gpio-controller; 204 + reg = <0x0 0xfd430000 0x1000>; 205 + clocks = <&clk_bus>; 206 + clock-names = "apb_pclk"; 207 + }; 208 + gpio4: gpio@fd440000 { 209 + #gpio-cells = <2>; 210 + compatible = "arm,pl061", "arm,primecell"; 211 + gpio-controller; 212 + reg = <0x0 0xfd440000 0x1000>; 213 + clocks = <&clk_bus>; 214 + clock-names = "apb_pclk"; 215 + status = "disabled"; 216 + }; 217 + gpio5: gpio@fd450000 { 218 + #gpio-cells = <2>; 219 + compatible = "arm,pl061", "arm,primecell"; 220 + gpio-controller; 221 + reg = <0x0 0xfd450000 0x1000>; 222 + clocks = <&clk_bus>; 223 + clock-names = "apb_pclk"; 224 + status = "disabled"; 225 + }; 226 + gpio6: gpio@fd460000 { 227 + #gpio-cells = <2>; 228 + compatible = "arm,pl061", "arm,primecell"; 229 + gpio-controller; 230 + reg = <0x0 0xfd460000 0x1000>; 231 + clocks = <&clk_bus>; 232 + clock-names = "apb_pclk"; 233 + status = "disabled"; 234 + }; 235 + gpio7: gpio@fd470000 { 236 + #gpio-cells = <2>; 237 + compatible = "arm,pl061", "arm,primecell"; 238 + gpio-controller; 239 + reg = <0x0 0xfd470000 0x1000>; 240 + clocks = <&clk_bus>; 241 + clock-names = "apb_pclk"; 242 + status = "disabled"; 243 + }; 244 + gpio8: gpio@fd480000 { 245 + #gpio-cells = <2>; 246 + compatible = "arm,pl061", "arm,primecell"; 247 + gpio-controller; 248 + reg = <0x0 0xfd480000 0x1000>; 249 + clocks = <&clk_bus>; 250 + clock-names = "apb_pclk"; 251 + status = "disabled"; 252 + }; 253 + gpio9: gpio@fd490000 { 254 + #gpio-cells = <2>; 255 + compatible = "arm,pl061", "arm,primecell"; 256 + gpio-controller; 257 + reg = <0x0 0xfd490000 0x1000>; 258 + clocks = <&clk_bus>; 259 + clock-names = "apb_pclk"; 260 + status = "disabled"; 261 + }; 262 + gpio10: gpio@fd4a0000 { 263 + #gpio-cells = <2>; 264 + compatible = "arm,pl061", "arm,primecell"; 265 + gpio-controller; 266 + reg = <0x0 0xfd4a0000 0x1000>; 267 + clocks = <&clk_bus>; 268 + clock-names = "apb_pclk"; 269 + status = "disabled"; 270 + }; 271 + gpio11: gpio@fd4b0000 { 272 + #gpio-cells = <2>; 273 + compatible = "arm,pl061", "arm,primecell"; 274 + gpio-controller; 275 + reg = <0x0 0xfd4b0000 0x1000>; 276 + clocks = <&clk_bus>; 277 + clock-names = "apb_pclk"; 278 + }; 279 + gpio12: gpio@fd4c0000 { 280 + #gpio-cells = <2>; 281 + compatible = "arm,pl061", "arm,primecell"; 282 + gpio-controller; 283 + reg = <0x0 0xfd4c0000 0x1000>; 284 + clocks = <&clk_bus>; 285 + clock-names = "apb_pclk"; 286 + status = "disabled"; 287 + }; 288 + gpio13: gpio@fd4d0000 { 289 + #gpio-cells = <2>; 290 + compatible = "arm,pl061", "arm,primecell"; 291 + gpio-controller; 292 + reg = <0x0 0xfd4d0000 0x1000>; 293 + clocks = <&clk_bus>; 294 + clock-names = "apb_pclk"; 295 + status = "disabled"; 296 + }; 297 + gpio14: gpio@fd4e0000 { 298 + #gpio-cells = <2>; 299 + compatible = "arm,pl061", "arm,primecell"; 300 + gpio-controller; 301 + reg = <0x0 0xfd4e0000 0x1000>; 302 + clocks = <&clk_bus>; 303 + clock-names = "apb_pclk"; 304 + status = "disabled"; 305 + }; 306 + gpio15: gpio@fd4f0000 { 307 + #gpio-cells = <2>; 308 + compatible = "arm,pl061", "arm,primecell"; 309 + gpio-controller; 310 + reg = <0x0 0xfd4f0000 0x1000>; 311 + clocks = <&clk_bus>; 312 + clock-names = "apb_pclk"; 313 + status = "disabled"; 314 + }; 315 + gpio16: gpio@fd500000 { 316 + #gpio-cells = <2>; 317 + compatible = "arm,pl061", "arm,primecell"; 318 + gpio-controller; 319 + reg = <0x0 0xfd500000 0x1000>; 320 + clocks = <&clk_bus>; 321 + clock-names = "apb_pclk"; 322 + status = "disabled"; 323 + }; 324 + gpio17: gpio@fd510000 { 325 + #gpio-cells = <2>; 326 + compatible = "arm,pl061", "arm,primecell"; 327 + gpio-controller; 328 + reg = <0x0 0xfd510000 0x1000>; 329 + clocks = <&clk_bus>; 330 + clock-names = "apb_pclk"; 331 + }; 332 + }; 333 + };