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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: rockchip-pcie: Use regmap_read_poll_timeout() for PCIe reference clk PLL status
Replace open-coded phy PCIe reference clk PLL status polling with
regmap_read_poll_timeout API. This change simplifies the code without
altering functionality.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20241012071919.3726-4-linux.amoon@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Anand Moon
and committed by
Vinod Koul
cb0ba26a
e96397db
+15
-41
+15
-41
drivers/phy/rockchip/phy-rockchip-pcie.c
+15
-41
drivers/phy/rockchip/phy-rockchip-pcie.c
···
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struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
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int err = 0;
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u32 status;
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-
unsigned long timeout;
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mutex_lock(&rk_phy->pcie_mutex);
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···
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* so we make it large enough here. And we use loop-break
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* method which should not be harmful.
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*/
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-
timeout = jiffies + msecs_to_jiffies(1000);
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-
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err = -EINVAL;
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while (time_before(jiffies, timeout)) {
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&status);
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if (status & PHY_PLL_LOCKED) {
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dev_dbg(&phy->dev, "pll locked!\n");
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err = 0;
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break;
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}
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msleep(20);
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}
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-
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+
err = regmap_read_poll_timeout(rk_phy->reg_base,
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+
rk_phy->phy_data->pcie_status,
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+
status,
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+
status & PHY_PLL_LOCKED,
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+
200, 100000);
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if (err) {
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dev_err(&phy->dev, "pll lock timeout!\n");
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goto err_pll_lock;
···
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phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
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phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
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err = -ETIMEDOUT;
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while (time_before(jiffies, timeout)) {
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&status);
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if (!(status & PHY_PLL_OUTPUT)) {
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dev_dbg(&phy->dev, "pll output enable done!\n");
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err = 0;
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break;
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}
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msleep(20);
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}
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-
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+
err = regmap_read_poll_timeout(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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status,
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!(status & PHY_PLL_OUTPUT),
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+
200, 100000);
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if (err) {
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dev_err(&phy->dev, "pll output enable timeout!\n");
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goto err_pll_lock;
···
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HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT));
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err = -EINVAL;
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while (time_before(jiffies, timeout)) {
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regmap_read(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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&status);
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if (status & PHY_PLL_LOCKED) {
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dev_dbg(&phy->dev, "pll relocked!\n");
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err = 0;
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break;
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}
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msleep(20);
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}
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+
err = regmap_read_poll_timeout(rk_phy->reg_base,
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rk_phy->phy_data->pcie_status,
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status,
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status & PHY_PLL_LOCKED,
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+
200, 100000);
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if (err) {
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dev_err(&phy->dev, "pll relock timeout!\n");
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goto err_pll_lock;