Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20230208091340.124641-1-konrad.dybcio@linaro.org' into clk-for-6.4
Merge DT bindings through a dedicated topic branch, such that they can
be reused in changes being picked up through dt source branches.
+285
+58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
+58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM6115
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm6115-gpucc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: GPLL0 main branch source
27
+
- description: GPLL0 main div source
28
+
29
+
required:
30
+
- compatible
31
+
- clocks
32
+
33
+
allOf:
34
+
- $ref: qcom,gcc.yaml#
35
+
36
+
unevaluatedProperties: false
37
+
38
+
examples:
39
+
- |
40
+
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
41
+
#include <dt-bindings/clock/qcom,rpmcc.h>
42
+
43
+
soc {
44
+
#address-cells = <1>;
45
+
#size-cells = <1>;
46
+
47
+
clock-controller@5990000 {
48
+
compatible = "qcom,sm6115-gpucc";
49
+
reg = <0x05990000 0x9000>;
50
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
51
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
52
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
53
+
#clock-cells = <1>;
54
+
#reset-cells = <1>;
55
+
#power-domain-cells = <1>;
56
+
};
57
+
};
58
+
...
+64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
+64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM6125
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks and power domains on
14
+
Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm6125-gpucc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: GPLL0 main branch source
27
+
28
+
'#clock-cells':
29
+
const: 1
30
+
31
+
'#power-domain-cells':
32
+
const: 1
33
+
34
+
reg:
35
+
maxItems: 1
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- clocks
41
+
- '#clock-cells'
42
+
- '#power-domain-cells'
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
49
+
#include <dt-bindings/clock/qcom,rpmcc.h>
50
+
51
+
soc {
52
+
#address-cells = <1>;
53
+
#size-cells = <1>;
54
+
55
+
clock-controller@5990000 {
56
+
compatible = "qcom,sm6125-gpucc";
57
+
reg = <0x05990000 0x9000>;
58
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
59
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
60
+
#clock-cells = <1>;
61
+
#power-domain-cells = <1>;
62
+
};
63
+
};
64
+
...
+60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
+60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM6375
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm6375-gpucc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: GPLL0 main branch source
27
+
- description: GPLL0 div branch source
28
+
- description: SNoC DVM GFX source
29
+
30
+
required:
31
+
- compatible
32
+
- clocks
33
+
34
+
allOf:
35
+
- $ref: qcom,gcc.yaml#
36
+
37
+
unevaluatedProperties: false
38
+
39
+
examples:
40
+
- |
41
+
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
42
+
#include <dt-bindings/clock/qcom,rpmcc.h>
43
+
44
+
soc {
45
+
#address-cells = <2>;
46
+
#size-cells = <2>;
47
+
48
+
clock-controller@5990000 {
49
+
compatible = "qcom,sm6375-gpucc";
50
+
reg = <0 0x05990000 0 0x9000>;
51
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
52
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
53
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
54
+
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
55
+
#clock-cells = <1>;
56
+
#reset-cells = <1>;
57
+
#power-domain-cells = <1>;
58
+
};
59
+
};
60
+
...
+36
include/dt-bindings/clock/qcom,sm6115-gpucc.h
+36
include/dt-bindings/clock/qcom,sm6115-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
9
+
10
+
/* GPU_CC clocks */
11
+
#define GPU_CC_PLL0 0
12
+
#define GPU_CC_PLL0_OUT_AUX2 1
13
+
#define GPU_CC_PLL1 2
14
+
#define GPU_CC_PLL1_OUT_AUX 3
15
+
#define GPU_CC_AHB_CLK 4
16
+
#define GPU_CC_CRC_AHB_CLK 5
17
+
#define GPU_CC_CX_GFX3D_CLK 6
18
+
#define GPU_CC_CX_GMU_CLK 7
19
+
#define GPU_CC_CX_SNOC_DVM_CLK 8
20
+
#define GPU_CC_CXO_AON_CLK 9
21
+
#define GPU_CC_CXO_CLK 10
22
+
#define GPU_CC_GMU_CLK_SRC 11
23
+
#define GPU_CC_GX_CXO_CLK 12
24
+
#define GPU_CC_GX_GFX3D_CLK 13
25
+
#define GPU_CC_GX_GFX3D_CLK_SRC 14
26
+
#define GPU_CC_SLEEP_CLK 15
27
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
28
+
29
+
/* Resets */
30
+
#define GPU_GX_BCR 0
31
+
32
+
/* GDSCs */
33
+
#define GPU_CX_GDSC 0
34
+
#define GPU_GX_GDSC 1
35
+
36
+
#endif
+31
include/dt-bindings/clock/qcom,sm6125-gpucc.h
+31
include/dt-bindings/clock/qcom,sm6125-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
9
+
10
+
/* Clocks */
11
+
#define GPU_CC_PLL0_OUT_AUX2 0
12
+
#define GPU_CC_PLL1_OUT_AUX2 1
13
+
#define GPU_CC_CRC_AHB_CLK 2
14
+
#define GPU_CC_CX_APB_CLK 3
15
+
#define GPU_CC_CX_GFX3D_CLK 4
16
+
#define GPU_CC_CX_GMU_CLK 5
17
+
#define GPU_CC_CX_SNOC_DVM_CLK 6
18
+
#define GPU_CC_CXO_AON_CLK 7
19
+
#define GPU_CC_CXO_CLK 8
20
+
#define GPU_CC_GMU_CLK_SRC 9
21
+
#define GPU_CC_SLEEP_CLK 10
22
+
#define GPU_CC_GX_GFX3D_CLK 11
23
+
#define GPU_CC_GX_GFX3D_CLK_SRC 12
24
+
#define GPU_CC_AHB_CLK 13
25
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
26
+
27
+
/* GDSCs */
28
+
#define GPU_CX_GDSC 0
29
+
#define GPU_GX_GDSC 1
30
+
31
+
#endif
+36
include/dt-bindings/clock/qcom,sm6375-gpucc.h
+36
include/dt-bindings/clock/qcom,sm6375-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
9
+
10
+
/* GPU CC clocks */
11
+
#define GPU_CC_PLL0 0
12
+
#define GPU_CC_PLL1 1
13
+
#define GPU_CC_AHB_CLK 2
14
+
#define GPU_CC_CX_GFX3D_CLK 3
15
+
#define GPU_CC_CX_GFX3D_SLV_CLK 4
16
+
#define GPU_CC_CX_GMU_CLK 5
17
+
#define GPU_CC_CX_SNOC_DVM_CLK 6
18
+
#define GPU_CC_CXO_AON_CLK 7
19
+
#define GPU_CC_CXO_CLK 8
20
+
#define GPU_CC_GMU_CLK_SRC 9
21
+
#define GPU_CC_GX_CXO_CLK 10
22
+
#define GPU_CC_GX_GFX3D_CLK 11
23
+
#define GPU_CC_GX_GFX3D_CLK_SRC 12
24
+
#define GPU_CC_GX_GMU_CLK 13
25
+
#define GPU_CC_SLEEP_CLK 14
26
+
27
+
/* GDSCs */
28
+
#define GPU_CX_GDSC 0
29
+
#define GPU_GX_GDSC 1
30
+
31
+
/* Resets */
32
+
#define GPU_GX_BCR 0
33
+
#define GPU_ACD_BCR 1
34
+
#define GPU_GX_ACD_MISC_BCR 2
35
+
36
+
#endif