Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: DPP low mem pwr related adjustment -Part I
[why]
Default low pwr mem state get chagned.
SW needs to wake mem up first
also need to put back to LS again after use: will do in Part II.
Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Charlene Liu
and committed by
Alex Deucher
cb7a978c
8ae9d73b
+57
-50
+1
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
+1
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
+9
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
+9
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
···
41
41
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
42
42
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
43
43
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\
44
+
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
44
45
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\
45
46
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\
46
47
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
···
209
208
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
210
209
TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
211
210
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\
211
+
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, mask_sh),\
212
212
TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\
213
213
TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\
214
214
TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\
···
338
336
TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\
339
337
TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\
340
338
TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\
339
+
TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_DIS, mask_sh),\
340
+
TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_FORCE, mask_sh),\
341
+
TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_STATE, mask_sh),\
341
342
TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\
342
343
TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\
343
344
TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\
···
563
558
type ISHARP_DELTA_LUT_SELECT; \
564
559
type ISHARP_DELTA_LUT_SELECT_CURRENT; \
565
560
type ISHARP_DELTA_LUT_HOST_SELECT; \
561
+
type ISHARP_DELTA_LUT_MEM_PWR_DIS; \
562
+
type ISHARP_DELTA_LUT_MEM_PWR_FORCE;\
563
+
type ISHARP_DELTA_LUT_MEM_PWR_STATE;\
566
564
type ISHARP_DELTA_DATA; \
567
565
type ISHARP_DELTA_INDEX; \
568
566
type ISHARP_NLDELTA_SCLIP_EN_P; \
···
637
629
uint32_t DSCL_SC_MATRIX_C0C1; \
638
630
uint32_t DSCL_SC_MATRIX_C2C3; \
639
631
uint32_t ISHARP_MODE; \
632
+
uint32_t ISHARP_DELTA_LUT_MEM_PWR_CTRL; \
640
633
uint32_t ISHARP_NOISEDET_THRESHOLD; \
641
634
uint32_t ISHARP_NOISE_GAIN_PWL; \
642
635
uint32_t ISHARP_LBA_PWL_SEG0; \
+46
-50
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
+46
-50
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
···
966
966
ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);
967
967
968
968
/* Skip remaining register programming if ISHARP is disabled */
969
-
if (!scl_data->dscl_prog_data.isharp_en) {
970
-
PERF_TRACE();
971
-
return;
972
-
}
969
+
if (scl_data->dscl_prog_data.isharp_en) {
970
+
/* ISHARP_NOISEDET_THRESHOLD */
971
+
REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0,
972
+
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold,
973
+
ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);
973
974
974
-
/* ISHARP_NOISEDET_THRESHOLD */
975
-
REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0,
976
-
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold,
977
-
ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);
975
+
/* ISHARP_NOISE_GAIN_PWL */
976
+
REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0,
977
+
ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in,
978
+
ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in,
979
+
ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope);
978
980
979
-
/* ISHARP_NOISE_GAIN_PWL */
980
-
REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0,
981
-
ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in,
982
-
ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in,
983
-
ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope);
981
+
/* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */
982
+
REG_SET_3(ISHARP_LBA_PWL_SEG0, 0,
983
+
ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0],
984
+
ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0],
985
+
ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);
986
+
REG_SET_3(ISHARP_LBA_PWL_SEG1, 0,
987
+
ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1],
988
+
ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1],
989
+
ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);
990
+
REG_SET_3(ISHARP_LBA_PWL_SEG2, 0,
991
+
ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2],
992
+
ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2],
993
+
ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);
994
+
REG_SET_3(ISHARP_LBA_PWL_SEG3, 0,
995
+
ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3],
996
+
ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3],
997
+
ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);
998
+
REG_SET_3(ISHARP_LBA_PWL_SEG4, 0,
999
+
ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4],
1000
+
ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4],
1001
+
ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);
1002
+
REG_SET_2(ISHARP_LBA_PWL_SEG5, 0,
1003
+
ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5],
1004
+
ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);
984
1005
985
-
/* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */
986
-
REG_SET_3(ISHARP_LBA_PWL_SEG0, 0,
987
-
ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0],
988
-
ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0],
989
-
ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);
990
-
REG_SET_3(ISHARP_LBA_PWL_SEG1, 0,
991
-
ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1],
992
-
ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1],
993
-
ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);
994
-
REG_SET_3(ISHARP_LBA_PWL_SEG2, 0,
995
-
ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2],
996
-
ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2],
997
-
ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);
998
-
REG_SET_3(ISHARP_LBA_PWL_SEG3, 0,
999
-
ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3],
1000
-
ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3],
1001
-
ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);
1002
-
REG_SET_3(ISHARP_LBA_PWL_SEG4, 0,
1003
-
ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4],
1004
-
ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4],
1005
-
ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);
1006
-
REG_SET_2(ISHARP_LBA_PWL_SEG5, 0,
1007
-
ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5],
1008
-
ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);
1006
+
/* ISHARP_DELTA_LUT */
1007
+
if (!program_isharp_1dlut)
1008
+
dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);
1009
1009
1010
-
/* ISHARP_DELTA_LUT */
1011
-
if (!program_isharp_1dlut)
1012
-
dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);
1013
-
1014
-
/* ISHARP_NLDELTA_SOFT_CLIP */
1015
-
REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0,
1016
-
ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p,
1017
-
ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p,
1018
-
ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p,
1019
-
ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n,
1020
-
ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n,
1021
-
ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);
1010
+
/* ISHARP_NLDELTA_SOFT_CLIP */
1011
+
REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0,
1012
+
ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p,
1013
+
ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p,
1014
+
ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p,
1015
+
ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n,
1016
+
ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n,
1017
+
ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);
1022
1018
1023
1019
/* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */
1024
-
if (scl_data->dscl_prog_data.isharp_en) {
1025
1020
if (scl_data->dscl_prog_data.filter_blur_scale_v) {
1026
1021
dpp401_dscl_set_scaler_filter(
1027
1022
dpp, scl_data->taps.v_taps,
···
1032
1037
*bs_coeffs_updated = true;
1033
1038
}
1034
1039
}
1040
+
1035
1041
PERF_TRACE();
1036
1042
} // dpp401_dscl_program_isharp
1037
1043
/**
+1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
···
394
394
SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \
395
395
SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \
396
396
SRI_ARR(ISHARP_MODE, DSCL, id), \
397
+
SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \
397
398
SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \
398
399
SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \
399
400
SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \