Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.18-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley
- Replacement of __ASSEMBLY__ with __ASSEMBLER__ in header files (other
architectures have already merged this type of cleanup)
- The introduction of ioremap_wc() for RISC-V
- Cleanup of the RISC-V kprobes code to use mostly-extant macros rather
than open code
- A RISC-V kprobes unit test
- An architecture-specific endianness swap macro set implementation,
leveraging some dedicated RISC-V instructions for this purpose if
they are available
- The ability to identity and communicate to userspace the presence
of a MIPS P8700-specific ISA extension, and to leverage its
MIPS-specific PAUSE implementation in cpu_relax()
- Several other miscellaneous cleanups
* tag 'riscv-for-linus-6.18-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (39 commits)
riscv: errata: Fix the PAUSE Opcode for MIPS P8700
riscv: hwprobe: Document MIPS xmipsexectl vendor extension
riscv: hwprobe: Add MIPS vendor extension probing
riscv: Add xmipsexectl instructions
riscv: Add xmipsexectl as a vendor extension
dt-bindings: riscv: Add xmipsexectl ISA extension description
riscv: cpufeature: add validation for zfa, zfh and zfhmin
perf: riscv: skip empty batches in counter start
selftests: riscv: Add README for RISC-V KSelfTest
riscv: sbi: Switch to new sys-off handler API
riscv: Move vendor errata definitions to new header
RISC-V: ACPI: enable parsing the BGRT table
riscv: Enable ARCH_HAVE_NMI_SAFE_CMPXCHG
riscv: pi: use 'targets' instead of extra-y in Makefile
riscv: introduce asm/swab.h
riscv: mmap(): use unsigned offset type in riscv_sys_mmap
drivers/perf: riscv: Remove redundant ternary operators
riscv: mm: Use mmu-type from FDT to limit SATP mode
riscv: mm: Return intended SATP mode for noXlvl options
riscv: kprobes: Remove duplication of RV_EXTRACT_ITYPE_IMM
...
+1147
-530
+9
Documentation/arch/riscv/hwprobe.rst
+9
Documentation/arch/riscv/hwprobe.rst
···
327
327
* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are
328
328
not supported at all and will generate a misaligned address fault.
329
329
330
+
* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the
331
+
mips vendor extensions that are compatible with the
332
+
:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
333
+
334
+
* MIPS
335
+
336
+
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor
337
+
extension is supported in the MIPS ISA extensions spec.
338
+
330
339
* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the
331
340
thead vendor extensions that are compatible with the
332
341
:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+6
Documentation/devicetree/bindings/riscv/extensions.yaml
+6
Documentation/devicetree/bindings/riscv/extensions.yaml
···
662
662
Registers in the AX45MP datasheet.
663
663
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
664
664
665
+
# MIPS
666
+
- const: xmipsexectl
667
+
description:
668
+
The MIPS extension for execution control as documented in
669
+
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
670
+
665
671
# SiFive
666
672
- const: xsfvqmaccdod
667
673
description:
+1
arch/riscv/Kconfig
+1
arch/riscv/Kconfig
···
54
54
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
55
55
select ARCH_HAS_UBSAN
56
56
select ARCH_HAS_VDSO_ARCH_DATA if GENERIC_VDSO_DATA_STORE
57
+
select ARCH_HAVE_NMI_SAFE_CMPXCHG
57
58
select ARCH_KEEP_MEMBLOCK if ACPI
58
59
select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU
59
60
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
+23
arch/riscv/Kconfig.errata
+23
arch/riscv/Kconfig.errata
···
21
21
22
22
If you don't know what to do here, say "Y".
23
23
24
+
config ERRATA_MIPS
25
+
bool "MIPS errata"
26
+
depends on RISCV_ALTERNATIVE
27
+
help
28
+
All MIPS errata Kconfig depend on this Kconfig. Disabling
29
+
this Kconfig will disable all MIPS errata. Please say "Y"
30
+
here if your platform uses MIPS CPU cores.
31
+
32
+
Otherwise, please say "N" here to avoid unnecessary overhead.
33
+
34
+
config ERRATA_MIPS_P8700_PAUSE_OPCODE
35
+
bool "Fix the PAUSE Opcode for MIPS P8700"
36
+
depends on ERRATA_MIPS && 64BIT
37
+
default n
38
+
help
39
+
The RISCV MIPS P8700 uses a different opcode for PAUSE.
40
+
It is a 'hint' encoding of the SLLI instruction,
41
+
with rd=0, rs1=0 and imm=5. It will behave as a NOP
42
+
instruction if no additional behavior beyond that of
43
+
SLLI is implemented.
44
+
45
+
If you are not using the P8700 processor, say n.
46
+
24
47
config ERRATA_SIFIVE
25
48
bool "SiFive errata"
26
49
depends on RISCV_ALTERNATIVE
+13
arch/riscv/Kconfig.vendor
+13
arch/riscv/Kconfig.vendor
···
16
16
If you don't know what to do here, say Y.
17
17
endmenu
18
18
19
+
menu "MIPS"
20
+
config RISCV_ISA_VENDOR_EXT_MIPS
21
+
bool "MIPS vendor extension support"
22
+
select RISCV_ISA_VENDOR_EXT
23
+
default y
24
+
help
25
+
Say N here to disable detection of and support for all MIPS vendor
26
+
extensions. Without this option enabled, MIPS vendor extensions will
27
+
not be detected at boot and their presence not reported to userspace.
28
+
29
+
If you don't know what to do here, say Y.
30
+
endmenu
31
+
19
32
menu "SiFive"
20
33
config RISCV_ISA_VENDOR_EXT_SIFIVE
21
34
bool "SiFive vendor extension support"
+1
arch/riscv/errata/Makefile
+1
arch/riscv/errata/Makefile
+5
arch/riscv/errata/mips/Makefile
+5
arch/riscv/errata/mips/Makefile
+67
arch/riscv/errata/mips/errata.c
+67
arch/riscv/errata/mips/errata.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#include <linux/memory.h>
7
+
#include <linux/module.h>
8
+
#include <asm/text-patching.h>
9
+
#include <asm/alternative.h>
10
+
#include <asm/errata_list.h>
11
+
#include <asm/vendorid_list.h>
12
+
#include <asm/vendor_extensions.h>
13
+
#include <asm/vendor_extensions/mips.h>
14
+
15
+
static inline bool errata_probe_pause(void)
16
+
{
17
+
if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE))
18
+
return false;
19
+
20
+
if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL))
21
+
return false;
22
+
23
+
return true;
24
+
}
25
+
26
+
static u32 mips_errata_probe(void)
27
+
{
28
+
u32 cpu_req_errata = 0;
29
+
30
+
if (errata_probe_pause())
31
+
cpu_req_errata |= BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE);
32
+
33
+
return cpu_req_errata;
34
+
}
35
+
36
+
void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
37
+
unsigned long archid, unsigned long impid,
38
+
unsigned int stage)
39
+
{
40
+
struct alt_entry *alt;
41
+
u32 cpu_req_errata = mips_errata_probe();
42
+
u32 tmp;
43
+
44
+
BUILD_BUG_ON(ERRATA_MIPS_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
45
+
46
+
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
47
+
return;
48
+
49
+
for (alt = begin; alt < end; alt++) {
50
+
if (alt->vendor_id != MIPS_VENDOR_ID)
51
+
continue;
52
+
53
+
if (alt->patch_id >= ERRATA_MIPS_NUMBER) {
54
+
WARN(1, "MIPS errata id:%d not in kernel errata list\n",
55
+
alt->patch_id);
56
+
continue;
57
+
}
58
+
59
+
tmp = (1U << alt->patch_id);
60
+
if (cpu_req_errata && tmp) {
61
+
mutex_lock(&text_mutex);
62
+
patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
63
+
alt->alt_len);
64
+
mutex_unlock(&text_mutex);
65
+
}
66
+
}
67
+
}
+6
-6
arch/riscv/include/asm/alternative-macros.h
+6
-6
arch/riscv/include/asm/alternative-macros.h
···
4
4
5
5
#ifdef CONFIG_RISCV_ALTERNATIVE
6
6
7
-
#ifdef __ASSEMBLY__
7
+
#ifdef __ASSEMBLER__
8
8
9
9
.macro ALT_ENTRY oldptr newptr vendor_id patch_id new_len
10
10
.4byte \oldptr - .
···
53
53
#define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__
54
54
#define __ALTERNATIVE_CFG_2(...) ALTERNATIVE_CFG_2 __VA_ARGS__
55
55
56
-
#else /* !__ASSEMBLY__ */
56
+
#else /* !__ASSEMBLER__ */
57
57
58
58
#include <asm/asm.h>
59
59
#include <linux/stringify.h>
···
98
98
__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1) \
99
99
ALT_NEW_CONTENT(vendor_id_2, patch_id_2, enable_2, new_c_2)
100
100
101
-
#endif /* __ASSEMBLY__ */
101
+
#endif /* __ASSEMBLER__ */
102
102
103
103
#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, patch_id, CONFIG_k) \
104
104
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, patch_id, IS_ENABLED(CONFIG_k))
···
109
109
new_c_2, vendor_id_2, patch_id_2, IS_ENABLED(CONFIG_k_2))
110
110
111
111
#else /* CONFIG_RISCV_ALTERNATIVE */
112
-
#ifdef __ASSEMBLY__
112
+
#ifdef __ASSEMBLER__
113
113
114
114
.macro ALTERNATIVE_CFG old_c
115
115
\old_c
···
118
118
#define __ALTERNATIVE_CFG(old_c, ...) ALTERNATIVE_CFG old_c
119
119
#define __ALTERNATIVE_CFG_2(old_c, ...) ALTERNATIVE_CFG old_c
120
120
121
-
#else /* !__ASSEMBLY__ */
121
+
#else /* !__ASSEMBLER__ */
122
122
123
123
#define __ALTERNATIVE_CFG(old_c, ...) old_c "\n"
124
124
#define __ALTERNATIVE_CFG_2(old_c, ...) old_c "\n"
125
125
126
-
#endif /* __ASSEMBLY__ */
126
+
#endif /* __ASSEMBLER__ */
127
127
128
128
#define _ALTERNATIVE_CFG(old_c, ...) __ALTERNATIVE_CFG(old_c)
129
129
#define _ALTERNATIVE_CFG_2(old_c, ...) __ALTERNATIVE_CFG_2(old_c)
+4
-1
arch/riscv/include/asm/alternative.h
+4
-1
arch/riscv/include/asm/alternative.h
···
8
8
9
9
#include <asm/alternative-macros.h>
10
10
11
-
#ifndef __ASSEMBLY__
11
+
#ifndef __ASSEMBLER__
12
12
13
13
#ifdef CONFIG_RISCV_ALTERNATIVE
14
14
···
48
48
void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
49
49
unsigned long archid, unsigned long impid,
50
50
unsigned int stage);
51
+
void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
52
+
unsigned long archid, unsigned long impid,
53
+
unsigned int stage);
51
54
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
52
55
unsigned long archid, unsigned long impid,
53
56
unsigned int stage);
+3
-3
arch/riscv/include/asm/asm-extable.h
+3
-3
arch/riscv/include/asm/asm-extable.h
···
10
10
11
11
#ifdef CONFIG_MMU
12
12
13
-
#ifdef __ASSEMBLY__
13
+
#ifdef __ASSEMBLER__
14
14
15
15
#define __ASM_EXTABLE_RAW(insn, fixup, type, data) \
16
16
.pushsection __ex_table, "a"; \
···
25
25
__ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_FIXUP, 0)
26
26
.endm
27
27
28
-
#else /* __ASSEMBLY__ */
28
+
#else /* __ASSEMBLER__ */
29
29
30
30
#include <linux/bits.h>
31
31
#include <linux/stringify.h>
···
77
77
EX_DATA_REG(ADDR, addr) \
78
78
")")
79
79
80
-
#endif /* __ASSEMBLY__ */
80
+
#endif /* __ASSEMBLER__ */
81
81
82
82
#else /* CONFIG_MMU */
83
83
#define _ASM_EXTABLE_UACCESS_ERR(insn, fixup, err)
+5
-5
arch/riscv/include/asm/asm.h
+5
-5
arch/riscv/include/asm/asm.h
···
6
6
#ifndef _ASM_RISCV_ASM_H
7
7
#define _ASM_RISCV_ASM_H
8
8
9
-
#ifdef __ASSEMBLY__
9
+
#ifdef __ASSEMBLER__
10
10
#define __ASM_STR(x) x
11
11
#else
12
12
#define __ASM_STR(x) #x
···
30
30
#define SRLI __REG_SEL(srliw, srli)
31
31
32
32
#if __SIZEOF_POINTER__ == 8
33
-
#ifdef __ASSEMBLY__
33
+
#ifdef __ASSEMBLER__
34
34
#define RISCV_PTR .dword
35
35
#define RISCV_SZPTR 8
36
36
#define RISCV_LGPTR 3
···
40
40
#define RISCV_LGPTR "3"
41
41
#endif
42
42
#elif __SIZEOF_POINTER__ == 4
43
-
#ifdef __ASSEMBLY__
43
+
#ifdef __ASSEMBLER__
44
44
#define RISCV_PTR .word
45
45
#define RISCV_SZPTR 4
46
46
#define RISCV_LGPTR 2
···
69
69
#error "Unexpected __SIZEOF_SHORT__"
70
70
#endif
71
71
72
-
#ifdef __ASSEMBLY__
72
+
#ifdef __ASSEMBLER__
73
73
#include <asm/asm-offsets.h>
74
74
75
75
/* Common assembly source macros */
···
194
194
#define ASM_NOKPROBE(name)
195
195
#endif
196
196
197
-
#endif /* __ASSEMBLY__ */
197
+
#endif /* __ASSEMBLER__ */
198
198
199
199
#endif /* _ASM_RISCV_ASM_H */
+1
-1
arch/riscv/include/asm/assembler.h
+1
-1
arch/riscv/include/asm/assembler.h
+2
-2
arch/riscv/include/asm/barrier.h
+2
-2
arch/riscv/include/asm/barrier.h
···
10
10
#ifndef _ASM_RISCV_BARRIER_H
11
11
#define _ASM_RISCV_BARRIER_H
12
12
13
-
#ifndef __ASSEMBLY__
13
+
#ifndef __ASSEMBLER__
14
14
#include <asm/cmpxchg.h>
15
15
#include <asm/fence.h>
16
16
···
82
82
83
83
#include <asm-generic/barrier.h>
84
84
85
-
#endif /* __ASSEMBLY__ */
85
+
#endif /* __ASSEMBLER__ */
86
86
87
87
#endif /* _ASM_RISCV_BARRIER_H */
+2
-2
arch/riscv/include/asm/cache.h
+2
-2
arch/riscv/include/asm/cache.h
···
24
24
#define ARCH_SLAB_MINALIGN 16
25
25
#endif
26
26
27
-
#ifndef __ASSEMBLY__
27
+
#ifndef __ASSEMBLER__
28
28
29
29
extern int dma_cache_alignment;
30
30
#ifdef CONFIG_RISCV_DMA_NONCOHERENT
···
35
35
}
36
36
#endif
37
37
38
-
#endif /* __ASSEMBLY__ */
38
+
#endif /* __ASSEMBLER__ */
39
39
40
40
#endif /* _ASM_RISCV_CACHE_H */
+2
-1
arch/riscv/include/asm/cmpxchg.h
+2
-1
arch/riscv/include/asm/cmpxchg.h
···
14
14
#include <asm/insn-def.h>
15
15
#include <asm/cpufeature-macros.h>
16
16
#include <asm/processor.h>
17
+
#include <asm/errata_list.h>
17
18
18
19
#define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \
19
20
swap_append, r, p, n) \
···
439
438
return;
440
439
441
440
no_zawrs:
442
-
asm volatile(RISCV_PAUSE : : : "memory");
441
+
ALT_RISCV_PAUSE();
443
442
}
444
443
445
444
#define __cmpwait_relaxed(ptr, val) \
+1
-1
arch/riscv/include/asm/cpu_ops_sbi.h
+1
-1
arch/riscv/include/asm/cpu_ops_sbi.h
+2
-2
arch/riscv/include/asm/csr.h
+2
-2
arch/riscv/include/asm/csr.h
···
513
513
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
514
514
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
515
515
516
-
#ifndef __ASSEMBLY__
516
+
#ifndef __ASSEMBLER__
517
517
518
518
#define csr_swap(csr, val) \
519
519
({ \
···
575
575
: "memory"); \
576
576
})
577
577
578
-
#endif /* __ASSEMBLY__ */
578
+
#endif /* __ASSEMBLER__ */
579
579
580
580
#endif /* _ASM_RISCV_CSR_H */
+2
-2
arch/riscv/include/asm/current.h
+2
-2
arch/riscv/include/asm/current.h
···
13
13
#include <linux/bug.h>
14
14
#include <linux/compiler.h>
15
15
16
-
#ifndef __ASSEMBLY__
16
+
#ifndef __ASSEMBLER__
17
17
18
18
struct task_struct;
19
19
···
35
35
36
36
register unsigned long current_stack_pointer __asm__("sp");
37
37
38
-
#endif /* __ASSEMBLY__ */
38
+
#endif /* __ASSEMBLER__ */
39
39
40
40
#endif /* _ASM_RISCV_CURRENT_H */
+16
-22
arch/riscv/include/asm/errata_list.h
+16
-22
arch/riscv/include/asm/errata_list.h
···
5
5
#ifndef ASM_ERRATA_LIST_H
6
6
#define ASM_ERRATA_LIST_H
7
7
8
-
#include <asm/alternative.h>
9
8
#include <asm/csr.h>
10
9
#include <asm/insn-def.h>
11
10
#include <asm/hwcap.h>
12
11
#include <asm/vendorid_list.h>
12
+
#include <asm/errata_list_vendors.h>
13
+
#include <asm/vendor_extensions/mips.h>
13
14
14
-
#ifdef CONFIG_ERRATA_ANDES
15
-
#define ERRATA_ANDES_NO_IOCP 0
16
-
#define ERRATA_ANDES_NUMBER 1
17
-
#endif
18
-
19
-
#ifdef CONFIG_ERRATA_SIFIVE
20
-
#define ERRATA_SIFIVE_CIP_453 0
21
-
#define ERRATA_SIFIVE_CIP_1200 1
22
-
#define ERRATA_SIFIVE_NUMBER 2
23
-
#endif
24
-
25
-
#ifdef CONFIG_ERRATA_THEAD
26
-
#define ERRATA_THEAD_MAE 0
27
-
#define ERRATA_THEAD_PMU 1
28
-
#define ERRATA_THEAD_GHOSTWRITE 2
29
-
#define ERRATA_THEAD_NUMBER 3
30
-
#endif
31
-
32
-
#ifdef __ASSEMBLY__
15
+
#ifdef __ASSEMBLER__
33
16
34
17
#define ALT_INSN_FAULT(x) \
35
18
ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
···
25
42
__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
26
43
SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
27
44
CONFIG_ERRATA_SIFIVE_CIP_453)
28
-
#else /* !__ASSEMBLY__ */
45
+
#else /* !__ASSEMBLER__ */
29
46
30
47
#define ALT_SFENCE_VMA_ASID(asid) \
31
48
asm(ALTERNATIVE("sfence.vma x0, %0", "sfence.vma", SIFIVE_VENDOR_ID, \
···
41
58
asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID, \
42
59
ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
43
60
: : "r" (addr), "r" (asid) : "memory")
61
+
62
+
#define ALT_RISCV_PAUSE() \
63
+
asm(ALTERNATIVE( \
64
+
RISCV_PAUSE, /* Original RISC‑V pause insn */ \
65
+
MIPS_PAUSE, /* Replacement for MIPS P8700 */ \
66
+
MIPS_VENDOR_ID, /* Vendor ID to match */ \
67
+
ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */ \
68
+
CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE) \
69
+
: /* no outputs */ \
70
+
: /* no inputs */ \
71
+
: "memory")
44
72
45
73
/*
46
74
* _val is marked as "will be overwritten", so need to set it to 0
···
117
123
#define THEAD_C9XX_RV_IRQ_PMU 17
118
124
#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
119
125
120
-
#endif /* __ASSEMBLY__ */
126
+
#endif /* __ASSEMBLER__ */
121
127
122
128
#endif
+29
arch/riscv/include/asm/errata_list_vendors.h
+29
arch/riscv/include/asm/errata_list_vendors.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
3
+
#ifndef ASM_ERRATA_LIST_VENDORS_H
4
+
#define ASM_ERRATA_LIST_VENDORS_H
5
+
6
+
#ifdef CONFIG_ERRATA_ANDES
7
+
#define ERRATA_ANDES_NO_IOCP 0
8
+
#define ERRATA_ANDES_NUMBER 1
9
+
#endif
10
+
11
+
#ifdef CONFIG_ERRATA_SIFIVE
12
+
#define ERRATA_SIFIVE_CIP_453 0
13
+
#define ERRATA_SIFIVE_CIP_1200 1
14
+
#define ERRATA_SIFIVE_NUMBER 2
15
+
#endif
16
+
17
+
#ifdef CONFIG_ERRATA_THEAD
18
+
#define ERRATA_THEAD_MAE 0
19
+
#define ERRATA_THEAD_PMU 1
20
+
#define ERRATA_THEAD_GHOSTWRITE 2
21
+
#define ERRATA_THEAD_NUMBER 3
22
+
#endif
23
+
24
+
#ifdef CONFIG_ERRATA_MIPS
25
+
#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0
26
+
#define ERRATA_MIPS_NUMBER 1
27
+
#endif
28
+
29
+
#endif /* ASM_ERRATA_LIST_VENDORS_H */
+3
-3
arch/riscv/include/asm/ftrace.h
+3
-3
arch/riscv/include/asm/ftrace.h
···
13
13
#endif
14
14
15
15
#define ARCH_SUPPORTS_FTRACE_OPS 1
16
-
#ifndef __ASSEMBLY__
16
+
#ifndef __ASSEMBLER__
17
17
18
18
extern void *return_address(unsigned int level);
19
19
···
112
112
#define MCOUNT_JALR_SIZE 4
113
113
#define MCOUNT_NOP4_SIZE 4
114
114
115
-
#ifndef __ASSEMBLY__
115
+
#ifndef __ASSEMBLER__
116
116
struct dyn_ftrace;
117
117
int ftrace_init_nop(struct module *mod, struct dyn_ftrace *rec);
118
118
#define ftrace_init_nop ftrace_init_nop
···
235
235
236
236
#endif /* CONFIG_DYNAMIC_FTRACE_WITH_ARGS */
237
237
238
-
#endif /* __ASSEMBLY__ */
238
+
#endif /* __ASSEMBLER__ */
239
239
240
240
#endif /* CONFIG_DYNAMIC_FTRACE */
241
241
+3
-3
arch/riscv/include/asm/gpr-num.h
+3
-3
arch/riscv/include/asm/gpr-num.h
···
2
2
#ifndef __ASM_GPR_NUM_H
3
3
#define __ASM_GPR_NUM_H
4
4
5
-
#ifdef __ASSEMBLY__
5
+
#ifdef __ASSEMBLER__
6
6
7
7
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
8
8
.equ .L__gpr_num_x\num, \num
···
41
41
.equ .L__gpr_num_t5, 30
42
42
.equ .L__gpr_num_t6, 31
43
43
44
-
#else /* __ASSEMBLY__ */
44
+
#else /* __ASSEMBLER__ */
45
45
46
46
#define __DEFINE_ASM_GPR_NUMS \
47
47
" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \
···
80
80
" .equ .L__gpr_num_t5, 30\n" \
81
81
" .equ .L__gpr_num_t6, 31\n"
82
82
83
-
#endif /* __ASSEMBLY__ */
83
+
#endif /* __ASSEMBLER__ */
84
84
85
85
#endif /* __ASM_GPR_NUM_H */
+2
-1
arch/riscv/include/asm/hwprobe.h
+2
-1
arch/riscv/include/asm/hwprobe.h
···
8
8
9
9
#include <uapi/asm/hwprobe.h>
10
10
11
-
#define RISCV_HWPROBE_MAX_KEY 13
11
+
#define RISCV_HWPROBE_MAX_KEY 14
12
12
13
13
static inline bool riscv_hwprobe_key_is_valid(__s64 key)
14
14
{
···
22
22
case RISCV_HWPROBE_KEY_IMA_EXT_0:
23
23
case RISCV_HWPROBE_KEY_CPUPERF_0:
24
24
case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
25
+
case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
25
26
case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
26
27
return true;
27
28
}
+2
-2
arch/riscv/include/asm/image.h
+2
-2
arch/riscv/include/asm/image.h
···
29
29
#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
30
30
RISCV_HEADER_VERSION_MINOR)
31
31
32
-
#ifndef __ASSEMBLY__
32
+
#ifndef __ASSEMBLER__
33
33
#define riscv_image_flag_field(flags, field)\
34
34
(((flags) >> field##_SHIFT) & field##_MASK)
35
35
/**
···
63
63
u32 magic2;
64
64
u32 res3;
65
65
};
66
-
#endif /* __ASSEMBLY__ */
66
+
#endif /* __ASSEMBLER__ */
67
67
#endif /* _ASM_RISCV_IMAGE_H */
+4
-4
arch/riscv/include/asm/insn-def.h
+4
-4
arch/riscv/include/asm/insn-def.h
···
25
25
#define INSN_S_SIMM5_SHIFT 7
26
26
#define INSN_S_OPCODE_SHIFT 0
27
27
28
-
#ifdef __ASSEMBLY__
28
+
#ifdef __ASSEMBLER__
29
29
30
30
#ifdef CONFIG_AS_HAS_INSN
31
31
···
77
77
#define __INSN_I(...) insn_i __VA_ARGS__
78
78
#define __INSN_S(...) insn_s __VA_ARGS__
79
79
80
-
#else /* ! __ASSEMBLY__ */
80
+
#else /* ! __ASSEMBLER__ */
81
81
82
82
#ifdef CONFIG_AS_HAS_INSN
83
83
···
153
153
154
154
#endif
155
155
156
-
#endif /* ! __ASSEMBLY__ */
156
+
#endif /* ! __ASSEMBLER__ */
157
157
158
158
#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \
159
159
__INSN_R(RV_##opcode, RV_##func3, RV_##func7, \
···
263
263
264
264
#define RISCV_INSN_NOP4 _AC(0x00000013, U)
265
265
266
-
#ifndef __ASSEMBLY__
266
+
#ifndef __ASSEMBLER__
267
267
#define nop() __asm__ __volatile__ ("nop")
268
268
#define __nops(n) ".rept " #n "\nnop\n.endr\n"
269
269
#define nops(n) __asm__ __volatile__ (__nops(n))
+194
-22
arch/riscv/include/asm/insn.h
+194
-22
arch/riscv/include/asm/insn.h
···
64
64
#define RVG_RS2_OPOFF 20
65
65
#define RVG_RD_OPOFF 7
66
66
#define RVG_RS1_MASK GENMASK(4, 0)
67
+
#define RVG_RS2_MASK GENMASK(4, 0)
67
68
#define RVG_RD_MASK GENMASK(4, 0)
68
69
69
70
/* The bit field of immediate value in RVC J instruction */
···
287
286
(code & RVC_INSN_J_RS1_MASK) != 0;
288
287
}
289
288
290
-
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
291
-
#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
292
-
#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
293
-
#define RVC_X(X, s, mask) RV_X(X, s, mask)
289
+
#define INSN_MATCH_LB 0x3
290
+
#define INSN_MASK_LB 0x707f
291
+
#define INSN_MATCH_LH 0x1003
292
+
#define INSN_MASK_LH 0x707f
293
+
#define INSN_MATCH_LW 0x2003
294
+
#define INSN_MASK_LW 0x707f
295
+
#define INSN_MATCH_LD 0x3003
296
+
#define INSN_MASK_LD 0x707f
297
+
#define INSN_MATCH_LBU 0x4003
298
+
#define INSN_MASK_LBU 0x707f
299
+
#define INSN_MATCH_LHU 0x5003
300
+
#define INSN_MASK_LHU 0x707f
301
+
#define INSN_MATCH_LWU 0x6003
302
+
#define INSN_MASK_LWU 0x707f
303
+
#define INSN_MATCH_SB 0x23
304
+
#define INSN_MASK_SB 0x707f
305
+
#define INSN_MATCH_SH 0x1023
306
+
#define INSN_MASK_SH 0x707f
307
+
#define INSN_MATCH_SW 0x2023
308
+
#define INSN_MASK_SW 0x707f
309
+
#define INSN_MATCH_SD 0x3023
310
+
#define INSN_MASK_SD 0x707f
311
+
312
+
#define INSN_MATCH_C_LD 0x6000
313
+
#define INSN_MASK_C_LD 0xe003
314
+
#define INSN_MATCH_C_SD 0xe000
315
+
#define INSN_MASK_C_SD 0xe003
316
+
#define INSN_MATCH_C_LW 0x4000
317
+
#define INSN_MASK_C_LW 0xe003
318
+
#define INSN_MATCH_C_SW 0xc000
319
+
#define INSN_MASK_C_SW 0xe003
320
+
#define INSN_MATCH_C_LDSP 0x6002
321
+
#define INSN_MASK_C_LDSP 0xe003
322
+
#define INSN_MATCH_C_SDSP 0xe002
323
+
#define INSN_MASK_C_SDSP 0xe003
324
+
#define INSN_MATCH_C_LWSP 0x4002
325
+
#define INSN_MASK_C_LWSP 0xe003
326
+
#define INSN_MATCH_C_SWSP 0xc002
327
+
#define INSN_MASK_C_SWSP 0xe003
328
+
329
+
#define INSN_OPCODE_MASK 0x007c
330
+
#define INSN_OPCODE_SHIFT 2
331
+
#define INSN_OPCODE_SYSTEM 28
332
+
333
+
#define INSN_MASK_WFI 0xffffffff
334
+
#define INSN_MATCH_WFI 0x10500073
335
+
336
+
#define INSN_MASK_WRS 0xffffffff
337
+
#define INSN_MATCH_WRS 0x00d00073
338
+
339
+
#define INSN_MATCH_CSRRW 0x1073
340
+
#define INSN_MASK_CSRRW 0x707f
341
+
#define INSN_MATCH_CSRRS 0x2073
342
+
#define INSN_MASK_CSRRS 0x707f
343
+
#define INSN_MATCH_CSRRC 0x3073
344
+
#define INSN_MASK_CSRRC 0x707f
345
+
#define INSN_MATCH_CSRRWI 0x5073
346
+
#define INSN_MASK_CSRRWI 0x707f
347
+
#define INSN_MATCH_CSRRSI 0x6073
348
+
#define INSN_MASK_CSRRSI 0x707f
349
+
#define INSN_MATCH_CSRRCI 0x7073
350
+
#define INSN_MASK_CSRRCI 0x707f
351
+
352
+
#define INSN_MATCH_FLW 0x2007
353
+
#define INSN_MASK_FLW 0x707f
354
+
#define INSN_MATCH_FLD 0x3007
355
+
#define INSN_MASK_FLD 0x707f
356
+
#define INSN_MATCH_FLQ 0x4007
357
+
#define INSN_MASK_FLQ 0x707f
358
+
#define INSN_MATCH_FSW 0x2027
359
+
#define INSN_MASK_FSW 0x707f
360
+
#define INSN_MATCH_FSD 0x3027
361
+
#define INSN_MASK_FSD 0x707f
362
+
#define INSN_MATCH_FSQ 0x4027
363
+
#define INSN_MASK_FSQ 0x707f
364
+
365
+
#define INSN_MATCH_C_FLD 0x2000
366
+
#define INSN_MASK_C_FLD 0xe003
367
+
#define INSN_MATCH_C_FLW 0x6000
368
+
#define INSN_MASK_C_FLW 0xe003
369
+
#define INSN_MATCH_C_FSD 0xa000
370
+
#define INSN_MASK_C_FSD 0xe003
371
+
#define INSN_MATCH_C_FSW 0xe000
372
+
#define INSN_MASK_C_FSW 0xe003
373
+
#define INSN_MATCH_C_FLDSP 0x2002
374
+
#define INSN_MASK_C_FLDSP 0xe003
375
+
#define INSN_MATCH_C_FSDSP 0xa002
376
+
#define INSN_MASK_C_FSDSP 0xe003
377
+
#define INSN_MATCH_C_FLWSP 0x6002
378
+
#define INSN_MASK_C_FLWSP 0xe003
379
+
#define INSN_MATCH_C_FSWSP 0xe002
380
+
#define INSN_MASK_C_FSWSP 0xe003
381
+
382
+
#define INSN_MATCH_C_LHU 0x8400
383
+
#define INSN_MASK_C_LHU 0xfc43
384
+
#define INSN_MATCH_C_LH 0x8440
385
+
#define INSN_MASK_C_LH 0xfc43
386
+
#define INSN_MATCH_C_SH 0x8c00
387
+
#define INSN_MASK_C_SH 0xfc43
388
+
389
+
#define INSN_16BIT_MASK 0x3
390
+
#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
391
+
#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
392
+
393
+
#define SHIFT_RIGHT(x, y) \
394
+
((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
395
+
396
+
#define REG_MASK \
397
+
((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
398
+
399
+
#define REG_OFFSET(insn, pos) \
400
+
(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
401
+
402
+
#define REG_PTR(insn, pos, regs) \
403
+
((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
404
+
405
+
#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
406
+
#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
407
+
#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
408
+
#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
409
+
#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
410
+
#define GET_SP(regs) (*REG_PTR(2, 0, regs))
411
+
#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
412
+
#define IMM_I(insn) ((s32)(insn) >> 20)
413
+
#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
414
+
(s32)(((insn) >> 7) & 0x1f))
415
+
416
+
#define SH_RD 7
417
+
#define SH_RS1 15
418
+
#define SH_RS2 20
419
+
#define SH_RS2C 2
420
+
#define MASK_RX 0x1f
421
+
422
+
#if defined(CONFIG_64BIT)
423
+
#define LOG_REGBYTES 3
424
+
#else
425
+
#define LOG_REGBYTES 2
426
+
#endif
427
+
428
+
#define MASK_FUNCT3 0x7000
429
+
430
+
#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
431
+
432
+
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
433
+
#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
434
+
#define RV_X_MASK(X, s, mask) (((X) >> (s)) & (mask))
435
+
#define RV_X(X, s, n) RV_X_MASK(X, s, ((1 << (n)) - 1))
436
+
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
437
+
(RV_X(x, 10, 3) << 3) | \
438
+
(RV_X(x, 5, 1) << 6))
439
+
#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
440
+
(RV_X(x, 5, 2) << 6))
441
+
#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
442
+
(RV_X(x, 12, 1) << 5) | \
443
+
(RV_X(x, 2, 2) << 6))
444
+
#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
445
+
(RV_X(x, 12, 1) << 5) | \
446
+
(RV_X(x, 2, 3) << 6))
447
+
#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
448
+
(RV_X(x, 7, 2) << 6))
449
+
#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
450
+
(RV_X(x, 7, 3) << 6))
451
+
#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
452
+
#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
453
+
#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
454
+
#define RVC_X(X, s, mask) RV_X_MASK(X, s, mask)
455
+
456
+
#define RV_EXTRACT_FUNCT3(x) \
457
+
({typeof(x) x_ = (x); \
458
+
(RV_X_MASK(x_, RV_INSN_FUNCT3_OPOFF, \
459
+
RV_INSN_FUNCT3_MASK >> RV_INSN_FUNCT3_OPOFF)); })
294
460
295
461
#define RV_EXTRACT_RS1_REG(x) \
296
462
({typeof(x) x_ = (x); \
297
-
(RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
463
+
(RV_X_MASK(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
464
+
465
+
#define RV_EXTRACT_RS2_REG(x) \
466
+
({typeof(x) x_ = (x); \
467
+
(RV_X_MASK(x_, RVG_RS2_OPOFF, RVG_RS2_MASK)); })
298
468
299
469
#define RV_EXTRACT_RD_REG(x) \
300
470
({typeof(x) x_ = (x); \
301
-
(RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
471
+
(RV_X_MASK(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
302
472
303
473
#define RV_EXTRACT_UTYPE_IMM(x) \
304
474
({typeof(x) x_ = (x); \
305
-
(RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
475
+
(RV_X_MASK(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
306
476
307
477
#define RV_EXTRACT_JTYPE_IMM(x) \
308
478
({typeof(x) x_ = (x); \
309
-
(RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
310
-
(RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
311
-
(RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
479
+
(RV_X_MASK(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
480
+
(RV_X_MASK(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
481
+
(RV_X_MASK(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
312
482
(RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
313
483
314
484
#define RV_EXTRACT_ITYPE_IMM(x) \
315
485
({typeof(x) x_ = (x); \
316
-
(RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
486
+
(RV_X_MASK(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
317
487
(RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
318
488
319
489
#define RV_EXTRACT_BTYPE_IMM(x) \
320
490
({typeof(x) x_ = (x); \
321
-
(RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
322
-
(RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
323
-
(RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
491
+
(RV_X_MASK(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
492
+
(RV_X_MASK(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
493
+
(RV_X_MASK(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
324
494
(RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
325
495
326
496
#define RVC_EXTRACT_C2_RS1_REG(x) \
327
497
({typeof(x) x_ = (x); \
328
-
(RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
498
+
(RV_X_MASK(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
329
499
330
500
#define RVC_EXTRACT_JTYPE_IMM(x) \
331
501
({typeof(x) x_ = (x); \
···
518
346
(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
519
347
520
348
#define RVG_EXTRACT_SYSTEM_CSR(x) \
521
-
({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
349
+
({typeof(x) x_ = (x); RV_X_MASK(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
522
350
523
351
#define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \
524
-
({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
352
+
({typeof(x) x_ = (x); RV_X_MASK(x_, RVFDQ_FL_FS_WIDTH_OFF, \
525
353
RVFDQ_FL_FS_WIDTH_MASK); })
526
354
527
-
#define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
355
+
#define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
528
356
529
357
/*
530
358
* Get the immediate from a J-type instruction.
···
547
375
{
548
376
/* drop the old IMMs, all jal IMM bits sit at 31:12 */
549
377
*insn &= ~GENMASK(31, 12);
550
-
*insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
551
-
(RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
552
-
(RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
553
-
(RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
378
+
*insn |= (RV_X_MASK(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
379
+
(RV_X_MASK(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
380
+
(RV_X_MASK(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
381
+
(RV_X_MASK(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
554
382
}
555
383
556
384
/*
+4
arch/riscv/include/asm/io.h
+4
arch/riscv/include/asm/io.h
+2
-2
arch/riscv/include/asm/jump_label.h
+2
-2
arch/riscv/include/asm/jump_label.h
···
7
7
#ifndef __ASM_JUMP_LABEL_H
8
8
#define __ASM_JUMP_LABEL_H
9
9
10
-
#ifndef __ASSEMBLY__
10
+
#ifndef __ASSEMBLER__
11
11
12
12
#include <linux/types.h>
13
13
#include <asm/asm.h>
···
66
66
return true;
67
67
}
68
68
69
-
#endif /* __ASSEMBLY__ */
69
+
#endif /* __ASSEMBLER__ */
70
70
#endif /* __ASM_JUMP_LABEL_H */
+1
-1
arch/riscv/include/asm/kasan.h
+1
-1
arch/riscv/include/asm/kasan.h
+2
-2
arch/riscv/include/asm/kgdb.h
+2
-2
arch/riscv/include/asm/kgdb.h
···
17
17
#define BREAK_INSTR_SIZE 4
18
18
#endif
19
19
20
-
#ifndef __ASSEMBLY__
20
+
#ifndef __ASSEMBLER__
21
21
22
22
void arch_kgdb_breakpoint(void);
23
23
extern unsigned long kgdb_compiled_break;
24
24
25
-
#endif /* !__ASSEMBLY__ */
25
+
#endif /* !__ASSEMBLER__ */
26
26
27
27
#define DBG_REG_ZERO "zero"
28
28
#define DBG_REG_RA "ra"
+2
-2
arch/riscv/include/asm/mmu.h
+2
-2
arch/riscv/include/asm/mmu.h
···
7
7
#ifndef _ASM_RISCV_MMU_H
8
8
#define _ASM_RISCV_MMU_H
9
9
10
-
#ifndef __ASSEMBLY__
10
+
#ifndef __ASSEMBLER__
11
11
12
12
typedef struct {
13
13
#ifndef CONFIG_MMU
···
40
40
41
41
void __meminit create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz,
42
42
pgprot_t prot);
43
-
#endif /* __ASSEMBLY__ */
43
+
#endif /* __ASSEMBLER__ */
44
44
45
45
#endif /* _ASM_RISCV_MMU_H */
+2
-2
arch/riscv/include/asm/page.h
+2
-2
arch/riscv/include/asm/page.h
···
41
41
#define PAGE_OFFSET ((unsigned long)phys_ram_base)
42
42
#endif /* CONFIG_MMU */
43
43
44
-
#ifndef __ASSEMBLY__
44
+
#ifndef __ASSEMBLER__
45
45
46
46
#ifdef CONFIG_RISCV_ISA_ZICBOZ
47
47
void clear_page(void *page);
···
199
199
return __va(pfn << PAGE_SHIFT);
200
200
}
201
201
202
-
#endif /* __ASSEMBLY__ */
202
+
#endif /* __ASSEMBLER__ */
203
203
204
204
#define virt_addr_valid(vaddr) ({ \
205
205
unsigned long _addr = (unsigned long)vaddr; \
+3
-2
arch/riscv/include/asm/pgtable.h
+3
-2
arch/riscv/include/asm/pgtable.h
···
111
111
112
112
#endif
113
113
114
-
#ifndef __ASSEMBLY__
114
+
#ifndef __ASSEMBLER__
115
115
116
116
#include <asm/page.h>
117
117
#include <asm/tlbflush.h>
···
203
203
204
204
#define PAGE_TABLE __pgprot(_PAGE_TABLE)
205
205
206
+
#define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)
206
207
#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
207
208
#define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP)
208
209
···
1136
1135
WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
1137
1136
set_pgd(pgdp, pgd); \
1138
1137
})
1139
-
#endif /* !__ASSEMBLY__ */
1138
+
#endif /* !__ASSEMBLER__ */
1140
1139
1141
1140
#endif /* _ASM_RISCV_PGTABLE_H */
+2
-2
arch/riscv/include/asm/processor.h
+2
-2
arch/riscv/include/asm/processor.h
···
54
54
#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
55
55
#endif
56
56
57
-
#ifndef __ASSEMBLY__
57
+
#ifndef __ASSEMBLER__
58
58
59
59
struct task_struct;
60
60
struct pt_regs;
···
215
215
#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
216
216
#endif
217
217
218
-
#endif /* __ASSEMBLY__ */
218
+
#endif /* __ASSEMBLER__ */
219
219
220
220
#endif /* _ASM_RISCV_PROCESSOR_H */
+2
-2
arch/riscv/include/asm/ptrace.h
+2
-2
arch/riscv/include/asm/ptrace.h
···
10
10
#include <asm/csr.h>
11
11
#include <linux/compiler.h>
12
12
13
-
#ifndef __ASSEMBLY__
13
+
#ifndef __ASSEMBLER__
14
14
15
15
struct pt_regs {
16
16
unsigned long epc;
···
180
180
return !(regs->status & SR_PIE);
181
181
}
182
182
183
-
#endif /* __ASSEMBLY__ */
183
+
#endif /* __ASSEMBLER__ */
184
184
185
185
#endif /* _ASM_RISCV_PTRACE_H */
+2
-2
arch/riscv/include/asm/scs.h
+2
-2
arch/riscv/include/asm/scs.h
···
2
2
#ifndef _ASM_SCS_H
3
3
#define _ASM_SCS_H
4
4
5
-
#ifdef __ASSEMBLY__
5
+
#ifdef __ASSEMBLER__
6
6
#include <asm/asm-offsets.h>
7
7
8
8
#ifdef CONFIG_SHADOW_CALL_STACK
···
49
49
.endm
50
50
51
51
#endif /* CONFIG_SHADOW_CALL_STACK */
52
-
#endif /* __ASSEMBLY__ */
52
+
#endif /* __ASSEMBLER__ */
53
53
54
54
#endif /* _ASM_SCS_H */
+2
-2
arch/riscv/include/asm/set_memory.h
+2
-2
arch/riscv/include/asm/set_memory.h
···
6
6
#ifndef _ASM_RISCV_SET_MEMORY_H
7
7
#define _ASM_RISCV_SET_MEMORY_H
8
8
9
-
#ifndef __ASSEMBLY__
9
+
#ifndef __ASSEMBLER__
10
10
/*
11
11
* Functions to change memory attributes.
12
12
*/
···
45
45
int set_direct_map_valid_noflush(struct page *page, unsigned nr, bool valid);
46
46
bool kernel_page_present(struct page *page);
47
47
48
-
#endif /* __ASSEMBLY__ */
48
+
#endif /* __ASSEMBLER__ */
49
49
50
50
#if defined(CONFIG_STRICT_KERNEL_RWX) || defined(CONFIG_XIP_KERNEL)
51
51
#ifdef CONFIG_64BIT
+87
arch/riscv/include/asm/swab.h
+87
arch/riscv/include/asm/swab.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
#ifndef _ASM_RISCV_SWAB_H
3
+
#define _ASM_RISCV_SWAB_H
4
+
5
+
#include <linux/types.h>
6
+
#include <linux/compiler.h>
7
+
#include <asm/cpufeature-macros.h>
8
+
#include <asm/hwcap.h>
9
+
#include <asm-generic/swab.h>
10
+
11
+
#if defined(CONFIG_TOOLCHAIN_HAS_ZBB) && defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE)
12
+
13
+
// Duplicated from include/uapi/linux/swab.h
14
+
#define ___constant_swab16(x) ((__u16)( \
15
+
(((__u16)(x) & (__u16)0x00ffU) << 8) | \
16
+
(((__u16)(x) & (__u16)0xff00U) >> 8)))
17
+
18
+
#define ___constant_swab32(x) ((__u32)( \
19
+
(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
20
+
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
21
+
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
22
+
(((__u32)(x) & (__u32)0xff000000UL) >> 24)))
23
+
24
+
#define ___constant_swab64(x) ((__u64)( \
25
+
(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
26
+
(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
27
+
(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
28
+
(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \
29
+
(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \
30
+
(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
31
+
(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
32
+
(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56)))
33
+
34
+
#define ARCH_SWAB(size, value) \
35
+
({ \
36
+
unsigned long x = value; \
37
+
\
38
+
if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { \
39
+
asm volatile (".option push\n" \
40
+
".option arch,+zbb\n" \
41
+
"rev8 %0, %1\n" \
42
+
".option pop\n" \
43
+
: "=r" (x) : "r" (x)); \
44
+
x = x >> (BITS_PER_LONG - size); \
45
+
} else { \
46
+
x = ___constant_swab##size(value); \
47
+
} \
48
+
x; \
49
+
})
50
+
51
+
static __always_inline __u16 __arch_swab16(__u16 value)
52
+
{
53
+
return ARCH_SWAB(16, value);
54
+
}
55
+
56
+
static __always_inline __u32 __arch_swab32(__u32 value)
57
+
{
58
+
return ARCH_SWAB(32, value);
59
+
}
60
+
61
+
#ifdef CONFIG_64BIT
62
+
static __always_inline __u64 __arch_swab64(__u64 value)
63
+
{
64
+
return ARCH_SWAB(64, value);
65
+
}
66
+
#else
67
+
static __always_inline __u64 __arch_swab64(__u64 value)
68
+
{
69
+
__u32 h = value >> 32;
70
+
__u32 l = value & ((1ULL << 32) - 1);
71
+
72
+
return ((__u64)(__arch_swab32(l)) << 32) | ((__u64)(__arch_swab32(h)));
73
+
}
74
+
#endif
75
+
76
+
#define __arch_swab64 __arch_swab64
77
+
#define __arch_swab32 __arch_swab32
78
+
#define __arch_swab16 __arch_swab16
79
+
80
+
#undef ___constant_swab16
81
+
#undef ___constant_swab32
82
+
#undef ___constant_swab64
83
+
84
+
#undef ARCH_SWAB
85
+
86
+
#endif /* defined(CONFIG_TOOLCHAIN_HAS_ZBB) && defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) */
87
+
#endif /* _ASM_RISCV_SWAB_H */
+2
-2
arch/riscv/include/asm/thread_info.h
+2
-2
arch/riscv/include/asm/thread_info.h
···
37
37
38
38
#define IRQ_STACK_SIZE THREAD_SIZE
39
39
40
-
#ifndef __ASSEMBLY__
40
+
#ifndef __ASSEMBLER__
41
41
42
42
#include <asm/processor.h>
43
43
#include <asm/csr.h>
···
98
98
void arch_release_task_struct(struct task_struct *tsk);
99
99
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
100
100
101
-
#endif /* !__ASSEMBLY__ */
101
+
#endif /* !__ASSEMBLER__ */
102
102
103
103
/*
104
104
* thread information flags
+2
-2
arch/riscv/include/asm/vdso.h
+2
-2
arch/riscv/include/asm/vdso.h
···
16
16
17
17
#define __VDSO_PAGES 4
18
18
19
-
#ifndef __ASSEMBLY__
19
+
#ifndef __ASSEMBLER__
20
20
#include <generated/vdso-offsets.h>
21
21
22
22
#define VDSO_SYMBOL(base, name) \
···
34
34
35
35
extern char vdso_start[], vdso_end[];
36
36
37
-
#endif /* !__ASSEMBLY__ */
37
+
#endif /* !__ASSEMBLER__ */
38
38
39
39
#endif /* CONFIG_MMU */
40
40
+2
-2
arch/riscv/include/asm/vdso/getrandom.h
+2
-2
arch/riscv/include/asm/vdso/getrandom.h
···
5
5
#ifndef __ASM_VDSO_GETRANDOM_H
6
6
#define __ASM_VDSO_GETRANDOM_H
7
7
8
-
#ifndef __ASSEMBLY__
8
+
#ifndef __ASSEMBLER__
9
9
10
10
#include <asm/unistd.h>
11
11
···
25
25
return ret;
26
26
}
27
27
28
-
#endif /* !__ASSEMBLY__ */
28
+
#endif /* !__ASSEMBLER__ */
29
29
30
30
#endif /* __ASM_VDSO_GETRANDOM_H */
+2
-2
arch/riscv/include/asm/vdso/gettimeofday.h
+2
-2
arch/riscv/include/asm/vdso/gettimeofday.h
···
2
2
#ifndef __ASM_VDSO_GETTIMEOFDAY_H
3
3
#define __ASM_VDSO_GETTIMEOFDAY_H
4
4
5
-
#ifndef __ASSEMBLY__
5
+
#ifndef __ASSEMBLER__
6
6
7
7
#include <asm/barrier.h>
8
8
#include <asm/unistd.h>
···
79
79
return csr_read(CSR_TIME);
80
80
}
81
81
82
-
#endif /* !__ASSEMBLY__ */
82
+
#endif /* !__ASSEMBLER__ */
83
83
84
84
#endif /* __ASM_VDSO_GETTIMEOFDAY_H */
+4
-3
arch/riscv/include/asm/vdso/processor.h
+4
-3
arch/riscv/include/asm/vdso/processor.h
···
2
2
#ifndef __ASM_VDSO_PROCESSOR_H
3
3
#define __ASM_VDSO_PROCESSOR_H
4
4
5
-
#ifndef __ASSEMBLY__
5
+
#ifndef __ASSEMBLER__
6
6
7
7
#include <asm/barrier.h>
8
+
#include <asm/errata_list.h>
8
9
#include <asm/insn-def.h>
9
10
10
11
static inline void cpu_relax(void)
···
20
19
* Reduce instruction retirement.
21
20
* This assumes the PC changes.
22
21
*/
23
-
__asm__ __volatile__ (RISCV_PAUSE);
22
+
ALT_RISCV_PAUSE();
24
23
barrier();
25
24
}
26
25
27
-
#endif /* __ASSEMBLY__ */
26
+
#endif /* __ASSEMBLER__ */
28
27
29
28
#endif /* __ASM_VDSO_PROCESSOR_H */
+2
-2
arch/riscv/include/asm/vdso/vsyscall.h
+2
-2
arch/riscv/include/asm/vdso/vsyscall.h
···
2
2
#ifndef __ASM_VDSO_VSYSCALL_H
3
3
#define __ASM_VDSO_VSYSCALL_H
4
4
5
-
#ifndef __ASSEMBLY__
5
+
#ifndef __ASSEMBLER__
6
6
7
7
#include <vdso/datapage.h>
8
8
9
9
/* The asm-generic header needs to be included after the definitions above */
10
10
#include <asm-generic/vdso/vsyscall.h>
11
11
12
-
#endif /* !__ASSEMBLY__ */
12
+
#endif /* !__ASSEMBLER__ */
13
13
14
14
#endif /* __ASM_VDSO_VSYSCALL_H */
+37
arch/riscv/include/asm/vendor_extensions/mips.h
+37
arch/riscv/include/asm/vendor_extensions/mips.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
7
+
#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
8
+
9
+
#include <linux/types.h>
10
+
11
+
#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL 0
12
+
13
+
#ifndef __ASSEMBLER__
14
+
struct riscv_isa_vendor_ext_data_list;
15
+
extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
16
+
#endif
17
+
18
+
/* Extension specific instructions */
19
+
20
+
/*
21
+
* All of the xmipsexectl extension instructions are
22
+
* ‘hint’ encodings of the SLLI instruction,
23
+
* with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB,
24
+
* and imm = 5 for PAUSE.
25
+
* MIPS.PAUSE is an alternative opcode which is implemented to have the
26
+
* same behavior as PAUSE on some MIPS RISCV cores.
27
+
* MIPS.EHB clears all execution hazards before allowing
28
+
* any subsequent instructions to execute.
29
+
* MIPS.IHB clears all instruction hazards before
30
+
* allowing any subsequent instructions to fetch.
31
+
*/
32
+
33
+
#define MIPS_PAUSE ".4byte 0x00501013\n\t"
34
+
#define MIPS_EHB ".4byte 0x00301013\n\t"
35
+
#define MIPS_IHB ".4byte 0x00101013\n\t"
36
+
37
+
#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
+22
arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
+22
arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
7
+
#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
8
+
9
+
#include <linux/cpumask.h>
10
+
#include <uapi/asm/hwprobe.h>
11
+
12
+
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
13
+
void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
14
+
#else
15
+
static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
16
+
const struct cpumask *cpus)
17
+
{
18
+
pair->value = 0;
19
+
}
20
+
#endif
21
+
22
+
#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
+1
arch/riscv/include/asm/vendorid_list.h
+1
arch/riscv/include/asm/vendorid_list.h
+1
arch/riscv/include/uapi/asm/hwprobe.h
+1
arch/riscv/include/uapi/asm/hwprobe.h
···
106
106
#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11
107
107
#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12
108
108
#define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13
109
+
#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14
109
110
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
110
111
111
112
/* Flags */
+1
-1
arch/riscv/include/uapi/asm/kvm.h
+1
-1
arch/riscv/include/uapi/asm/kvm.h
+2
-2
arch/riscv/include/uapi/asm/ptrace.h
+2
-2
arch/riscv/include/uapi/asm/ptrace.h
···
6
6
#ifndef _UAPI_ASM_RISCV_PTRACE_H
7
7
#define _UAPI_ASM_RISCV_PTRACE_H
8
8
9
-
#ifndef __ASSEMBLY__
9
+
#ifndef __ASSEMBLER__
10
10
11
11
#include <linux/types.h>
12
12
···
127
127
*/
128
128
#define RISCV_MAX_VLENB (8192)
129
129
130
-
#endif /* __ASSEMBLY__ */
130
+
#endif /* __ASSEMBLER__ */
131
131
132
132
#endif /* _UAPI_ASM_RISCV_PTRACE_H */
+2
-2
arch/riscv/include/uapi/asm/sigcontext.h
+2
-2
arch/riscv/include/uapi/asm/sigcontext.h
···
15
15
/* The size of END signal context header. */
16
16
#define END_HDR_SIZE 0x0
17
17
18
-
#ifndef __ASSEMBLY__
18
+
#ifndef __ASSEMBLER__
19
19
20
20
struct __sc_riscv_v_state {
21
21
struct __riscv_v_ext_state v_state;
···
35
35
};
36
36
};
37
37
38
-
#endif /*!__ASSEMBLY__*/
38
+
#endif /*!__ASSEMBLER__*/
39
39
40
40
#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
+3
arch/riscv/include/uapi/asm/vendor/mips.h
+3
arch/riscv/include/uapi/asm/vendor/mips.h
+3
arch/riscv/kernel/acpi.c
+3
arch/riscv/kernel/acpi.c
···
14
14
*/
15
15
16
16
#include <linux/acpi.h>
17
+
#include <linux/efi-bgrt.h>
17
18
#include <linux/efi.h>
18
19
#include <linux/io.h>
19
20
#include <linux/memblock.h>
···
161
160
early_init_dt_scan_chosen_stdout();
162
161
} else {
163
162
acpi_parse_spcr(earlycon_acpi_spcr_enable, true);
163
+
if (IS_ENABLED(CONFIG_ACPI_BGRT))
164
+
acpi_table_parse(ACPI_SIG_BGRT, acpi_parse_bgrt);
164
165
}
165
166
}
166
167
+5
arch/riscv/kernel/alternative.c
+5
arch/riscv/kernel/alternative.c
···
47
47
cpu_mfr_info->patch_func = andes_errata_patch_func;
48
48
break;
49
49
#endif
50
+
#ifdef CONFIG_ERRATA_MIPS
51
+
case MIPS_VENDOR_ID:
52
+
cpu_mfr_info->patch_func = mips_errata_patch_func;
53
+
break;
54
+
#endif
50
55
#ifdef CONFIG_ERRATA_SIFIVE
51
56
case SIFIVE_VENDOR_ID:
52
57
cpu_mfr_info->patch_func = sifive_errata_patch_func;
+3
-3
arch/riscv/kernel/cpufeature.c
+3
-3
arch/riscv/kernel/cpufeature.c
···
474
474
__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
475
475
__RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
476
476
__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
477
-
__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
477
+
__RISCV_ISA_EXT_DATA_VALIDATE(zfa, RISCV_ISA_EXT_ZFA, riscv_ext_f_depends),
478
478
__RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends),
479
-
__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
480
-
__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
479
+
__RISCV_ISA_EXT_DATA_VALIDATE(zfh, RISCV_ISA_EXT_ZFH, riscv_ext_f_depends),
480
+
__RISCV_ISA_EXT_DATA_VALIDATE(zfhmin, RISCV_ISA_EXT_ZFHMIN, riscv_ext_f_depends),
481
481
__RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
482
482
__RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
483
483
__RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
+1
arch/riscv/kernel/entry.S
+1
arch/riscv/kernel/entry.S
+1
-1
arch/riscv/kernel/machine_kexec_file.c
+1
-1
arch/riscv/kernel/machine_kexec_file.c
···
15
15
#include <linux/memblock.h>
16
16
#include <linux/vmalloc.h>
17
17
#include <asm/setup.h>
18
+
#include <asm/insn.h>
18
19
19
20
const struct kexec_file_ops * const kexec_file_loaders[] = {
20
21
&elf_kexec_ops,
···
110
109
}
111
110
#endif
112
111
113
-
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
114
112
#define RISCV_IMM_BITS 12
115
113
#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
116
114
#define RISCV_CONST_HIGH_PART(x) \
+1
-1
arch/riscv/kernel/pi/Makefile
+1
-1
arch/riscv/kernel/pi/Makefile
+2
-2
arch/riscv/kernel/pi/cmdline_early.c
+2
-2
arch/riscv/kernel/pi/cmdline_early.c
+40
arch/riscv/kernel/pi/fdt_early.c
+40
arch/riscv/kernel/pi/fdt_early.c
···
3
3
#include <linux/init.h>
4
4
#include <linux/libfdt.h>
5
5
#include <linux/ctype.h>
6
+
#include <asm/csr.h>
6
7
7
8
#include "pi.h"
8
9
···
183
182
}
184
183
185
184
return ret;
185
+
}
186
+
187
+
/**
188
+
* set_satp_mode_from_fdt - determine SATP mode based on the MMU type in fdt
189
+
*
190
+
* @dtb_pa: physical address of the device tree blob
191
+
*
192
+
* Returns the SATP mode corresponding to the MMU type of the first enabled CPU,
193
+
* 0 otherwise
194
+
*/
195
+
u64 set_satp_mode_from_fdt(uintptr_t dtb_pa)
196
+
{
197
+
const void *fdt = (const void *)dtb_pa;
198
+
const char *mmu_type;
199
+
int node, parent;
200
+
201
+
parent = fdt_path_offset(fdt, "/cpus");
202
+
if (parent < 0)
203
+
return 0;
204
+
205
+
fdt_for_each_subnode(node, fdt, parent) {
206
+
if (!fdt_node_name_eq(fdt, node, "cpu"))
207
+
continue;
208
+
209
+
if (!fdt_device_is_available(fdt, node))
210
+
continue;
211
+
212
+
mmu_type = fdt_getprop(fdt, node, "mmu-type", NULL);
213
+
if (!mmu_type)
214
+
break;
215
+
216
+
if (!strcmp(mmu_type, "riscv,sv39"))
217
+
return SATP_MODE_39;
218
+
else if (!strcmp(mmu_type, "riscv,sv48"))
219
+
return SATP_MODE_48;
220
+
break;
221
+
}
222
+
223
+
return 0;
186
224
}
+1
arch/riscv/kernel/pi/pi.h
+1
arch/riscv/kernel/pi/pi.h
···
14
14
u64 get_kaslr_seed_zkr(const uintptr_t dtb_pa);
15
15
bool set_nokaslr_from_cmdline(uintptr_t dtb_pa);
16
16
u64 set_satp_mode_from_cmdline(uintptr_t dtb_pa);
17
+
u64 set_satp_mode_from_fdt(uintptr_t dtb_pa);
17
18
18
19
bool fdt_early_match_extension_isa(const void *fdt, const char *ext_name);
19
20
+19
-75
arch/riscv/kernel/probes/simulate-insn.c
+19
-75
arch/riscv/kernel/probes/simulate-insn.c
···
41
41
* 1 10 1 8 5 JAL/J
42
42
*/
43
43
bool ret;
44
-
u32 imm;
45
-
u32 index = (opcode >> 7) & 0x1f;
44
+
s32 imm;
45
+
u32 index = RV_EXTRACT_RD_REG(opcode);
46
46
47
47
ret = rv_insn_reg_set_val(regs, index, addr + 4);
48
48
if (!ret)
49
49
return ret;
50
50
51
-
imm = ((opcode >> 21) & 0x3ff) << 1;
52
-
imm |= ((opcode >> 20) & 0x1) << 11;
53
-
imm |= ((opcode >> 12) & 0xff) << 12;
54
-
imm |= ((opcode >> 31) & 0x1) << 20;
51
+
imm = RV_EXTRACT_JTYPE_IMM(opcode);
55
52
56
-
instruction_pointer_set(regs, addr + sign_extend32((imm), 20));
53
+
instruction_pointer_set(regs, addr + imm);
57
54
58
55
return ret;
59
56
}
···
64
67
*/
65
68
bool ret;
66
69
unsigned long base_addr;
67
-
u32 imm = (opcode >> 20) & 0xfff;
68
-
u32 rd_index = (opcode >> 7) & 0x1f;
69
-
u32 rs1_index = (opcode >> 15) & 0x1f;
70
+
u32 imm = RV_EXTRACT_ITYPE_IMM(opcode);
71
+
u32 rd_index = RV_EXTRACT_RD_REG(opcode);
72
+
u32 rs1_index = RV_EXTRACT_RS1_REG(opcode);
70
73
71
74
ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr);
72
75
if (!ret)
···
81
84
return ret;
82
85
}
83
86
84
-
#define auipc_rd_idx(opcode) \
85
-
((opcode >> 7) & 0x1f)
86
-
87
-
#define auipc_imm(opcode) \
88
-
((((opcode) >> 12) & 0xfffff) << 12)
89
-
90
-
#if __riscv_xlen == 64
91
-
#define auipc_offset(opcode) sign_extend64(auipc_imm(opcode), 31)
92
-
#elif __riscv_xlen == 32
93
-
#define auipc_offset(opcode) auipc_imm(opcode)
94
-
#else
95
-
#error "Unexpected __riscv_xlen"
96
-
#endif
97
-
98
87
bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)
99
88
{
100
89
/*
···
90
107
* 20 5 7
91
108
*/
92
109
93
-
u32 rd_idx = auipc_rd_idx(opcode);
94
-
unsigned long rd_val = addr + auipc_offset(opcode);
110
+
u32 rd_idx = RV_EXTRACT_RD_REG(opcode);
111
+
unsigned long rd_val = addr + (s32)RV_EXTRACT_UTYPE_IMM(opcode);
95
112
96
113
if (!rv_insn_reg_set_val(regs, rd_idx, rd_val))
97
114
return false;
···
100
117
101
118
return true;
102
119
}
103
-
104
-
#define branch_rs1_idx(opcode) \
105
-
(((opcode) >> 15) & 0x1f)
106
-
107
-
#define branch_rs2_idx(opcode) \
108
-
(((opcode) >> 20) & 0x1f)
109
-
110
-
#define branch_funct3(opcode) \
111
-
(((opcode) >> 12) & 0x7)
112
-
113
-
#define branch_imm(opcode) \
114
-
(((((opcode) >> 8) & 0xf ) << 1) | \
115
-
((((opcode) >> 25) & 0x3f) << 5) | \
116
-
((((opcode) >> 7) & 0x1 ) << 11) | \
117
-
((((opcode) >> 31) & 0x1 ) << 12))
118
-
119
-
#define branch_offset(opcode) \
120
-
sign_extend32((branch_imm(opcode)), 12)
121
120
122
121
bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)
123
122
{
···
121
156
unsigned long rs1_val;
122
157
unsigned long rs2_val;
123
158
124
-
if (!rv_insn_reg_get_val(regs, branch_rs1_idx(opcode), &rs1_val) ||
125
-
!rv_insn_reg_get_val(regs, branch_rs2_idx(opcode), &rs2_val))
159
+
if (!rv_insn_reg_get_val(regs, RV_EXTRACT_RS1_REG(opcode), &rs1_val) ||
160
+
!rv_insn_reg_get_val(regs, RV_EXTRACT_RS2_REG(opcode), &rs2_val))
126
161
return false;
127
162
128
-
offset_tmp = branch_offset(opcode);
129
-
switch (branch_funct3(opcode)) {
163
+
offset_tmp = RV_EXTRACT_BTYPE_IMM(opcode);
164
+
switch (RV_EXTRACT_FUNCT3(opcode)) {
130
165
case RVG_FUNCT3_BEQ:
131
166
offset = (rs1_val == rs2_val) ? offset_tmp : 4;
132
167
break;
···
156
191
157
192
bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)
158
193
{
159
-
/*
160
-
* 15 13 12 2 1 0
161
-
* | funct3 | offset[11|4|9:8|10|6|7|3:1|5] | opcode |
162
-
* 3 11 2
163
-
*/
194
+
s32 offset = RVC_EXTRACT_JTYPE_IMM(opcode);
164
195
165
-
s32 offset;
166
-
167
-
offset = ((opcode >> 3) & 0x7) << 1;
168
-
offset |= ((opcode >> 11) & 0x1) << 4;
169
-
offset |= ((opcode >> 2) & 0x1) << 5;
170
-
offset |= ((opcode >> 7) & 0x1) << 6;
171
-
offset |= ((opcode >> 6) & 0x1) << 7;
172
-
offset |= ((opcode >> 9) & 0x3) << 8;
173
-
offset |= ((opcode >> 8) & 0x1) << 10;
174
-
offset |= ((opcode >> 12) & 0x1) << 11;
175
-
176
-
instruction_pointer_set(regs, addr + sign_extend32(offset, 11));
196
+
instruction_pointer_set(regs, addr + offset);
177
197
178
198
return true;
179
199
}
···
174
224
175
225
unsigned long jump_addr;
176
226
177
-
u32 rs1 = (opcode >> 7) & 0x1f;
227
+
u32 rs1 = RVC_EXTRACT_C2_RS1_REG(opcode);
178
228
179
229
if (rs1 == 0) /* C.JR is only valid when rs1 != x0 */
180
230
return false;
···
218
268
if (!rv_insn_reg_get_val(regs, rs1, &rs1_val))
219
269
return false;
220
270
221
-
if ((rs1_val != 0 && is_bnez) || (rs1_val == 0 && !is_bnez)) {
222
-
offset = ((opcode >> 3) & 0x3) << 1;
223
-
offset |= ((opcode >> 10) & 0x3) << 3;
224
-
offset |= ((opcode >> 2) & 0x1) << 5;
225
-
offset |= ((opcode >> 5) & 0x3) << 6;
226
-
offset |= ((opcode >> 12) & 0x1) << 8;
227
-
offset = sign_extend32(offset, 8);
228
-
} else {
271
+
if ((rs1_val != 0 && is_bnez) || (rs1_val == 0 && !is_bnez))
272
+
offset = RVC_EXTRACT_BTYPE_IMM(opcode);
273
+
else
229
274
offset = 2;
230
-
}
231
275
232
276
instruction_pointer_set(regs, addr + offset);
233
277
+2
-2
arch/riscv/kernel/sbi.c
+2
-2
arch/riscv/kernel/sbi.c
···
148
148
149
149
static void sbi_set_power_off(void)
150
150
{
151
-
pm_power_off = sbi_shutdown;
151
+
register_platform_power_off(sbi_shutdown);
152
152
}
153
153
#else
154
154
static void __sbi_set_timer_v01(uint64_t stime_value)
···
682
682
if (sbi_spec_version >= sbi_mk_version(0, 3) &&
683
683
sbi_probe_extension(SBI_EXT_SRST)) {
684
684
pr_info("SBI SRST extension detected\n");
685
-
pm_power_off = sbi_srst_power_off;
685
+
register_platform_power_off(sbi_srst_power_off);
686
686
sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot;
687
687
sbi_srst_reboot_nb.priority = 192;
688
688
register_restart_handler(&sbi_srst_reboot_nb);
+10
-8
arch/riscv/kernel/sys_hwprobe.c
+10
-8
arch/riscv/kernel/sys_hwprobe.c
···
15
15
#include <asm/uaccess.h>
16
16
#include <asm/unistd.h>
17
17
#include <asm/vector.h>
18
+
#include <asm/vendor_extensions/mips_hwprobe.h>
18
19
#include <asm/vendor_extensions/sifive_hwprobe.h>
19
20
#include <asm/vendor_extensions/thead_hwprobe.h>
20
21
#include <vdso/vsyscall.h>
···
154
153
EXT_KEY(ZVKT);
155
154
}
156
155
157
-
if (has_fpu()) {
158
-
EXT_KEY(ZCD);
159
-
EXT_KEY(ZCF);
160
-
EXT_KEY(ZFA);
161
-
EXT_KEY(ZFBFMIN);
162
-
EXT_KEY(ZFH);
163
-
EXT_KEY(ZFHMIN);
164
-
}
156
+
EXT_KEY(ZCD);
157
+
EXT_KEY(ZCF);
158
+
EXT_KEY(ZFA);
159
+
EXT_KEY(ZFBFMIN);
160
+
EXT_KEY(ZFH);
161
+
EXT_KEY(ZFHMIN);
165
162
166
163
if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
167
164
EXT_KEY(SUPM);
···
307
308
308
309
case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
309
310
hwprobe_isa_vendor_ext_thead_0(pair, cpus);
311
+
break;
312
+
case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
313
+
hwprobe_isa_vendor_ext_mips_0(pair, cpus);
310
314
break;
311
315
312
316
/*
+1
-1
arch/riscv/kernel/sys_riscv.c
+1
-1
arch/riscv/kernel/sys_riscv.c
···
10
10
11
11
static long riscv_sys_mmap(unsigned long addr, unsigned long len,
12
12
unsigned long prot, unsigned long flags,
13
-
unsigned long fd, off_t offset,
13
+
unsigned long fd, unsigned long offset,
14
14
unsigned long page_shift_offset)
15
15
{
16
16
if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
+12
arch/riscv/kernel/tests/Kconfig.debug
+12
arch/riscv/kernel/tests/Kconfig.debug
···
30
30
31
31
If unsure, say N.
32
32
33
+
config RISCV_KPROBES_KUNIT
34
+
bool "KUnit test for riscv kprobes" if !KUNIT_ALL_TESTS
35
+
depends on KUNIT
36
+
depends on KPROBES
37
+
default KUNIT_ALL_TESTS
38
+
help
39
+
Enable testing for riscv kprobes. Useful for riscv and/or kprobes
40
+
development. The test verifies that kprobes do not change the behaviour
41
+
of some sample functions.
42
+
43
+
If unsure, say N.
44
+
33
45
endif # RUNTIME_TESTING_MENU
34
46
35
47
endmenu # "arch/riscv/kernel runtime Testing"
+1
arch/riscv/kernel/tests/Makefile
+1
arch/riscv/kernel/tests/Makefile
+1
arch/riscv/kernel/tests/kprobes/Makefile
+1
arch/riscv/kernel/tests/kprobes/Makefile
···
1
+
obj-y += test-kprobes.o test-kprobes-asm.o
+229
arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S
+229
arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
3
+
#include <linux/linkage.h>
4
+
#include <asm/asm.h>
5
+
#include "test-kprobes.h"
6
+
7
+
SYM_FUNC_START(test_kprobes_add)
8
+
li a1, KPROBE_TEST_MAGIC_UPPER
9
+
li a2, KPROBE_TEST_MAGIC_LOWER
10
+
test_kprobes_add_addr1:
11
+
add a1, a1, a2
12
+
test_kprobes_add_addr2:
13
+
add a0, a1, x0
14
+
ret
15
+
SYM_FUNC_END(test_kprobes_add)
16
+
17
+
SYM_FUNC_START(test_kprobes_jal)
18
+
li a0, 0
19
+
mv a1, ra
20
+
.option push
21
+
.option norvc
22
+
test_kprobes_jal_addr1:
23
+
jal x0, 2f
24
+
ret
25
+
.option pop
26
+
1: li a0, KPROBE_TEST_MAGIC_UPPER
27
+
ret
28
+
.option push
29
+
.option norvc
30
+
test_kprobes_jal_addr2:
31
+
2: jal 1b
32
+
.option pop
33
+
li a2, KPROBE_TEST_MAGIC_LOWER
34
+
add a0, a0, a2
35
+
jr a1
36
+
SYM_FUNC_END(test_kprobes_jal)
37
+
38
+
SYM_FUNC_START(test_kprobes_jalr)
39
+
la a0, 1f
40
+
mv a1, ra
41
+
.option push
42
+
.option norvc
43
+
test_kprobes_jalr_addr:
44
+
jalr a0
45
+
.option pop
46
+
li t0, KPROBE_TEST_MAGIC_UPPER
47
+
add a0, a0, t0
48
+
jr a1
49
+
1: li a0, KPROBE_TEST_MAGIC_LOWER
50
+
ret
51
+
SYM_FUNC_END(test_kprobes_jalr)
52
+
53
+
SYM_FUNC_START(test_kprobes_auipc)
54
+
test_kprobes_auipc_addr:
55
+
auipc a0, KPROBE_TEST_MAGIC_LOWER
56
+
la a1, test_kprobes_auipc_addr
57
+
sub a0, a0, a1
58
+
srli a0, a0, 12
59
+
li a1, KPROBE_TEST_MAGIC_UPPER
60
+
add a0, a0, a1
61
+
ret
62
+
SYM_FUNC_END(test_kprobes_auipc)
63
+
64
+
SYM_FUNC_START(test_kprobes_branch)
65
+
.option push
66
+
.option norvc
67
+
li a0, 0
68
+
li a1, 1
69
+
li a2, 2
70
+
test_kprobes_branch_addr1:
71
+
beqz a0, 1f
72
+
ret
73
+
1:
74
+
test_kprobes_branch_addr2:
75
+
beqz a1, 3f
76
+
test_kprobes_branch_addr3:
77
+
bnez a0, 3f
78
+
test_kprobes_branch_addr4:
79
+
bnez a2, 1f
80
+
ret
81
+
1:
82
+
test_kprobes_branch_addr5:
83
+
bge a1, a2, 3f
84
+
test_kprobes_branch_addr6:
85
+
bge a2, a1, 2f
86
+
ret
87
+
1:
88
+
li t0, KPROBE_TEST_MAGIC_UPPER
89
+
add a0, a0, t0
90
+
ret
91
+
2:
92
+
test_kprobes_branch_addr7:
93
+
blt a2, a1, 3f
94
+
li a0, KPROBE_TEST_MAGIC_LOWER
95
+
test_kprobes_branch_addr8:
96
+
blt a1, a2, 1b
97
+
3:
98
+
li a0, 0
99
+
ret
100
+
.option pop
101
+
SYM_FUNC_END(test_kprobes_branch)
102
+
103
+
#ifdef CONFIG_RISCV_ISA_C
104
+
105
+
SYM_FUNC_START(test_kprobes_c_j)
106
+
li a0, 0
107
+
test_kprobes_branch_c_j_addr1:
108
+
c.j 2f
109
+
1:
110
+
li a1, KPROBE_TEST_MAGIC_UPPER
111
+
add a0, a0, a1
112
+
ret
113
+
2: li a0, KPROBE_TEST_MAGIC_LOWER
114
+
test_kprobes_branch_c_j_addr2:
115
+
c.j 1b
116
+
SYM_FUNC_END(test_kprobes_c_j)
117
+
118
+
SYM_FUNC_START(test_kprobes_c_jr)
119
+
la a0, 2f
120
+
test_kprobes_c_jr_addr1:
121
+
c.jr a0
122
+
ret
123
+
1: li a1, KPROBE_TEST_MAGIC_LOWER
124
+
add a0, a0, a1
125
+
ret
126
+
2:
127
+
li a0, KPROBE_TEST_MAGIC_UPPER
128
+
la a1, 1b
129
+
test_kprobes_c_jr_addr2:
130
+
c.jr a1
131
+
SYM_FUNC_END(test_kprobes_c_jr)
132
+
133
+
SYM_FUNC_START(test_kprobes_c_jalr)
134
+
mv a1, ra
135
+
la a0, 1f
136
+
test_kprobes_c_jalr_addr:
137
+
c.jalr a0
138
+
li a2, KPROBE_TEST_MAGIC_UPPER
139
+
add a0, a0, a2
140
+
jr a1
141
+
1: li a0, KPROBE_TEST_MAGIC_LOWER
142
+
ret
143
+
SYM_FUNC_END(test_kprobes_c_jalr)
144
+
145
+
SYM_FUNC_START(test_kprobes_c_beqz)
146
+
li a0, 0
147
+
li a1, 1
148
+
test_kprobes_c_beqz_addr1:
149
+
c.beqz a0, 2f
150
+
ret
151
+
1: li a1, KPROBE_TEST_MAGIC_UPPER
152
+
add a0, a0, a1
153
+
ret
154
+
test_kprobes_c_beqz_addr2:
155
+
2: c.beqz a1, 3f
156
+
li a0, KPROBE_TEST_MAGIC_LOWER
157
+
mv a1, x0
158
+
test_kprobes_c_beqz_addr3:
159
+
c.beqz a1, 1b
160
+
3: li a0, 0
161
+
ret
162
+
SYM_FUNC_END(test_kprobes_c_beqz)
163
+
164
+
SYM_FUNC_START(test_kprobes_c_bnez)
165
+
li a0, 0
166
+
li a1, 1
167
+
test_kprobes_c_bnez_addr1:
168
+
c.bnez a1, 2f
169
+
ret
170
+
1: li a1, KPROBE_TEST_MAGIC_UPPER
171
+
add a0, a0, a1
172
+
ret
173
+
test_kprobes_c_bnez_addr2:
174
+
2: c.bnez a0, 3f
175
+
li a0, KPROBE_TEST_MAGIC_LOWER
176
+
test_kprobes_c_bnez_addr3:
177
+
c.bnez a0, 1b
178
+
3: li a0, 0
179
+
ret
180
+
SYM_FUNC_END(test_kprobes_c_bnez)
181
+
182
+
#endif /* CONFIG_RISCV_ISA_C */
183
+
184
+
SYM_DATA_START(test_kprobes_addresses)
185
+
RISCV_PTR test_kprobes_add_addr1
186
+
RISCV_PTR test_kprobes_add_addr2
187
+
RISCV_PTR test_kprobes_jal_addr1
188
+
RISCV_PTR test_kprobes_jal_addr2
189
+
RISCV_PTR test_kprobes_jalr_addr
190
+
RISCV_PTR test_kprobes_auipc_addr
191
+
RISCV_PTR test_kprobes_branch_addr1
192
+
RISCV_PTR test_kprobes_branch_addr2
193
+
RISCV_PTR test_kprobes_branch_addr3
194
+
RISCV_PTR test_kprobes_branch_addr4
195
+
RISCV_PTR test_kprobes_branch_addr5
196
+
RISCV_PTR test_kprobes_branch_addr6
197
+
RISCV_PTR test_kprobes_branch_addr7
198
+
RISCV_PTR test_kprobes_branch_addr8
199
+
#ifdef CONFIG_RISCV_ISA_C
200
+
RISCV_PTR test_kprobes_branch_c_j_addr1
201
+
RISCV_PTR test_kprobes_branch_c_j_addr2
202
+
RISCV_PTR test_kprobes_c_jr_addr1
203
+
RISCV_PTR test_kprobes_c_jr_addr2
204
+
RISCV_PTR test_kprobes_c_jalr_addr
205
+
RISCV_PTR test_kprobes_c_beqz_addr1
206
+
RISCV_PTR test_kprobes_c_beqz_addr2
207
+
RISCV_PTR test_kprobes_c_beqz_addr3
208
+
RISCV_PTR test_kprobes_c_bnez_addr1
209
+
RISCV_PTR test_kprobes_c_bnez_addr2
210
+
RISCV_PTR test_kprobes_c_bnez_addr3
211
+
#endif /* CONFIG_RISCV_ISA_C */
212
+
RISCV_PTR 0
213
+
SYM_DATA_END(test_kprobes_addresses)
214
+
215
+
SYM_DATA_START(test_kprobes_functions)
216
+
RISCV_PTR test_kprobes_add
217
+
RISCV_PTR test_kprobes_jal
218
+
RISCV_PTR test_kprobes_jalr
219
+
RISCV_PTR test_kprobes_auipc
220
+
RISCV_PTR test_kprobes_branch
221
+
#ifdef CONFIG_RISCV_ISA_C
222
+
RISCV_PTR test_kprobes_c_j
223
+
RISCV_PTR test_kprobes_c_jr
224
+
RISCV_PTR test_kprobes_c_jalr
225
+
RISCV_PTR test_kprobes_c_beqz
226
+
RISCV_PTR test_kprobes_c_bnez
227
+
#endif /* CONFIG_RISCV_ISA_C */
228
+
RISCV_PTR 0
229
+
SYM_DATA_END(test_kprobes_functions)
+56
arch/riscv/kernel/tests/kprobes/test-kprobes.c
+56
arch/riscv/kernel/tests/kprobes/test-kprobes.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
3
+
#include <linux/kernel.h>
4
+
#include <linux/kprobes.h>
5
+
#include <kunit/test.h>
6
+
#include "test-kprobes.h"
7
+
8
+
static int kprobe_dummy_handler(struct kprobe *kp, struct pt_regs *regs)
9
+
{
10
+
return 0;
11
+
}
12
+
13
+
static void test_kprobe_riscv(struct kunit *test)
14
+
{
15
+
unsigned int num_kprobe = 0;
16
+
long (*func)(void);
17
+
struct kprobe *kp;
18
+
int i;
19
+
20
+
while (test_kprobes_addresses[num_kprobe])
21
+
num_kprobe++;
22
+
23
+
kp = kcalloc(num_kprobe, sizeof(*kp), GFP_KERNEL);
24
+
KUNIT_EXPECT_TRUE(test, kp);
25
+
if (!kp)
26
+
return;
27
+
28
+
for (i = 0; i < num_kprobe; ++i) {
29
+
kp[i].addr = test_kprobes_addresses[i];
30
+
kp[i].pre_handler = kprobe_dummy_handler;
31
+
KUNIT_EXPECT_EQ(test, 0, register_kprobe(&kp[i]));
32
+
}
33
+
34
+
for (i = 0;; ++i) {
35
+
func = test_kprobes_functions[i];
36
+
if (!func)
37
+
break;
38
+
KUNIT_EXPECT_EQ_MSG(test, KPROBE_TEST_MAGIC, func(), "function %d broken", i);
39
+
}
40
+
41
+
for (i = 0; i < num_kprobe; ++i)
42
+
unregister_kprobe(&kp[i]);
43
+
kfree(kp);
44
+
}
45
+
46
+
static struct kunit_case kprobes_testcases[] = {
47
+
KUNIT_CASE(test_kprobe_riscv),
48
+
{}
49
+
};
50
+
51
+
static struct kunit_suite kprobes_test_suite = {
52
+
.name = "kprobes_test_riscv",
53
+
.test_cases = kprobes_testcases,
54
+
};
55
+
56
+
kunit_test_suites(&kprobes_test_suite);
+24
arch/riscv/kernel/tests/kprobes/test-kprobes.h
+24
arch/riscv/kernel/tests/kprobes/test-kprobes.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
#ifndef TEST_KPROBES_H
3
+
#define TEST_KPROBES_H
4
+
5
+
/*
6
+
* The magic value that all the functions in the test_kprobes_functions array return. The test
7
+
* installs kprobes into these functions, and verify that the functions still correctly return this
8
+
* value.
9
+
*/
10
+
#define KPROBE_TEST_MAGIC 0xcafebabe
11
+
#define KPROBE_TEST_MAGIC_LOWER 0x0000babe
12
+
#define KPROBE_TEST_MAGIC_UPPER 0xcafe0000
13
+
14
+
#ifndef __ASSEMBLY__
15
+
16
+
/* array of addresses to install kprobes */
17
+
extern void *test_kprobes_addresses[];
18
+
19
+
/* array of functions that return KPROBE_TEST_MAGIC */
20
+
extern long (*test_kprobes_functions[])(void);
21
+
22
+
#endif /* __ASSEMBLY__ */
23
+
24
+
#endif /* TEST_KPROBES_H */
+1
-143
arch/riscv/kernel/traps_misaligned.c
+1
-143
arch/riscv/kernel/traps_misaligned.c
···
18
18
#include <asm/cpufeature.h>
19
19
#include <asm/sbi.h>
20
20
#include <asm/vector.h>
21
-
22
-
#define INSN_MATCH_LB 0x3
23
-
#define INSN_MASK_LB 0x707f
24
-
#define INSN_MATCH_LH 0x1003
25
-
#define INSN_MASK_LH 0x707f
26
-
#define INSN_MATCH_LW 0x2003
27
-
#define INSN_MASK_LW 0x707f
28
-
#define INSN_MATCH_LD 0x3003
29
-
#define INSN_MASK_LD 0x707f
30
-
#define INSN_MATCH_LBU 0x4003
31
-
#define INSN_MASK_LBU 0x707f
32
-
#define INSN_MATCH_LHU 0x5003
33
-
#define INSN_MASK_LHU 0x707f
34
-
#define INSN_MATCH_LWU 0x6003
35
-
#define INSN_MASK_LWU 0x707f
36
-
#define INSN_MATCH_SB 0x23
37
-
#define INSN_MASK_SB 0x707f
38
-
#define INSN_MATCH_SH 0x1023
39
-
#define INSN_MASK_SH 0x707f
40
-
#define INSN_MATCH_SW 0x2023
41
-
#define INSN_MASK_SW 0x707f
42
-
#define INSN_MATCH_SD 0x3023
43
-
#define INSN_MASK_SD 0x707f
44
-
45
-
#define INSN_MATCH_FLW 0x2007
46
-
#define INSN_MASK_FLW 0x707f
47
-
#define INSN_MATCH_FLD 0x3007
48
-
#define INSN_MASK_FLD 0x707f
49
-
#define INSN_MATCH_FLQ 0x4007
50
-
#define INSN_MASK_FLQ 0x707f
51
-
#define INSN_MATCH_FSW 0x2027
52
-
#define INSN_MASK_FSW 0x707f
53
-
#define INSN_MATCH_FSD 0x3027
54
-
#define INSN_MASK_FSD 0x707f
55
-
#define INSN_MATCH_FSQ 0x4027
56
-
#define INSN_MASK_FSQ 0x707f
57
-
58
-
#define INSN_MATCH_C_LD 0x6000
59
-
#define INSN_MASK_C_LD 0xe003
60
-
#define INSN_MATCH_C_SD 0xe000
61
-
#define INSN_MASK_C_SD 0xe003
62
-
#define INSN_MATCH_C_LW 0x4000
63
-
#define INSN_MASK_C_LW 0xe003
64
-
#define INSN_MATCH_C_SW 0xc000
65
-
#define INSN_MASK_C_SW 0xe003
66
-
#define INSN_MATCH_C_LDSP 0x6002
67
-
#define INSN_MASK_C_LDSP 0xe003
68
-
#define INSN_MATCH_C_SDSP 0xe002
69
-
#define INSN_MASK_C_SDSP 0xe003
70
-
#define INSN_MATCH_C_LWSP 0x4002
71
-
#define INSN_MASK_C_LWSP 0xe003
72
-
#define INSN_MATCH_C_SWSP 0xc002
73
-
#define INSN_MASK_C_SWSP 0xe003
74
-
75
-
#define INSN_MATCH_C_FLD 0x2000
76
-
#define INSN_MASK_C_FLD 0xe003
77
-
#define INSN_MATCH_C_FLW 0x6000
78
-
#define INSN_MASK_C_FLW 0xe003
79
-
#define INSN_MATCH_C_FSD 0xa000
80
-
#define INSN_MASK_C_FSD 0xe003
81
-
#define INSN_MATCH_C_FSW 0xe000
82
-
#define INSN_MASK_C_FSW 0xe003
83
-
#define INSN_MATCH_C_FLDSP 0x2002
84
-
#define INSN_MASK_C_FLDSP 0xe003
85
-
#define INSN_MATCH_C_FSDSP 0xa002
86
-
#define INSN_MASK_C_FSDSP 0xe003
87
-
#define INSN_MATCH_C_FLWSP 0x6002
88
-
#define INSN_MASK_C_FLWSP 0xe003
89
-
#define INSN_MATCH_C_FSWSP 0xe002
90
-
#define INSN_MASK_C_FSWSP 0xe003
91
-
92
-
#define INSN_MATCH_C_LHU 0x8400
93
-
#define INSN_MASK_C_LHU 0xfc43
94
-
#define INSN_MATCH_C_LH 0x8440
95
-
#define INSN_MASK_C_LH 0xfc43
96
-
#define INSN_MATCH_C_SH 0x8c00
97
-
#define INSN_MASK_C_SH 0xfc43
98
-
99
-
#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
100
-
101
-
#if defined(CONFIG_64BIT)
102
-
#define LOG_REGBYTES 3
103
-
#define XLEN 64
104
-
#else
105
-
#define LOG_REGBYTES 2
106
-
#define XLEN 32
107
-
#endif
108
-
#define REGBYTES (1 << LOG_REGBYTES)
109
-
#define XLEN_MINUS_16 ((XLEN) - 16)
110
-
111
-
#define SH_RD 7
112
-
#define SH_RS1 15
113
-
#define SH_RS2 20
114
-
#define SH_RS2C 2
115
-
116
-
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
117
-
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
118
-
(RV_X(x, 10, 3) << 3) | \
119
-
(RV_X(x, 5, 1) << 6))
120
-
#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
121
-
(RV_X(x, 5, 2) << 6))
122
-
#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
123
-
(RV_X(x, 12, 1) << 5) | \
124
-
(RV_X(x, 2, 2) << 6))
125
-
#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
126
-
(RV_X(x, 12, 1) << 5) | \
127
-
(RV_X(x, 2, 3) << 6))
128
-
#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
129
-
(RV_X(x, 7, 2) << 6))
130
-
#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
131
-
(RV_X(x, 7, 3) << 6))
132
-
#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
133
-
#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
134
-
#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
135
-
136
-
#define SHIFT_RIGHT(x, y) \
137
-
((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
138
-
139
-
#define REG_MASK \
140
-
((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
141
-
142
-
#define REG_OFFSET(insn, pos) \
143
-
(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
144
-
145
-
#define REG_PTR(insn, pos, regs) \
146
-
(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
147
-
148
-
#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
149
-
#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
150
-
#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
151
-
#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
152
-
#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
153
-
#define GET_SP(regs) (*REG_PTR(2, 0, regs))
154
-
#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
155
-
#define IMM_I(insn) ((s32)(insn) >> 20)
156
-
#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
157
-
(s32)(((insn) >> 7) & 0x1f))
158
-
#define MASK_FUNCT3 0x7000
159
-
160
-
#define GET_PRECISION(insn) (((insn) >> 25) & 3)
161
-
#define GET_RM(insn) (((insn) >> 12) & 7)
162
-
#define PRECISION_S 0
163
-
#define PRECISION_D 1
21
+
#include <asm/insn.h>
164
22
165
23
#ifdef CONFIG_FPU
166
24
+1
-1
arch/riscv/kernel/vector.c
+1
-1
arch/riscv/kernel/vector.c
···
93
93
return true;
94
94
case RVV_OPCODE_VL:
95
95
case RVV_OPCODE_VS:
96
-
width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
96
+
width = RVV_EXTRACT_VL_VS_WIDTH(insn_buf);
97
97
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
98
98
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
99
99
return true;
+10
arch/riscv/kernel/vendor_extensions.c
+10
arch/riscv/kernel/vendor_extensions.c
···
6
6
#include <asm/vendorid_list.h>
7
7
#include <asm/vendor_extensions.h>
8
8
#include <asm/vendor_extensions/andes.h>
9
+
#include <asm/vendor_extensions/mips.h>
9
10
#include <asm/vendor_extensions/sifive.h>
10
11
#include <asm/vendor_extensions/thead.h>
11
12
···
16
15
struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = {
17
16
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
18
17
&riscv_isa_vendor_ext_list_andes,
18
+
#endif
19
+
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
20
+
&riscv_isa_vendor_ext_list_mips,
19
21
#endif
20
22
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
21
23
&riscv_isa_vendor_ext_list_sifive,
···
51
47
case ANDES_VENDOR_ID:
52
48
bmap = &riscv_isa_vendor_ext_list_andes.all_harts_isa_bitmap;
53
49
cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
50
+
break;
51
+
#endif
52
+
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
53
+
case MIPS_VENDOR_ID:
54
+
bmap = &riscv_isa_vendor_ext_list_mips.all_harts_isa_bitmap;
55
+
cpu_bmap = riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap;
54
56
break;
55
57
#endif
56
58
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
+2
arch/riscv/kernel/vendor_extensions/Makefile
+2
arch/riscv/kernel/vendor_extensions/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0-only
2
2
3
3
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
4
+
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) += mips.o
5
+
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) += mips_hwprobe.o
4
6
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive.o
5
7
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive_hwprobe.o
6
8
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o
+22
arch/riscv/kernel/vendor_extensions/mips.c
+22
arch/riscv/kernel/vendor_extensions/mips.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#include <asm/cpufeature.h>
7
+
#include <asm/vendor_extensions.h>
8
+
#include <asm/vendor_extensions/mips.h>
9
+
10
+
#include <linux/array_size.h>
11
+
#include <linux/cpumask.h>
12
+
#include <linux/types.h>
13
+
14
+
/* All MIPS vendor extensions supported in Linux */
15
+
static const struct riscv_isa_ext_data riscv_isa_vendor_ext_mips[] = {
16
+
__RISCV_ISA_EXT_DATA(xmipsexectl, RISCV_ISA_VENDOR_EXT_XMIPSEXECTL),
17
+
};
18
+
19
+
struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips = {
20
+
.ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_mips),
21
+
.ext_data = riscv_isa_vendor_ext_mips,
22
+
};
+23
arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
+23
arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#include <asm/vendor_extensions.h>
7
+
#include <asm/vendor_extensions/mips.h>
8
+
#include <asm/vendor_extensions/mips_hwprobe.h>
9
+
#include <asm/vendor_extensions/vendor_hwprobe.h>
10
+
11
+
#include <linux/cpumask.h>
12
+
#include <linux/types.h>
13
+
14
+
#include <uapi/asm/hwprobe.h>
15
+
#include <uapi/asm/vendor/mips.h>
16
+
17
+
void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
18
+
const struct cpumask *cpus)
19
+
{
20
+
VENDOR_EXTENSION_SUPPORTED(pair, cpus,
21
+
riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap,
22
+
{ VENDOR_EXT_KEY(XMIPSEXECTL); });
23
+
}
+1
-127
arch/riscv/kvm/vcpu_insn.c
+1
-127
arch/riscv/kvm/vcpu_insn.c
···
8
8
#include <linux/kvm_host.h>
9
9
10
10
#include <asm/cpufeature.h>
11
-
12
-
#define INSN_OPCODE_MASK 0x007c
13
-
#define INSN_OPCODE_SHIFT 2
14
-
#define INSN_OPCODE_SYSTEM 28
15
-
16
-
#define INSN_MASK_WFI 0xffffffff
17
-
#define INSN_MATCH_WFI 0x10500073
18
-
19
-
#define INSN_MASK_WRS 0xffffffff
20
-
#define INSN_MATCH_WRS 0x00d00073
21
-
22
-
#define INSN_MATCH_CSRRW 0x1073
23
-
#define INSN_MASK_CSRRW 0x707f
24
-
#define INSN_MATCH_CSRRS 0x2073
25
-
#define INSN_MASK_CSRRS 0x707f
26
-
#define INSN_MATCH_CSRRC 0x3073
27
-
#define INSN_MASK_CSRRC 0x707f
28
-
#define INSN_MATCH_CSRRWI 0x5073
29
-
#define INSN_MASK_CSRRWI 0x707f
30
-
#define INSN_MATCH_CSRRSI 0x6073
31
-
#define INSN_MASK_CSRRSI 0x707f
32
-
#define INSN_MATCH_CSRRCI 0x7073
33
-
#define INSN_MASK_CSRRCI 0x707f
34
-
35
-
#define INSN_MATCH_LB 0x3
36
-
#define INSN_MASK_LB 0x707f
37
-
#define INSN_MATCH_LH 0x1003
38
-
#define INSN_MASK_LH 0x707f
39
-
#define INSN_MATCH_LW 0x2003
40
-
#define INSN_MASK_LW 0x707f
41
-
#define INSN_MATCH_LD 0x3003
42
-
#define INSN_MASK_LD 0x707f
43
-
#define INSN_MATCH_LBU 0x4003
44
-
#define INSN_MASK_LBU 0x707f
45
-
#define INSN_MATCH_LHU 0x5003
46
-
#define INSN_MASK_LHU 0x707f
47
-
#define INSN_MATCH_LWU 0x6003
48
-
#define INSN_MASK_LWU 0x707f
49
-
#define INSN_MATCH_SB 0x23
50
-
#define INSN_MASK_SB 0x707f
51
-
#define INSN_MATCH_SH 0x1023
52
-
#define INSN_MASK_SH 0x707f
53
-
#define INSN_MATCH_SW 0x2023
54
-
#define INSN_MASK_SW 0x707f
55
-
#define INSN_MATCH_SD 0x3023
56
-
#define INSN_MASK_SD 0x707f
57
-
58
-
#define INSN_MATCH_C_LD 0x6000
59
-
#define INSN_MASK_C_LD 0xe003
60
-
#define INSN_MATCH_C_SD 0xe000
61
-
#define INSN_MASK_C_SD 0xe003
62
-
#define INSN_MATCH_C_LW 0x4000
63
-
#define INSN_MASK_C_LW 0xe003
64
-
#define INSN_MATCH_C_SW 0xc000
65
-
#define INSN_MASK_C_SW 0xe003
66
-
#define INSN_MATCH_C_LDSP 0x6002
67
-
#define INSN_MASK_C_LDSP 0xe003
68
-
#define INSN_MATCH_C_SDSP 0xe002
69
-
#define INSN_MASK_C_SDSP 0xe003
70
-
#define INSN_MATCH_C_LWSP 0x4002
71
-
#define INSN_MASK_C_LWSP 0xe003
72
-
#define INSN_MATCH_C_SWSP 0xc002
73
-
#define INSN_MASK_C_SWSP 0xe003
74
-
75
-
#define INSN_16BIT_MASK 0x3
76
-
77
-
#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
78
-
79
-
#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
80
-
81
-
#ifdef CONFIG_64BIT
82
-
#define LOG_REGBYTES 3
83
-
#else
84
-
#define LOG_REGBYTES 2
85
-
#endif
86
-
#define REGBYTES (1 << LOG_REGBYTES)
87
-
88
-
#define SH_RD 7
89
-
#define SH_RS1 15
90
-
#define SH_RS2 20
91
-
#define SH_RS2C 2
92
-
#define MASK_RX 0x1f
93
-
94
-
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
95
-
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
96
-
(RV_X(x, 10, 3) << 3) | \
97
-
(RV_X(x, 5, 1) << 6))
98
-
#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
99
-
(RV_X(x, 5, 2) << 6))
100
-
#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
101
-
(RV_X(x, 12, 1) << 5) | \
102
-
(RV_X(x, 2, 2) << 6))
103
-
#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
104
-
(RV_X(x, 12, 1) << 5) | \
105
-
(RV_X(x, 2, 3) << 6))
106
-
#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
107
-
(RV_X(x, 7, 2) << 6))
108
-
#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
109
-
(RV_X(x, 7, 3) << 6))
110
-
#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
111
-
#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
112
-
#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
113
-
114
-
#define SHIFT_RIGHT(x, y) \
115
-
((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
116
-
117
-
#define REG_MASK \
118
-
((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
119
-
120
-
#define REG_OFFSET(insn, pos) \
121
-
(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
122
-
123
-
#define REG_PTR(insn, pos, regs) \
124
-
((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
125
-
126
-
#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
127
-
128
-
#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
129
-
#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
130
-
#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
131
-
#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
132
-
#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
133
-
#define GET_SP(regs) (*REG_PTR(2, 0, regs))
134
-
#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
135
-
#define IMM_I(insn) ((s32)(insn) >> 20)
136
-
#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
137
-
(s32)(((insn) >> 7) & 0x1f))
11
+
#include <asm/insn.h>
138
12
139
13
struct insn_func {
140
14
unsigned long mask;
+9
-3
arch/riscv/mm/init.c
+9
-3
arch/riscv/mm/init.c
···
23
23
#include <linux/kfence.h>
24
24
#include <linux/execmem.h>
25
25
26
+
#include <asm/alternative.h>
26
27
#include <asm/fixmap.h>
27
28
#include <asm/io.h>
28
29
#include <asm/kasan.h>
···
817
816
818
817
#if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL)
819
818
u64 __pi_set_satp_mode_from_cmdline(uintptr_t dtb_pa);
819
+
u64 __pi_set_satp_mode_from_fdt(uintptr_t dtb_pa);
820
820
821
821
static void __init disable_pgtable_l5(void)
822
822
{
···
857
855
* underlying hardware: establish 1:1 mapping in 4-level page table mode
858
856
* then read SATP to see if the configuration was taken into account
859
857
* meaning sv48 is supported.
858
+
* The maximum SATP mode is limited by both the command line and the "mmu-type"
859
+
* property in the device tree, since some platforms may hang if an unsupported
860
+
* SATP mode is attempted.
860
861
*/
861
862
static __init void set_satp_mode(uintptr_t dtb_pa)
862
863
{
863
864
u64 identity_satp, hw_satp;
864
865
uintptr_t set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK;
865
-
u64 satp_mode_cmdline = __pi_set_satp_mode_from_cmdline(dtb_pa);
866
+
u64 satp_mode_limit = min_not_zero(__pi_set_satp_mode_from_cmdline(dtb_pa),
867
+
__pi_set_satp_mode_from_fdt(dtb_pa));
866
868
867
869
kernel_map.page_offset = PAGE_OFFSET_L5;
868
870
869
-
if (satp_mode_cmdline == SATP_MODE_57) {
871
+
if (satp_mode_limit == SATP_MODE_48) {
870
872
disable_pgtable_l5();
871
-
} else if (satp_mode_cmdline == SATP_MODE_48) {
873
+
} else if (satp_mode_limit == SATP_MODE_39) {
872
874
disable_pgtable_l5();
873
875
disable_pgtable_l4();
874
876
return;
+5
-3
drivers/perf/riscv_pmu_sbi.c
+5
-3
drivers/perf/riscv_pmu_sbi.c
···
339
339
if (!info)
340
340
return false;
341
341
342
-
return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
342
+
return info->type == SBI_PMU_CTR_TYPE_FW;
343
343
}
344
344
345
345
/*
···
877
877
for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
878
878
ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask;
879
879
/* Start all the counters that did not overflow in a single shot */
880
-
sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr_start_mask,
881
-
0, 0, 0, 0);
880
+
if (ctr_start_mask) {
881
+
sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG,
882
+
ctr_start_mask, 0, 0, 0, 0);
883
+
}
882
884
}
883
885
884
886
/* Reinitialize and start all the counter that overflowed */
-2
lib/raid6/recov_rvv.c
-2
lib/raid6/recov_rvv.c
+30
-33
lib/raid6/rvv.c
+30
-33
lib/raid6/rvv.c
···
9
9
* Copyright 2002-2004 H. Peter Anvin
10
10
*/
11
11
12
-
#include <asm/simd.h>
13
12
#include <asm/vector.h>
14
-
#include <crypto/internal/simd.h>
15
13
#include <linux/raid/pq.h>
16
-
#include <linux/types.h>
17
14
#include "rvv.h"
18
15
19
16
#define NSIZE (riscv_v_vsize / 32) /* NSIZE = vlenb */
···
44
47
asm volatile (".option push\n"
45
48
".option arch,+v\n"
46
49
"vle8.v v0, (%[wp0])\n"
47
-
"vle8.v v1, (%[wp0])\n"
50
+
"vmv.v.v v1, v0\n"
48
51
".option pop\n"
49
52
: :
50
53
[wp0]"r"(&dptr[z0][d + 0 * NSIZE])
···
117
120
asm volatile (".option push\n"
118
121
".option arch,+v\n"
119
122
"vle8.v v0, (%[wp0])\n"
120
-
"vle8.v v1, (%[wp0])\n"
123
+
"vmv.v.v v1, v0\n"
121
124
".option pop\n"
122
125
: :
123
126
[wp0]"r"(&dptr[z0][d + 0 * NSIZE])
···
218
221
asm volatile (".option push\n"
219
222
".option arch,+v\n"
220
223
"vle8.v v0, (%[wp0])\n"
221
-
"vle8.v v1, (%[wp0])\n"
224
+
"vmv.v.v v1, v0\n"
222
225
"vle8.v v4, (%[wp1])\n"
223
-
"vle8.v v5, (%[wp1])\n"
226
+
"vmv.v.v v5, v4\n"
224
227
".option pop\n"
225
228
: :
226
229
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
···
310
313
asm volatile (".option push\n"
311
314
".option arch,+v\n"
312
315
"vle8.v v0, (%[wp0])\n"
313
-
"vle8.v v1, (%[wp0])\n"
316
+
"vmv.v.v v1, v0\n"
314
317
"vle8.v v4, (%[wp1])\n"
315
-
"vle8.v v5, (%[wp1])\n"
318
+
"vmv.v.v v5, v4\n"
316
319
".option pop\n"
317
320
: :
318
321
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
···
440
443
asm volatile (".option push\n"
441
444
".option arch,+v\n"
442
445
"vle8.v v0, (%[wp0])\n"
443
-
"vle8.v v1, (%[wp0])\n"
446
+
"vmv.v.v v1, v0\n"
444
447
"vle8.v v4, (%[wp1])\n"
445
-
"vle8.v v5, (%[wp1])\n"
448
+
"vmv.v.v v5, v4\n"
446
449
"vle8.v v8, (%[wp2])\n"
447
-
"vle8.v v9, (%[wp2])\n"
450
+
"vmv.v.v v9, v8\n"
448
451
"vle8.v v12, (%[wp3])\n"
449
-
"vle8.v v13, (%[wp3])\n"
452
+
"vmv.v.v v13, v12\n"
450
453
".option pop\n"
451
454
: :
452
455
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
···
566
569
asm volatile (".option push\n"
567
570
".option arch,+v\n"
568
571
"vle8.v v0, (%[wp0])\n"
569
-
"vle8.v v1, (%[wp0])\n"
572
+
"vmv.v.v v1, v0\n"
570
573
"vle8.v v4, (%[wp1])\n"
571
-
"vle8.v v5, (%[wp1])\n"
574
+
"vmv.v.v v5, v4\n"
572
575
"vle8.v v8, (%[wp2])\n"
573
-
"vle8.v v9, (%[wp2])\n"
576
+
"vmv.v.v v9, v8\n"
574
577
"vle8.v v12, (%[wp3])\n"
575
-
"vle8.v v13, (%[wp3])\n"
578
+
"vmv.v.v v13, v12\n"
576
579
".option pop\n"
577
580
: :
578
581
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
···
754
757
asm volatile (".option push\n"
755
758
".option arch,+v\n"
756
759
"vle8.v v0, (%[wp0])\n"
757
-
"vle8.v v1, (%[wp0])\n"
760
+
"vmv.v.v v1, v0\n"
758
761
"vle8.v v4, (%[wp1])\n"
759
-
"vle8.v v5, (%[wp1])\n"
762
+
"vmv.v.v v5, v4\n"
760
763
"vle8.v v8, (%[wp2])\n"
761
-
"vle8.v v9, (%[wp2])\n"
764
+
"vmv.v.v v9, v8\n"
762
765
"vle8.v v12, (%[wp3])\n"
763
-
"vle8.v v13, (%[wp3])\n"
766
+
"vmv.v.v v13, v12\n"
764
767
"vle8.v v16, (%[wp4])\n"
765
-
"vle8.v v17, (%[wp4])\n"
768
+
"vmv.v.v v17, v16\n"
766
769
"vle8.v v20, (%[wp5])\n"
767
-
"vle8.v v21, (%[wp5])\n"
770
+
"vmv.v.v v21, v20\n"
768
771
"vle8.v v24, (%[wp6])\n"
769
-
"vle8.v v25, (%[wp6])\n"
772
+
"vmv.v.v v25, v24\n"
770
773
"vle8.v v28, (%[wp7])\n"
771
-
"vle8.v v29, (%[wp7])\n"
774
+
"vmv.v.v v29, v28\n"
772
775
".option pop\n"
773
776
: :
774
777
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
···
948
951
asm volatile (".option push\n"
949
952
".option arch,+v\n"
950
953
"vle8.v v0, (%[wp0])\n"
951
-
"vle8.v v1, (%[wp0])\n"
954
+
"vmv.v.v v1, v0\n"
952
955
"vle8.v v4, (%[wp1])\n"
953
-
"vle8.v v5, (%[wp1])\n"
956
+
"vmv.v.v v5, v4\n"
954
957
"vle8.v v8, (%[wp2])\n"
955
-
"vle8.v v9, (%[wp2])\n"
958
+
"vmv.v.v v9, v8\n"
956
959
"vle8.v v12, (%[wp3])\n"
957
-
"vle8.v v13, (%[wp3])\n"
960
+
"vmv.v.v v13, v12\n"
958
961
"vle8.v v16, (%[wp4])\n"
959
-
"vle8.v v17, (%[wp4])\n"
962
+
"vmv.v.v v17, v16\n"
960
963
"vle8.v v20, (%[wp5])\n"
961
-
"vle8.v v21, (%[wp5])\n"
964
+
"vmv.v.v v21, v20\n"
962
965
"vle8.v v24, (%[wp6])\n"
963
-
"vle8.v v25, (%[wp6])\n"
966
+
"vmv.v.v v25, v24\n"
964
967
"vle8.v v28, (%[wp7])\n"
965
-
"vle8.v v29, (%[wp7])\n"
968
+
"vmv.v.v v29, v28\n"
966
969
".option pop\n"
967
970
: :
968
971
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
+3
-3
tools/arch/riscv/include/asm/csr.h
+3
-3
tools/arch/riscv/include/asm/csr.h
···
468
468
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
469
469
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
470
470
471
-
#ifdef __ASSEMBLY__
471
+
#ifdef __ASSEMBLER__
472
472
#define __ASM_STR(x) x
473
473
#else
474
474
#define __ASM_STR(x) #x
475
475
#endif
476
476
477
-
#ifndef __ASSEMBLY__
477
+
#ifndef __ASSEMBLER__
478
478
479
479
#define csr_swap(csr, val) \
480
480
({ \
···
536
536
: "memory"); \
537
537
})
538
538
539
-
#endif /* __ASSEMBLY__ */
539
+
#endif /* __ASSEMBLER__ */
540
540
541
541
#endif /* _ASM_RISCV_CSR_H */
+2
-2
tools/arch/riscv/include/asm/vdso/processor.h
+2
-2
tools/arch/riscv/include/asm/vdso/processor.h
···
2
2
#ifndef __ASM_VDSO_PROCESSOR_H
3
3
#define __ASM_VDSO_PROCESSOR_H
4
4
5
-
#ifndef __ASSEMBLY__
5
+
#ifndef __ASSEMBLER__
6
6
7
7
#include <asm-generic/barrier.h>
8
8
···
27
27
barrier();
28
28
}
29
29
30
-
#endif /* __ASSEMBLY__ */
30
+
#endif /* __ASSEMBLER__ */
31
31
32
32
#endif /* __ASM_VDSO_PROCESSOR_H */
+24
tools/testing/selftests/riscv/README
+24
tools/testing/selftests/riscv/README
···
1
+
KSelfTest RISC-V
2
+
================
3
+
4
+
- These tests are riscv specific and so not built or run but just skipped
5
+
completely when env-variable ARCH is found to be different than 'riscv'.
6
+
7
+
- Holding true the above, RISC-V KSFT tests can be run within the
8
+
KSelfTest framework using standard Linux top-level-makefile targets:
9
+
10
+
$ make TARGETS=riscv kselftest-clean
11
+
$ make TARGETS=riscv kselftest
12
+
13
+
or
14
+
15
+
$ make -C tools/testing/selftests TARGETS=riscv \
16
+
INSTALL_PATH=<your-installation-path> install
17
+
18
+
or, alternatively, only specific riscv/ subtargets can be picked:
19
+
20
+
$ make -C tools/testing/selftests TARGETS=riscv RISCV_SUBTARGETS="mm vector" \
21
+
INSTALL_PATH=<your-installation-path> install
22
+
23
+
Further details on building and running KSFT can be found in:
24
+
Documentation/dev-tools/kselftest.rst