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x86/decompressor: Pass pgtable address to trampoline directly

The only remaining use of the trampoline address by the trampoline
itself is deriving the page table address from it, and this involves
adding an offset of 0x0. So simplify this, and pass the new CR3 value
directly.

This makes the fact that the page table happens to be at the start of
the trampoline allocation an implementation detail of the caller.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230807162720.545787-15-ardb@kernel.org

authored by

Ard Biesheuvel and committed by
Borislav Petkov (AMD) cb83cece f97b67a7

+8 -11
+4 -4
arch/x86/boot/compressed/head_64.S
··· 521 521 * running in 64-bit mode. 522 522 * 523 523 * Return address is at the top of the stack (might be above 4G). 524 - * The first argument (EDI) contains the 32-bit addressable base of the 525 - * trampoline memory. 524 + * The first argument (EDI) contains the address of the temporary PGD level 525 + * page table in 32-bit addressable memory which will be programmed into 526 + * register CR3. 526 527 */ 527 528 .section ".rodata", "a", @progbits 528 529 SYM_CODE_START(trampoline_32bit_src) ··· 576 575 movl %eax, %cr0 577 576 578 577 /* Point CR3 to the trampoline's new top level page table */ 579 - leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%edi), %eax 580 - movl %eax, %cr3 578 + movl %edi, %cr3 581 579 582 580 /* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */ 583 581 movl $MSR_EFER, %ecx
-2
arch/x86/boot/compressed/pgtable.h
··· 3 3 4 4 #define TRAMPOLINE_32BIT_SIZE (2 * PAGE_SIZE) 5 5 6 - #define TRAMPOLINE_32BIT_PGTABLE_OFFSET 0 7 - 8 6 #define TRAMPOLINE_32BIT_CODE_OFFSET PAGE_SIZE 9 7 #define TRAMPOLINE_32BIT_CODE_SIZE 0xA0 10 8
+4 -5
arch/x86/boot/compressed/pgtable_64.c
··· 103 103 104 104 asmlinkage void configure_5level_paging(struct boot_params *bp) 105 105 { 106 - void (*toggle_la57)(void *trampoline); 106 + void (*toggle_la57)(void *cr3); 107 107 bool l5_required = false; 108 108 109 109 /* Initialize boot_params. Required for cmdline_find_option_bool(). */ ··· 174 174 * For 4- to 5-level paging transition, set up current CR3 as 175 175 * the first and the only entry in a new top-level page table. 176 176 */ 177 - trampoline_32bit[TRAMPOLINE_32BIT_PGTABLE_OFFSET] = __native_read_cr3() | _PAGE_TABLE_NOENC; 177 + *trampoline_32bit = __native_read_cr3() | _PAGE_TABLE_NOENC; 178 178 } else { 179 179 unsigned long src; 180 180 ··· 187 187 * may be above 4G. 188 188 */ 189 189 src = *(unsigned long *)__native_read_cr3() & PAGE_MASK; 190 - memcpy(trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long), 191 - (void *)src, PAGE_SIZE); 190 + memcpy(trampoline_32bit, (void *)src, PAGE_SIZE); 192 191 } 193 192 194 193 toggle_la57(trampoline_32bit); ··· 197 198 { 198 199 void *trampoline_pgtable; 199 200 200 - trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long); 201 + trampoline_pgtable = trampoline_32bit; 201 202 202 203 /* 203 204 * Move the top level page table out of trampoline memory,