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ASoC: Intel: Fix MCLK leaks and clean up error

aravindanilraj0702@gmail.com <aravindanilraj0702@gmail.com> says:

From: Aravind Anilraj <aravindanilraj0702@gmail.com>

This series fixes MCLK resource leaks in the platform_clock_control()
implementations for bytcr_rt5640, bytcr_rt5651, and cht_bsw_rt5672.

In the SND_SOC_DAPM_EVENT_ON() path, clk_prepare_enable() is called to
enable MCLK, but subsequent failures in codec clock configuration (eg:
*_prepare_and_enable_pll1() or snd_soc_dai_set_sysclk()) return without
disabling the clock, leaking a reference.

Patches 1-3 fix this by adding the missing clk_disable_unprepare() calls
in the relevant error paths, ensuring proper symmetry between enable and
disable operations within the EVENT_ON scope.

Patch 4 moves unrelated logging changes into a separate patch and
standardizes error messages.

Mark Brown cba9ce8c ccd7e53b

+11 -3
+3 -1
sound/soc/intel/boards/bytcr_rt5640.c
··· 285 285 if (SND_SOC_DAPM_EVENT_ON(event)) { 286 286 ret = clk_prepare_enable(priv->mclk); 287 287 if (ret < 0) { 288 - dev_err(card->dev, "could not configure MCLK state\n"); 288 + dev_err(card->dev, "could not configure MCLK state: %d\n", ret); 289 289 return ret; 290 290 } 291 291 ret = byt_rt5640_prepare_and_enable_pll1(codec_dai, 48000); 292 + if (ret < 0) 293 + clk_disable_unprepare(priv->mclk); 292 294 } else { 293 295 /* 294 296 * Set codec clock source to internal clock before
+3 -1
sound/soc/intel/boards/bytcr_rt5651.c
··· 205 205 if (SND_SOC_DAPM_EVENT_ON(event)) { 206 206 ret = clk_prepare_enable(priv->mclk); 207 207 if (ret < 0) { 208 - dev_err(card->dev, "could not configure MCLK state"); 208 + dev_err(card->dev, "could not configure MCLK state: %d\n", ret); 209 209 return ret; 210 210 } 211 211 ret = byt_rt5651_prepare_and_enable_pll1(codec_dai, 48000, 50); 212 + if (ret < 0) 213 + clk_disable_unprepare(priv->mclk); 212 214 } else { 213 215 /* 214 216 * Set codec clock source to internal clock before
+5 -1
sound/soc/intel/boards/cht_bsw_rt5672.c
··· 67 67 ret = clk_prepare_enable(ctx->mclk); 68 68 if (ret < 0) { 69 69 dev_err(card->dev, 70 - "could not configure MCLK state"); 70 + "could not configure MCLK state: %d\n", ret); 71 71 return ret; 72 72 } 73 73 } ··· 77 77 CHT_PLAT_CLK_3_HZ, 48000 * 512); 78 78 if (ret < 0) { 79 79 dev_err(card->dev, "can't set codec pll: %d\n", ret); 80 + if (ctx->mclk) 81 + clk_disable_unprepare(ctx->mclk); 80 82 return ret; 81 83 } 82 84 ··· 87 85 48000 * 512, SND_SOC_CLOCK_IN); 88 86 if (ret < 0) { 89 87 dev_err(card->dev, "can't set codec sysclk: %d\n", ret); 88 + if (ctx->mclk) 89 + clk_disable_unprepare(ctx->mclk); 90 90 return ret; 91 91 } 92 92 } else {