Merge tag 'omap-for-v5.19/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

+1 -1

arch/arm/boot/dts/am335x-baltos.dtsi

··· 285 285 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 286 286 regulator-name = "vdd_mpu"; 287 287 regulator-min-microvolt = <912500>; 288 - regulator-max-microvolt = <1312500>; 288 + regulator-max-microvolt = <1351500>; 289 289 regulator-boot-on; 290 290 regulator-always-on; 291 291 };

+316 -60

arch/arm/boot/dts/am335x-guardian.dts

··· 29 29 reg = <0x80000000 0x10000000>; /* 256 MB */ 30 30 }; 31 31 32 - gpio_keys { 32 + guardian_buttons: gpio-keys { 33 + pinctrl-names = "default"; 34 + pinctrl-0 = <&guardian_button_pins>; 33 35 compatible = "gpio-keys"; 34 36 #address-cells = <1>; 35 37 #size-cells = <0>; 36 - pinctrl-names = "default"; 37 - pinctrl-0 = <&gpio_keys_pins>; 38 38 39 - button21 { 39 + select-button { 40 + label = "guardian-select-button"; 41 + linux,code = <KEY_5>; 42 + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; 43 + wakeup-source; 44 + }; 45 + 46 + power-button { 40 47 label = "guardian-power-button"; 41 48 linux,code = <KEY_POWER>; 42 - gpios = <&gpio2 21 0>; 49 + gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; 43 50 wakeup-source; 44 51 }; 45 52 }; 46 53 47 - leds { 48 - compatible = "gpio-leds"; 54 + guardian_leds: gpio-leds { 49 55 pinctrl-names = "default"; 50 - pinctrl-0 = <&leds_pins>; 56 + pinctrl-0 = <&guardian_led_pins>; 57 + compatible = "gpio-leds"; 51 58 52 - led1 { 53 - label = "green:heartbeat"; 54 - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; 59 + life-led { 60 + label = "guardian:life-led"; 61 + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 55 62 linux,default-trigger = "heartbeat"; 56 63 default-state = "off"; 57 64 }; 65 + }; 58 66 59 - led2 { 60 - label = "green:mmc0"; 61 - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 62 - linux,default-trigger = "mmc0"; 63 - default-state = "off"; 64 - }; 67 + gpio-poweroff { 68 + compatible = "gpio-poweroff"; 69 + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 65 70 }; 66 71 67 72 panel { ··· 105 100 106 101 }; 107 102 108 - pwm7: dmtimer-pwm { 103 + guardian_beeper: dmtimer-pwm@7 { 109 104 compatible = "ti,omap-dmtimer-pwm"; 110 105 ti,timers = <&timer7>; 111 106 pinctrl-names = "default"; 112 - pinctrl-0 = <&dmtimer7_pins>; 107 + pinctrl-0 = <&guardian_beeper_pins>; 113 108 ti,clock-source = <0x01>; 114 109 }; 115 110 116 - vmmcsd_fixed: regulator-3v3 { 111 + vmmcsd_fixed: fixedregulator0 { 117 112 compatible = "regulator-fixed"; 118 113 regulator-name = "vmmcsd_fixed"; 119 114 regulator-min-microvolt = <3300000>; 120 115 regulator-max-microvolt = <3300000>; 116 + }; 117 + 118 + mt_keypad: mt_keypad@0 { 119 + compatible = "gpio-mt-keypad"; 120 + debounce-delay-ms = <10>; 121 + col-scan-delay-us = <2>; 122 + keypad,num-lines = <5>; 123 + linux,no-autorepeat; 124 + gpio-activelow; 125 + line-gpios = < 126 + &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/ 127 + &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/ 128 + &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/ 129 + &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/ 130 + &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/ 131 + >; 121 132 }; 122 133 }; 123 134 ··· 154 133 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 155 134 <1 IRQ_TYPE_NONE>; /* termcount */ 156 135 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 136 + ti,nand-xfer-type = "prefetch-dma"; 157 137 ti,nand-ecc-opt = "bch16"; 158 138 ti,elm-id = <&elm>; 159 139 nand-bus-width = <8>; 160 140 gpmc,device-width = <1>; 161 141 gpmc,sync-clk-ps = <0>; 162 142 gpmc,cs-on-ns = <0>; 163 - gpmc,cs-rd-off-ns = <44>; 164 - gpmc,cs-wr-off-ns = <44>; 165 - gpmc,adv-on-ns = <6>; 166 - gpmc,adv-rd-off-ns = <34>; 167 - gpmc,adv-wr-off-ns = <44>; 143 + gpmc,cs-rd-off-ns = <30>; 144 + gpmc,cs-wr-off-ns = <30>; 145 + gpmc,adv-on-ns = <0>; 146 + gpmc,adv-rd-off-ns = <30>; 147 + gpmc,adv-wr-off-ns = <30>; 168 148 gpmc,we-on-ns = <0>; 169 - gpmc,we-off-ns = <40>; 170 - gpmc,oe-on-ns = <0>; 171 - gpmc,oe-off-ns = <54>; 172 - gpmc,access-ns = <64>; 173 - gpmc,rd-cycle-ns = <82>; 174 - gpmc,wr-cycle-ns = <82>; 149 + gpmc,we-off-ns = <15>; 150 + gpmc,oe-on-ns = <1>; 151 + gpmc,oe-off-ns = <15>; 152 + gpmc,access-ns = <30>; 153 + gpmc,rd-cycle-ns = <30>; 154 + gpmc,wr-cycle-ns = <30>; 175 155 gpmc,bus-turnaround-ns = <0>; 176 156 gpmc,cycle2cycle-delay-ns = <0>; 177 157 gpmc,clk-activation-ns = <0>; 178 - gpmc,wr-access-ns = <40>; 158 + gpmc,wr-access-ns = <0>; 179 159 gpmc,wr-data-mux-bus-ns = <0>; 180 160 181 161 /* ··· 220 198 }; 221 199 222 200 partition@6 { 223 - label = "u-boot-env"; 224 - reg = <0x300000 0x40000>; 201 + label = "u-boot-2"; 202 + reg = <0x300000 0x100000>; 225 203 }; 226 204 227 205 partition@7 { 228 - label = "u-boot-env.backup1"; 229 - reg = <0x340000 0x40000>; 206 + label = "u-boot-2.backup1"; 207 + reg = <0x400000 0x100000>; 230 208 }; 231 209 232 210 partition@8 { 211 + label = "u-boot-env"; 212 + reg = <0x500000 0x40000>; 213 + }; 214 + 215 + partition@9 { 216 + label = "u-boot-env.backup1"; 217 + reg = <0x540000 0x40000>; 218 + }; 219 + 220 + partition@10 { 221 + label = "splash-screen"; 222 + reg = <0x580000 0x40000>; 223 + }; 224 + 225 + partition@11 { 233 226 label = "UBI"; 234 - reg = <0x380000 0x1fc80000>; 227 + reg = <0x5c0000 0x1fa40000>; 235 228 }; 236 229 }; 237 230 }; ··· 265 228 &lcdc { 266 229 blue-and-red-wiring = "crossed"; 267 230 status = "okay"; 231 + port { 232 + lcdc_0: endpoint@0 { 233 + remote-endpoint = <0>; 234 + }; 235 + }; 268 236 }; 269 237 270 238 &mmc1 { ··· 284 242 &rtc { 285 243 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 286 244 clock-names = "ext-clk", "int-clk"; 287 - system-power-controller; 288 245 }; 289 246 290 247 &spi0 { ··· 296 255 #include "tps65217.dtsi" 297 256 298 257 &tps { 258 + /* 259 + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only 260 + * mode") at poweroff. Most BeagleBone versions do not support RTC-only 261 + * mode and risk hardware damage if this mode is entered. 262 + * 263 + * For details, see linux-omap mailing list May 2015 thread 264 + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller 265 + * In particular, messages: 266 + * http://www.spinics.net/lists/linux-omap/msg118585.html 267 + * http://www.spinics.net/lists/linux-omap/msg118615.html 268 + * 269 + * You can override this later with 270 + * &tps { /delete-property/ ti,pmic-shutdown-controller; } 271 + * if you want to use RTC-only mode and made sure you are not affected 272 + * by the hardware problems. (Tip: double-check by performing a current 273 + * measurement after shutdown: it should be less than 1 mA.) 274 + */ 299 275 ti,pmic-shutdown-controller; 300 276 interrupt-parent = <&intc>; 301 277 interrupts = <7>; /* NMI */ 302 278 303 279 backlight { 304 280 isel = <1>; /* 1 - ISET1, 2 ISET2 */ 305 - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ 306 - default-brightness = <100>; 281 + fdim = <500>; /* TPS65217_BL_FDIM_500HZ */ 282 + default-brightness = <50>; 283 + /* 1(on) - enable current sink, while initialization */ 284 + /* 0(off) - disable current sink, while initialization */ 285 + isink-en = <1>; 307 286 }; 308 287 309 288 regulators { ··· 333 272 }; 334 273 335 274 dcdc2_reg: regulator@1 { 275 + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 336 276 regulator-name = "vdd_mpu"; 337 277 regulator-min-microvolt = <925000>; 338 278 regulator-max-microvolt = <1351500>; ··· 342 280 }; 343 281 344 282 dcdc3_reg: regulator@2 { 283 + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 345 284 regulator-name = "vdd_core"; 346 285 regulator-min-microvolt = <925000>; 347 286 regulator-max-microvolt = <1150000>; ··· 382 319 }; 383 320 }; 384 321 322 + &gpio0 { 323 + gpio-line-names = 324 + "", 325 + "", 326 + "", 327 + "", 328 + "", 329 + "", 330 + "", 331 + "", 332 + "", 333 + "", 334 + "", 335 + "", 336 + "", 337 + "", 338 + "", 339 + "", 340 + "", 341 + "", 342 + "", 343 + "", 344 + "", 345 + "", 346 + "", 347 + "", 348 + "", 349 + "", 350 + "", 351 + "", 352 + "", 353 + "MirxWakeup", 354 + "", 355 + ""; 356 + }; 357 + 358 + &gpio3 { 359 + ti,gpio-always-on; 360 + ti,no-reset-on-init; 361 + gpio-line-names = 362 + "", 363 + "MirxBtReset", 364 + "", 365 + "CcVolAdcEn", 366 + "MirxBlePause", 367 + "", 368 + "", 369 + "", 370 + "", 371 + "", 372 + "", 373 + "", 374 + "", 375 + "", 376 + "AspEn", 377 + "", 378 + "", 379 + "", 380 + "", 381 + "", 382 + "", 383 + "BatVolAdcEn", 384 + "", 385 + "", 386 + "", 387 + "", 388 + "", 389 + "", 390 + "", 391 + "", 392 + "", 393 + ""; 394 + }; 395 + 385 396 &uart0 { 386 397 pinctrl-names = "default"; 387 398 pinctrl-0 = <&uart0_pins>; 399 + status = "okay"; 400 + }; 401 + 402 + &uart2 { 403 + pinctrl-names = "default"; 404 + pinctrl-0 = <&uart2_pins>; 388 405 status = "okay"; 389 406 }; 390 407 ··· 474 331 475 332 &usb1 { 476 333 dr_mode = "host"; 334 + /delete-property/dmas; 335 + /delete-property/dma-names; 477 336 }; 478 337 479 338 &am33xx_pinmux { 480 339 pinctrl-names = "default"; 481 - pinctrl-0 = <&clkout2_pin &gpio_pins>; 340 + pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; 482 341 483 342 clkout2_pin: pinmux_clkout2_pin { 484 343 pinctrl-single,pins = < 344 + /* xdma_event_intr1.clkout2 */ 485 345 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) 486 346 >; 487 347 }; 488 348 489 - dmtimer7_pins: pinmux_dmtimer7_pins { 349 + guardian_interface_pins: pinmux_interface_pins { 490 350 pinctrl-single,pins = < 491 - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) 351 + /* ADC_BATSENSE_EN */ 352 + /* (A14) MCASP0_AHCLKx.gpio3[21] */ 353 + AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) 354 + /* ADC_COINCELL_EN */ 355 + /* (J16) MII1_TX_EN.gpio3[3] */ 356 + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) 357 + /* ASP_ENABLE */ 358 + /* (A13) MCASP0_ACLKx.gpio3[14] */ 359 + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) 360 + /* (D16) uart1_rxd.uart1_rxd */ 361 + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) 362 + /* (D15) uart1_txd.uart1_txd */ 363 + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) 364 + /*SWITCH-OFF_3V6*/ 365 + /* (M18) gpio0[1] */ 366 + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) 367 + /* MIRACULIX */ 368 + /* (H17) gmii1_crs.gpio3[1] */ 369 + AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) 370 + /* (H18) rmii1_refclk.gpio0[29] */ 371 + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) 372 + /* (J18) gmii1_txd3.gpio0[16] */ 373 + AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 ) 374 + /* (J17) gmii1_rxdv.gpio3[4] */ 375 + AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) 492 376 >; 493 377 }; 494 378 495 - gpio_keys_pins: pinmux_gpio_keys_pins { 379 + guardian_beeper_pins: pinmux_dmtimer7_pins { 496 380 pinctrl-single,pins = < 497 - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) 381 + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ 498 382 >; 499 383 }; 500 384 501 - gpio_pins: pinmux_gpio_pins { 385 + guardian_button_pins: pinmux_guardian_button_pins { 502 386 pinctrl-single,pins = < 503 - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) 504 - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) 387 + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ 388 + AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ 505 389 >; 506 390 }; 391 + 507 392 508 393 i2c0_pins: pinmux_i2c0_pins { 509 394 pinctrl-single,pins = < 510 - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) 511 - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) 395 + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 396 + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 397 + >; 398 + }; 399 + 400 + led_bl_pins: gpio_led_bl_pins { 401 + pinctrl-single,pins = < 402 + /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ 403 + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) 512 404 >; 513 405 }; 514 406 515 407 lcd_disen_pins: pinmux_lcd_disen_pins { 516 408 pinctrl-single,pins = < 409 + /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ 517 410 AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) 518 411 >; 519 412 }; 520 413 521 414 lcd_pins_default: pinmux_lcd_pins_default { 522 415 pinctrl-single,pins = < 416 + /* (U10) gpmc_ad8.lcd_data23 */ 523 417 AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 418 + /* (T10) gpmc_ad9.lcd_data22 */ 524 419 AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 420 + /* (T11) gpmc_ad10.lcd_data21 */ 525 421 AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 422 + /* (U12) gpmc_ad11.lcd_data20 */ 526 423 AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 424 + /* (T12) gpmc_ad12.lcd_data19 */ 527 425 AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 426 + /* (R12) gpmc_ad13.lcd_data18 */ 528 427 AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 428 + /* (V13) gpmc_ad14.lcd_data17 */ 529 429 AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 430 + /* (U13) gpmc_ad15.lcd_data16 */ 530 431 AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 432 + /* lcd_data0.lcd_data0 */ 531 433 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 434 + /* lcd_data1.lcd_data1 */ 532 435 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 436 + /* lcd_data2.lcd_data2 */ 533 437 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 438 + /* lcd_data3.lcd_data3 */ 534 439 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 440 + /* lcd_data4.lcd_data4 */ 535 441 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 442 + /* lcd_data5.lcd_data5 */ 536 443 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 444 + /* lcd_data6.lcd_data6 */ 537 445 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 446 + /* lcd_data7.lcd_data7 */ 538 447 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 448 + /* lcd_data8.lcd_data8 */ 539 449 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 450 + /* lcd_data9.lcd_data9 */ 540 451 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 452 + /* lcd_data10.lcd_data10 */ 541 453 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 454 + /* lcd_data11.lcd_data11 */ 542 455 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 456 + /* lcd_data12.lcd_data12 */ 543 457 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 458 + /* lcd_data13.lcd_data13 */ 544 459 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 460 + /* lcd_data14.lcd_data14 */ 545 461 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 462 + /* lcd_data15.lcd_data15 */ 546 463 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 464 + /* lcd_vsync.lcd_vsync */ 547 465 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 466 + /* lcd_hsync.lcd_hsync */ 548 467 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 468 + /* lcd_pclk.lcd_pclk */ 549 469 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 470 + /* lcd_ac_bias_en.lcd_ac_bias_en */ 550 471 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 551 472 >; 552 473 }; 553 474 554 475 lcd_pins_sleep: pinmux_lcd_pins_sleep { 555 476 pinctrl-single,pins = < 477 + /* lcd_data0.lcd_data0 */ 556 478 AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 479 + /* lcd_data1.lcd_data1 */ 557 480 AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 481 + /* lcd_data2.lcd_data2 */ 558 482 AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 483 + /* lcd_data3.lcd_data3 */ 559 484 AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 485 + /* lcd_data4.lcd_data4 */ 560 486 AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 487 + /* lcd_data5.lcd_data5 */ 561 488 AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 489 + /* lcd_data6.lcd_data6 */ 562 490 AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 491 + /* lcd_data7.lcd_data7 */ 563 492 AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 493 + /* lcd_data8.lcd_data8 */ 564 494 AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 495 + /* lcd_data9.lcd_data9 */ 565 496 AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 497 + /* lcd_data10.lcd_data10 */ 566 498 AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 499 + /* lcd_data11.lcd_data11 */ 567 500 AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 501 + /* lcd_data12.lcd_data12 */ 568 502 AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 503 + /* lcd_data13.lcd_data13 */ 569 504 AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 505 + /* lcd_data14.lcd_data14 */ 570 506 AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 507 + /* lcd_data15.lcd_data15 */ 571 508 AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 509 + /* lcd_vsync.lcd_vsync */ 572 510 AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 511 + /* lcd_hsync.lcd_hsync */ 573 512 AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 513 + /* lcd_pclk.lcd_pclk */ 574 514 AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 515 + /* lcd_ac_bias_en.lcd_ac_bias_en */ 575 516 AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 576 517 >; 577 518 }; 578 519 579 - leds_pins: pinmux_leds_pins { 520 + guardian_led_pins: pinmux_guardian_led_pins { 580 521 pinctrl-single,pins = < 581 - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) 582 - AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) 522 + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ 583 523 >; 584 524 }; 585 525 586 526 mmc1_pins: pinmux_mmc1_pins { 587 527 pinctrl-single,pins = < 588 - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) 589 - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) 590 - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) 591 - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) 592 - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) 593 - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) 594 - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) 528 + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ 529 + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ 530 + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ 531 + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ 532 + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ 533 + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ 534 + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ 595 535 >; 596 536 }; 597 537 598 538 spi0_pins: pinmux_spi0_pins { 599 539 pinctrl-single,pins = < 540 + /* SPI0_CLK - spi0_clk.spi */ 600 541 AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) 542 + /* SPI0_MOSI - spi0_d0.spi0 */ 601 543 AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) 544 + /* SPI0_MISO - spi0_d1.spi0 */ 602 545 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) 546 + /* SPI0_CS0 - spi */ 603 547 AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) 604 548 >; 605 549 }; 606 550 607 551 uart0_pins: pinmux_uart0_pins { 608 552 pinctrl-single,pins = < 553 + /* uart0_rxd.uart0_rxd */ 609 554 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) 555 + /* uart0_txd.uart0_txd */ 610 556 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) 557 + >; 558 + }; 559 + 560 + uart2_pins: pinmux_uart2_pins { 561 + pinctrl-single,pins = < 562 + /* K18 uart2_rxd.mirx_txd */ 563 + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) 564 + /* L18 uart2_txd.mirx_rxd */ 565 + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) 611 566 >; 612 567 }; 613 568 614 569 nandflash_pins: pinmux_nandflash_pins { 615 570 pinctrl-single,pins = < 571 + /* (U7) gpmc_ad0.gpmc_ad0 */ 616 572 AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) 573 + /* (V7) gpmc_ad1.gpmc_ad1 */ 617 574 AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) 575 + /* (R8) gpmc_ad2.gpmc_ad2 */ 618 576 AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) 577 + /* (T8) gpmc_ad3.gpmc_ad3 */ 619 578 AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) 579 + /* (U8) gpmc_ad4.gpmc_ad4 */ 620 580 AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) 581 + /* (V8) gpmc_ad5.gpmc_ad5 */ 621 582 AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) 583 + /* (R9) gpmc_ad6.gpmc_ad6 */ 622 584 AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) 585 + /* (T9) gpmc_ad7.gpmc_ad7 */ 623 586 AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) 587 + /* (T17) gpmc_wait0.gpmc_wait0 */ 624 588 AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) 589 + /* (U17) gpmc_wpn.gpmc_wpn */ 625 590 AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) 591 + /* (V6) gpmc_csn0.gpmc_csn0 */ 626 592 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) 593 + /* (R7) gpmc_advn_ale.gpmc_advn_ale */ 627 594 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) 595 + /* (T7) gpmc_oen_ren.gpmc_oen_ren */ 628 596 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) 597 + /* (U6) gpmc_wen.gpmc_wen */ 629 598 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) 599 + /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ 630 600 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) 631 601 >; 632 602 };

+238 -135

arch/arm/boot/dts/am33xx-clocks.dtsi

··· 5 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 6 */ 7 7 &scm_clocks { 8 - sys_clkin_ck: sys_clkin_ck@40 { 8 + sys_clkin_ck: clock-sys-clkin-22@40 { 9 9 #clock-cells = <0>; 10 10 compatible = "ti,mux-clock"; 11 + clock-output-names = "sys_clkin_ck"; 11 12 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 12 13 ti,bit-shift = <22>; 13 14 reg = <0x0040>; 14 15 }; 15 16 16 - adc_tsc_fck: adc_tsc_fck { 17 + adc_tsc_fck: clock-adc-tsc-fck { 17 18 #clock-cells = <0>; 18 19 compatible = "fixed-factor-clock"; 20 + clock-output-names = "adc_tsc_fck"; 19 21 clocks = <&sys_clkin_ck>; 20 22 clock-mult = <1>; 21 23 clock-div = <1>; 22 24 }; 23 25 24 - dcan0_fck: dcan0_fck { 26 + dcan0_fck: clock-dcan0-fck { 25 27 #clock-cells = <0>; 26 28 compatible = "fixed-factor-clock"; 29 + clock-output-names = "dcan0_fck"; 27 30 clocks = <&sys_clkin_ck>; 28 31 clock-mult = <1>; 29 32 clock-div = <1>; 30 33 }; 31 34 32 - dcan1_fck: dcan1_fck { 35 + dcan1_fck: clock-dcan1-fck { 33 36 #clock-cells = <0>; 34 37 compatible = "fixed-factor-clock"; 38 + clock-output-names = "dcan1_fck"; 35 39 clocks = <&sys_clkin_ck>; 36 40 clock-mult = <1>; 37 41 clock-div = <1>; 38 42 }; 39 43 40 - mcasp0_fck: mcasp0_fck { 44 + mcasp0_fck: clock-mcasp0-fck { 41 45 #clock-cells = <0>; 42 46 compatible = "fixed-factor-clock"; 47 + clock-output-names = "mcasp0_fck"; 43 48 clocks = <&sys_clkin_ck>; 44 49 clock-mult = <1>; 45 50 clock-div = <1>; 46 51 }; 47 52 48 - mcasp1_fck: mcasp1_fck { 53 + mcasp1_fck: clock-mcasp1-fck { 49 54 #clock-cells = <0>; 50 55 compatible = "fixed-factor-clock"; 56 + clock-output-names = "mcasp1_fck"; 51 57 clocks = <&sys_clkin_ck>; 52 58 clock-mult = <1>; 53 59 clock-div = <1>; 54 60 }; 55 61 56 - smartreflex0_fck: smartreflex0_fck { 62 + smartreflex0_fck: clock-smartreflex0-fck { 57 63 #clock-cells = <0>; 58 64 compatible = "fixed-factor-clock"; 65 + clock-output-names = "smartreflex0_fck"; 59 66 clocks = <&sys_clkin_ck>; 60 67 clock-mult = <1>; 61 68 clock-div = <1>; 62 69 }; 63 70 64 - smartreflex1_fck: smartreflex1_fck { 71 + smartreflex1_fck: clock-smartreflex1-fck { 65 72 #clock-cells = <0>; 66 73 compatible = "fixed-factor-clock"; 74 + clock-output-names = "smartreflex1_fck"; 67 75 clocks = <&sys_clkin_ck>; 68 76 clock-mult = <1>; 69 77 clock-div = <1>; 70 78 }; 71 79 72 - sha0_fck: sha0_fck { 80 + sha0_fck: clock-sha0-fck { 73 81 #clock-cells = <0>; 74 82 compatible = "fixed-factor-clock"; 83 + clock-output-names = "sha0_fck"; 75 84 clocks = <&sys_clkin_ck>; 76 85 clock-mult = <1>; 77 86 clock-div = <1>; 78 87 }; 79 88 80 - aes0_fck: aes0_fck { 89 + aes0_fck: clock-aes0-fck { 81 90 #clock-cells = <0>; 82 91 compatible = "fixed-factor-clock"; 92 + clock-output-names = "aes0_fck"; 83 93 clocks = <&sys_clkin_ck>; 84 94 clock-mult = <1>; 85 95 clock-div = <1>; 86 96 }; 87 97 88 - rng_fck: rng_fck { 98 + rng_fck: clock-rng-fck { 89 99 #clock-cells = <0>; 90 100 compatible = "fixed-factor-clock"; 101 + clock-output-names = "rng_fck"; 91 102 clocks = <&sys_clkin_ck>; 92 103 clock-mult = <1>; 93 104 clock-div = <1>; 94 105 }; 95 106 96 - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { 97 - #clock-cells = <0>; 98 - compatible = "ti,gate-clock"; 99 - clocks = <&l4ls_gclk>; 100 - ti,bit-shift = <0>; 101 - reg = <0x0664>; 102 - }; 107 + clock@664 { 108 + compatible = "ti,clksel"; 109 + reg = <0x664>; 110 + #clock-cells = <2>; 111 + #address-cells = <0>; 103 112 104 - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { 105 - #clock-cells = <0>; 106 - compatible = "ti,gate-clock"; 107 - clocks = <&l4ls_gclk>; 108 - ti,bit-shift = <1>; 109 - reg = <0x0664>; 110 - }; 113 + ehrpwm0_tbclk: clock-ehrpwm0-tbclk { 114 + #clock-cells = <0>; 115 + compatible = "ti,gate-clock"; 116 + clock-output-names = "ehrpwm0_tbclk"; 117 + clocks = <&l4ls_gclk>; 118 + ti,bit-shift = <0>; 119 + }; 111 120 112 - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { 113 - #clock-cells = <0>; 114 - compatible = "ti,gate-clock"; 115 - clocks = <&l4ls_gclk>; 116 - ti,bit-shift = <2>; 117 - reg = <0x0664>; 121 + ehrpwm1_tbclk: clock-ehrpwm1-tbclk { 122 + #clock-cells = <0>; 123 + compatible = "ti,gate-clock"; 124 + clock-output-names = "ehrpwm1_tbclk"; 125 + clocks = <&l4ls_gclk>; 126 + ti,bit-shift = <1>; 127 + }; 128 + 129 + ehrpwm2_tbclk: clock-ehrpwm2-tbclk { 130 + #clock-cells = <0>; 131 + compatible = "ti,gate-clock"; 132 + clock-output-names = "ehrpwm2_tbclk"; 133 + clocks = <&l4ls_gclk>; 134 + ti,bit-shift = <2>; 135 + }; 118 136 }; 119 137 }; 120 138 &prcm_clocks { 121 - clk_32768_ck: clk_32768_ck { 139 + clk_32768_ck: clock-clk-32768 { 122 140 #clock-cells = <0>; 123 141 compatible = "fixed-clock"; 142 + clock-output-names = "clk_32768_ck"; 124 143 clock-frequency = <32768>; 125 144 }; 126 145 127 - clk_rc32k_ck: clk_rc32k_ck { 146 + clk_rc32k_ck: clock-clk-rc32k { 128 147 #clock-cells = <0>; 129 148 compatible = "fixed-clock"; 149 + clock-output-names = "clk_rc32k_ck"; 130 150 clock-frequency = <32000>; 131 151 }; 132 152 133 - virt_19200000_ck: virt_19200000_ck { 153 + virt_19200000_ck: clock-virt-19200000 { 134 154 #clock-cells = <0>; 135 155 compatible = "fixed-clock"; 156 + clock-output-names = "virt_19200000_ck"; 136 157 clock-frequency = <19200000>; 137 158 }; 138 159 139 - virt_24000000_ck: virt_24000000_ck { 160 + virt_24000000_ck: clock-virt-24000000 { 140 161 #clock-cells = <0>; 141 162 compatible = "fixed-clock"; 163 + clock-output-names = "virt_24000000_ck"; 142 164 clock-frequency = <24000000>; 143 165 }; 144 166 145 - virt_25000000_ck: virt_25000000_ck { 167 + virt_25000000_ck: clock-virt-25000000 { 146 168 #clock-cells = <0>; 147 169 compatible = "fixed-clock"; 170 + clock-output-names = "virt_25000000_ck"; 148 171 clock-frequency = <25000000>; 149 172 }; 150 173 151 - virt_26000000_ck: virt_26000000_ck { 174 + virt_26000000_ck: clock-virt-26000000 { 152 175 #clock-cells = <0>; 153 176 compatible = "fixed-clock"; 177 + clock-output-names = "virt_26000000_ck"; 154 178 clock-frequency = <26000000>; 155 179 }; 156 180 157 - tclkin_ck: tclkin_ck { 181 + tclkin_ck: clock-tclkin { 158 182 #clock-cells = <0>; 159 183 compatible = "fixed-clock"; 184 + clock-output-names = "tclkin_ck"; 160 185 clock-frequency = <12000000>; 161 186 }; 162 187 163 - dpll_core_ck: dpll_core_ck@490 { 188 + dpll_core_ck: clock@490 { 164 189 #clock-cells = <0>; 165 190 compatible = "ti,am3-dpll-core-clock"; 191 + clock-output-names = "dpll_core_ck"; 166 192 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 167 193 reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; 168 194 }; 169 195 170 - dpll_core_x2_ck: dpll_core_x2_ck { 196 + dpll_core_x2_ck: clock-dpll-core-x2 { 171 197 #clock-cells = <0>; 172 198 compatible = "ti,am3-dpll-x2-clock"; 199 + clock-output-names = "dpll_core_x2_ck"; 173 200 clocks = <&dpll_core_ck>; 174 201 }; 175 202 176 - dpll_core_m4_ck: dpll_core_m4_ck@480 { 203 + dpll_core_m4_ck: clock-dpll-core-m4@480 { 177 204 #clock-cells = <0>; 178 205 compatible = "ti,divider-clock"; 206 + clock-output-names = "dpll_core_m4_ck"; 179 207 clocks = <&dpll_core_x2_ck>; 180 208 ti,max-div = <31>; 181 209 reg = <0x0480>; 182 210 ti,index-starts-at-one; 183 211 }; 184 212 185 - dpll_core_m5_ck: dpll_core_m5_ck@484 { 213 + dpll_core_m5_ck: clock-dpll-core-m5@484 { 186 214 #clock-cells = <0>; 187 215 compatible = "ti,divider-clock"; 216 + clock-output-names = "dpll_core_m5_ck"; 188 217 clocks = <&dpll_core_x2_ck>; 189 218 ti,max-div = <31>; 190 219 reg = <0x0484>; 191 220 ti,index-starts-at-one; 192 221 }; 193 222 194 - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { 223 + dpll_core_m6_ck: clock-dpll-core-m6@4d8 { 195 224 #clock-cells = <0>; 196 225 compatible = "ti,divider-clock"; 226 + clock-output-names = "dpll_core_m6_ck"; 197 227 clocks = <&dpll_core_x2_ck>; 198 228 ti,max-div = <31>; 199 229 reg = <0x04d8>; 200 230 ti,index-starts-at-one; 201 231 }; 202 232 203 - dpll_mpu_ck: dpll_mpu_ck@488 { 233 + dpll_mpu_ck: clock@488 { 204 234 #clock-cells = <0>; 205 235 compatible = "ti,am3-dpll-clock"; 236 + clock-output-names = "dpll_mpu_ck"; 206 237 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 207 238 reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; 208 239 }; 209 240 210 - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { 241 + dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { 211 242 #clock-cells = <0>; 212 243 compatible = "ti,divider-clock"; 244 + clock-output-names = "dpll_mpu_m2_ck"; 213 245 clocks = <&dpll_mpu_ck>; 214 246 ti,max-div = <31>; 215 247 reg = <0x04a8>; 216 248 ti,index-starts-at-one; 217 249 }; 218 250 219 - dpll_ddr_ck: dpll_ddr_ck@494 { 251 + dpll_ddr_ck: clock@494 { 220 252 #clock-cells = <0>; 221 253 compatible = "ti,am3-dpll-no-gate-clock"; 254 + clock-output-names = "dpll_ddr_ck"; 222 255 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 223 256 reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; 224 257 }; 225 258 226 - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { 259 + dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { 227 260 #clock-cells = <0>; 228 261 compatible = "ti,divider-clock"; 262 + clock-output-names = "dpll_ddr_m2_ck"; 229 263 clocks = <&dpll_ddr_ck>; 230 264 ti,max-div = <31>; 231 265 reg = <0x04a0>; 232 266 ti,index-starts-at-one; 233 267 }; 234 268 235 - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { 269 + dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { 236 270 #clock-cells = <0>; 237 271 compatible = "fixed-factor-clock"; 272 + clock-output-names = "dpll_ddr_m2_div2_ck"; 238 273 clocks = <&dpll_ddr_m2_ck>; 239 274 clock-mult = <1>; 240 275 clock-div = <2>; 241 276 }; 242 277 243 - dpll_disp_ck: dpll_disp_ck@498 { 278 + dpll_disp_ck: clock@498 { 244 279 #clock-cells = <0>; 245 280 compatible = "ti,am3-dpll-no-gate-clock"; 281 + clock-output-names = "dpll_disp_ck"; 246 282 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 247 283 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; 248 284 }; 249 285 250 - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { 286 + dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { 251 287 #clock-cells = <0>; 252 288 compatible = "ti,divider-clock"; 289 + clock-output-names = "dpll_disp_m2_ck"; 253 290 clocks = <&dpll_disp_ck>; 254 291 ti,max-div = <31>; 255 292 reg = <0x04a4>; ··· 294 257 ti,set-rate-parent; 295 258 }; 296 259 297 - dpll_per_ck: dpll_per_ck@48c { 260 + dpll_per_ck: clock@48c { 298 261 #clock-cells = <0>; 299 262 compatible = "ti,am3-dpll-no-gate-j-type-clock"; 263 + clock-output-names = "dpll_per_ck"; 300 264 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 301 265 reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; 302 266 }; 303 267 304 - dpll_per_m2_ck: dpll_per_m2_ck@4ac { 268 + dpll_per_m2_ck: clock-dpll-per-m2@4ac { 305 269 #clock-cells = <0>; 306 270 compatible = "ti,divider-clock"; 271 + clock-output-names = "dpll_per_m2_ck"; 307 272 clocks = <&dpll_per_ck>; 308 273 ti,max-div = <31>; 309 274 reg = <0x04ac>; 310 275 ti,index-starts-at-one; 311 276 }; 312 277 313 - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 278 + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { 314 279 #clock-cells = <0>; 315 280 compatible = "fixed-factor-clock"; 281 + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; 316 282 clocks = <&dpll_per_m2_ck>; 317 283 clock-mult = <1>; 318 284 clock-div = <4>; 319 285 }; 320 286 321 - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 287 + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { 322 288 #clock-cells = <0>; 323 289 compatible = "fixed-factor-clock"; 290 + clock-output-names = "dpll_per_m2_div4_ck"; 324 291 clocks = <&dpll_per_m2_ck>; 325 292 clock-mult = <1>; 326 293 clock-div = <4>; 327 294 }; 328 295 329 - clk_24mhz: clk_24mhz { 296 + clk_24mhz: clock-clk-24mhz { 330 297 #clock-cells = <0>; 331 298 compatible = "fixed-factor-clock"; 299 + clock-output-names = "clk_24mhz"; 332 300 clocks = <&dpll_per_m2_ck>; 333 301 clock-mult = <1>; 334 302 clock-div = <8>; 335 303 }; 336 304 337 - clkdiv32k_ck: clkdiv32k_ck { 305 + clkdiv32k_ck: clock-clkdiv32k { 338 306 #clock-cells = <0>; 339 307 compatible = "fixed-factor-clock"; 308 + clock-output-names = "clkdiv32k_ck"; 340 309 clocks = <&clk_24mhz>; 341 310 clock-mult = <1>; 342 311 clock-div = <732>; 343 312 }; 344 313 345 - l3_gclk: l3_gclk { 314 + l3_gclk: clock-l3-gclk { 346 315 #clock-cells = <0>; 347 316 compatible = "fixed-factor-clock"; 317 + clock-output-names = "l3_gclk"; 348 318 clocks = <&dpll_core_m4_ck>; 349 319 clock-mult = <1>; 350 320 clock-div = <1>; 351 321 }; 352 322 353 - pruss_ocp_gclk: pruss_ocp_gclk@530 { 323 + pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { 354 324 #clock-cells = <0>; 355 325 compatible = "ti,mux-clock"; 326 + clock-output-names = "pruss_ocp_gclk"; 356 327 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; 357 328 reg = <0x0530>; 358 329 }; 359 330 360 - mmu_fck: mmu_fck@914 { 331 + mmu_fck: clock-mmu-fck-1@914 { 361 332 #clock-cells = <0>; 362 333 compatible = "ti,gate-clock"; 334 + clock-output-names = "mmu_fck"; 363 335 clocks = <&dpll_core_m4_ck>; 364 336 ti,bit-shift = <1>; 365 337 reg = <0x0914>; 366 338 }; 367 339 368 - timer1_fck: timer1_fck@528 { 340 + timer1_fck: clock-timer1-fck@528 { 369 341 #clock-cells = <0>; 370 342 compatible = "ti,mux-clock"; 343 + clock-output-names = "timer1_fck"; 371 344 clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; 372 345 reg = <0x0528>; 373 346 }; 374 347 375 - timer2_fck: timer2_fck@508 { 348 + timer2_fck: clock-timer2-fck@508 { 376 349 #clock-cells = <0>; 377 350 compatible = "ti,mux-clock"; 351 + clock-output-names = "timer2_fck"; 378 352 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 379 353 reg = <0x0508>; 380 354 }; 381 355 382 - timer3_fck: timer3_fck@50c { 356 + timer3_fck: clock-timer3-fck@50c { 383 357 #clock-cells = <0>; 384 358 compatible = "ti,mux-clock"; 359 + clock-output-names = "timer3_fck"; 385 360 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 386 361 reg = <0x050c>; 387 362 }; 388 363 389 - timer4_fck: timer4_fck@510 { 364 + timer4_fck: clock-timer4-fck@510 { 390 365 #clock-cells = <0>; 391 366 compatible = "ti,mux-clock"; 367 + clock-output-names = "timer4_fck"; 392 368 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 393 369 reg = <0x0510>; 394 370 }; 395 371 396 - timer5_fck: timer5_fck@518 { 372 + timer5_fck: clock-timer5-fck@518 { 397 373 #clock-cells = <0>; 398 374 compatible = "ti,mux-clock"; 375 + clock-output-names = "timer5_fck"; 399 376 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 400 377 reg = <0x0518>; 401 378 }; 402 379 403 - timer6_fck: timer6_fck@51c { 380 + timer6_fck: clock-timer6-fck@51c { 404 381 #clock-cells = <0>; 405 382 compatible = "ti,mux-clock"; 383 + clock-output-names = "timer6_fck"; 406 384 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 407 385 reg = <0x051c>; 408 386 }; 409 387 410 - timer7_fck: timer7_fck@504 { 388 + timer7_fck: clock-timer7-fck@504 { 411 389 #clock-cells = <0>; 412 390 compatible = "ti,mux-clock"; 391 + clock-output-names = "timer7_fck"; 413 392 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 414 393 reg = <0x0504>; 415 394 }; 416 395 417 - usbotg_fck: usbotg_fck@47c { 396 + usbotg_fck: clock-usbotg-fck-8@47c { 418 397 #clock-cells = <0>; 419 398 compatible = "ti,gate-clock"; 399 + clock-output-names = "usbotg_fck"; 420 400 clocks = <&dpll_per_ck>; 421 401 ti,bit-shift = <8>; 422 402 reg = <0x047c>; 423 403 }; 424 404 425 - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 405 + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { 426 406 #clock-cells = <0>; 427 407 compatible = "fixed-factor-clock"; 408 + clock-output-names = "dpll_core_m4_div2_ck"; 428 409 clocks = <&dpll_core_m4_ck>; 429 410 clock-mult = <1>; 430 411 clock-div = <2>; 431 412 }; 432 413 433 - ieee5000_fck: ieee5000_fck@e4 { 414 + ieee5000_fck: clock-ieee5000-fck-1@e4 { 434 415 #clock-cells = <0>; 435 416 compatible = "ti,gate-clock"; 417 + clock-output-names = "ieee5000_fck"; 436 418 clocks = <&dpll_core_m4_div2_ck>; 437 419 ti,bit-shift = <1>; 438 420 reg = <0x00e4>; 439 421 }; 440 422 441 - wdt1_fck: wdt1_fck@538 { 423 + wdt1_fck: clock-wdt1-fck@538 { 442 424 #clock-cells = <0>; 443 425 compatible = "ti,mux-clock"; 426 + clock-output-names = "wdt1_fck"; 444 427 clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 445 428 reg = <0x0538>; 446 429 }; 447 430 448 - l4_rtc_gclk: l4_rtc_gclk { 431 + l4_rtc_gclk: clock-l4-rtc-gclk { 449 432 #clock-cells = <0>; 450 433 compatible = "fixed-factor-clock"; 434 + clock-output-names = "l4_rtc_gclk"; 451 435 clocks = <&dpll_core_m4_ck>; 452 436 clock-mult = <1>; 453 437 clock-div = <2>; 454 438 }; 455 439 456 - l4hs_gclk: l4hs_gclk { 440 + l4hs_gclk: clock-l4hs-gclk { 457 441 #clock-cells = <0>; 458 442 compatible = "fixed-factor-clock"; 443 + clock-output-names = "l4hs_gclk"; 459 444 clocks = <&dpll_core_m4_ck>; 460 445 clock-mult = <1>; 461 446 clock-div = <1>; 462 447 }; 463 448 464 - l3s_gclk: l3s_gclk { 449 + l3s_gclk: clock-l3s-gclk { 465 450 #clock-cells = <0>; 466 451 compatible = "fixed-factor-clock"; 452 + clock-output-names = "l3s_gclk"; 467 453 clocks = <&dpll_core_m4_div2_ck>; 468 454 clock-mult = <1>; 469 455 clock-div = <1>; 470 456 }; 471 457 472 - l4fw_gclk: l4fw_gclk { 458 + l4fw_gclk: clock-l4fw-gclk { 473 459 #clock-cells = <0>; 474 460 compatible = "fixed-factor-clock"; 461 + clock-output-names = "l4fw_gclk"; 475 462 clocks = <&dpll_core_m4_div2_ck>; 476 463 clock-mult = <1>; 477 464 clock-div = <1>; 478 465 }; 479 466 480 - l4ls_gclk: l4ls_gclk { 467 + l4ls_gclk: clock-l4ls-gclk { 481 468 #clock-cells = <0>; 482 469 compatible = "fixed-factor-clock"; 470 + clock-output-names = "l4ls_gclk"; 483 471 clocks = <&dpll_core_m4_div2_ck>; 484 472 clock-mult = <1>; 485 473 clock-div = <1>; 486 474 }; 487 475 488 - sysclk_div_ck: sysclk_div_ck { 476 + sysclk_div_ck: clock-sysclk-div { 489 477 #clock-cells = <0>; 490 478 compatible = "fixed-factor-clock"; 479 + clock-output-names = "sysclk_div_ck"; 491 480 clocks = <&dpll_core_m4_ck>; 492 481 clock-mult = <1>; 493 482 clock-div = <1>; 494 483 }; 495 484 496 - cpsw_125mhz_gclk: cpsw_125mhz_gclk { 485 + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { 497 486 #clock-cells = <0>; 498 487 compatible = "fixed-factor-clock"; 488 + clock-output-names = "cpsw_125mhz_gclk"; 499 489 clocks = <&dpll_core_m5_ck>; 500 490 clock-mult = <1>; 501 491 clock-div = <2>; 502 492 }; 503 493 504 - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { 494 + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { 505 495 #clock-cells = <0>; 506 496 compatible = "ti,mux-clock"; 497 + clock-output-names = "cpsw_cpts_rft_clk"; 507 498 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; 508 499 reg = <0x0520>; 509 500 }; 510 501 511 - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { 502 + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { 512 503 #clock-cells = <0>; 513 504 compatible = "ti,mux-clock"; 505 + clock-output-names = "gpio0_dbclk_mux_ck"; 514 506 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 515 507 reg = <0x053c>; 516 508 }; 517 509 518 - lcd_gclk: lcd_gclk@534 { 510 + lcd_gclk: clock-lcd-gclk@534 { 519 511 #clock-cells = <0>; 520 512 compatible = "ti,mux-clock"; 513 + clock-output-names = "lcd_gclk"; 521 514 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 522 515 reg = <0x0534>; 523 516 ti,set-rate-parent; 524 517 }; 525 518 526 - mmc_clk: mmc_clk { 519 + mmc_clk: clock-mmc { 527 520 #clock-cells = <0>; 528 521 compatible = "fixed-factor-clock"; 522 + clock-output-names = "mmc_clk"; 529 523 clocks = <&dpll_per_m2_ck>; 530 524 clock-mult = <1>; 531 525 clock-div = <2>; 532 526 }; 533 527 534 - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { 535 - #clock-cells = <0>; 536 - compatible = "ti,mux-clock"; 537 - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; 538 - ti,bit-shift = <1>; 539 - reg = <0x052c>; 528 + clock@52c { 529 + compatible = "ti,clksel"; 530 + reg = <0x52c>; 531 + #clock-cells = <2>; 532 + #address-cells = <0>; 533 + 534 + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { 535 + #clock-cells = <0>; 536 + compatible = "ti,mux-clock"; 537 + clock-output-names = "gfx_fclk_clksel_ck"; 538 + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; 539 + ti,bit-shift = <1>; 540 + }; 541 + 542 + gfx_fck_div_ck: clock-gfx-fck-div { 543 + #clock-cells = <0>; 544 + compatible = "ti,divider-clock"; 545 + clock-output-names = "gfx_fck_div_ck"; 546 + clocks = <&gfx_fclk_clksel_ck>; 547 + ti,max-div = <2>; 548 + }; 540 549 }; 541 550 542 - gfx_fck_div_ck: gfx_fck_div_ck@52c { 543 - #clock-cells = <0>; 544 - compatible = "ti,divider-clock"; 545 - clocks = <&gfx_fclk_clksel_ck>; 546 - reg = <0x052c>; 547 - ti,max-div = <2>; 548 - }; 551 + clock@700 { 552 + compatible = "ti,clksel"; 553 + reg = <0x700>; 554 + #clock-cells = <2>; 555 + #address-cells = <0>; 549 556 550 - sysclkout_pre_ck: sysclkout_pre_ck@700 { 551 - #clock-cells = <0>; 552 - compatible = "ti,mux-clock"; 553 - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; 554 - reg = <0x0700>; 555 - }; 557 + sysclkout_pre_ck: clock-sysclkout-pre { 558 + #clock-cells = <0>; 559 + compatible = "ti,mux-clock"; 560 + clock-output-names = "sysclkout_pre_ck"; 561 + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; 562 + }; 556 563 557 - clkout2_div_ck: clkout2_div_ck@700 { 558 - #clock-cells = <0>; 559 - compatible = "ti,divider-clock"; 560 - clocks = <&sysclkout_pre_ck>; 561 - ti,bit-shift = <3>; 562 - ti,max-div = <8>; 563 - reg = <0x0700>; 564 - }; 564 + clkout2_div_ck: clock-clkout2-div { 565 + #clock-cells = <0>; 566 + compatible = "ti,divider-clock"; 567 + clock-output-names = "clkout2_div_ck"; 568 + clocks = <&sysclkout_pre_ck>; 569 + ti,bit-shift = <3>; 570 + ti,max-div = <8>; 571 + }; 565 572 566 - clkout2_ck: clkout2_ck@700 { 567 - #clock-cells = <0>; 568 - compatible = "ti,gate-clock"; 569 - clocks = <&clkout2_div_ck>; 570 - ti,bit-shift = <7>; 571 - reg = <0x0700>; 573 + clkout2_ck: clock-clkout2 { 574 + #clock-cells = <0>; 575 + compatible = "ti,gate-clock"; 576 + clock-output-names = "clkout2_ck"; 577 + clocks = <&clkout2_div_ck>; 578 + ti,bit-shift = <7>; 579 + }; 572 580 }; 573 581 }; 574 582 575 583 &prcm { 576 - per_cm: per-cm@0 { 584 + per_cm: clock@0 { 577 585 compatible = "ti,omap4-cm"; 586 + clock-output-names = "per_cm"; 578 587 reg = <0x0 0x400>; 579 588 #address-cells = <1>; 580 589 #size-cells = <1>; 581 590 ranges = <0 0x0 0x400>; 582 591 583 - l4ls_clkctrl: l4ls-clkctrl@38 { 592 + l4ls_clkctrl: clock@38 { 584 593 compatible = "ti,clkctrl"; 594 + clock-output-names = "l4ls_clkctrl"; 585 595 reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; 586 596 #clock-cells = <2>; 587 597 }; 588 598 589 - l3s_clkctrl: l3s-clkctrl@1c { 599 + l3s_clkctrl: clock@1c { 590 600 compatible = "ti,clkctrl"; 601 + clock-output-names = "l3s_clkctrl"; 591 602 reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; 592 603 #clock-cells = <2>; 593 604 }; 594 605 595 - l3_clkctrl: l3-clkctrl@24 { 606 + l3_clkctrl: clock@24 { 596 607 compatible = "ti,clkctrl"; 608 + clock-output-names = "l3_clkctrl"; 597 609 reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; 598 610 #clock-cells = <2>; 599 611 }; 600 612 601 - l4hs_clkctrl: l4hs-clkctrl@120 { 613 + l4hs_clkctrl: clock@120 { 602 614 compatible = "ti,clkctrl"; 615 + clock-output-names = "l4hs_clkctrl"; 603 616 reg = <0x120 0x4>; 604 617 #clock-cells = <2>; 605 618 }; 606 619 607 - pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { 620 + pruss_ocp_clkctrl: clock@e8 { 608 621 compatible = "ti,clkctrl"; 622 + clock-output-names = "pruss_ocp_clkctrl"; 609 623 reg = <0xe8 0x4>; 610 624 #clock-cells = <2>; 611 625 }; 612 626 613 - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { 627 + cpsw_125mhz_clkctrl: clock@0 { 614 628 compatible = "ti,clkctrl"; 629 + clock-output-names = "cpsw_125mhz_clkctrl"; 615 630 reg = <0x0 0x18>; 616 631 #clock-cells = <2>; 617 632 }; 618 633 619 - lcdc_clkctrl: lcdc-clkctrl@18 { 634 + lcdc_clkctrl: clock@18 { 620 635 compatible = "ti,clkctrl"; 636 + clock-output-names = "lcdc_clkctrl"; 621 637 reg = <0x18 0x4>; 622 638 #clock-cells = <2>; 623 639 }; 624 640 625 - clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { 641 + clk_24mhz_clkctrl: clock@14c { 626 642 compatible = "ti,clkctrl"; 643 + clock-output-names = "clk_24mhz_clkctrl"; 627 644 reg = <0x14c 0x4>; 628 645 #clock-cells = <2>; 629 646 }; 630 647 }; 631 648 632 - wkup_cm: wkup-cm@400 { 649 + wkup_cm: clock@400 { 633 650 compatible = "ti,omap4-cm"; 651 + clock-output-names = "wkup_cm"; 634 652 reg = <0x400 0x100>; 635 653 #address-cells = <1>; 636 654 #size-cells = <1>; 637 655 ranges = <0 0x400 0x100>; 638 656 639 - l4_wkup_clkctrl: l4-wkup-clkctrl@0 { 657 + l4_wkup_clkctrl: clock@0 { 640 658 compatible = "ti,clkctrl"; 659 + clock-output-names = "l4_wkup_clkctrl"; 641 660 reg = <0x0 0x10>, <0xb4 0x24>; 642 661 #clock-cells = <2>; 643 662 }; 644 663 645 - l3_aon_clkctrl: l3-aon-clkctrl@14 { 664 + l3_aon_clkctrl: clock@14 { 646 665 compatible = "ti,clkctrl"; 666 + clock-output-names = "l3_aon_clkctrl"; 647 667 reg = <0x14 0x4>; 648 668 #clock-cells = <2>; 649 669 }; 650 670 651 - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { 671 + l4_wkup_aon_clkctrl: clock@b0 { 652 672 compatible = "ti,clkctrl"; 673 + clock-output-names = "l4_wkup_aon_clkctrl"; 653 674 reg = <0xb0 0x4>; 654 675 #clock-cells = <2>; 655 676 }; 656 677 }; 657 678 658 - mpu_cm: mpu-cm@600 { 679 + mpu_cm: clock@600 { 659 680 compatible = "ti,omap4-cm"; 681 + clock-output-names = "mpu_cm"; 660 682 reg = <0x600 0x100>; 661 683 #address-cells = <1>; 662 684 #size-cells = <1>; 663 685 ranges = <0 0x600 0x100>; 664 686 665 - mpu_clkctrl: mpu-clkctrl@0 { 687 + mpu_clkctrl: clock@0 { 666 688 compatible = "ti,clkctrl"; 689 + clock-output-names = "mpu_clkctrl"; 667 690 reg = <0x0 0x8>; 668 691 #clock-cells = <2>; 669 692 }; 670 693 }; 671 694 672 - l4_rtc_cm: l4-rtc-cm@800 { 695 + l4_rtc_cm: clock@800 { 673 696 compatible = "ti,omap4-cm"; 697 + clock-output-names = "l4_rtc_cm"; 674 698 reg = <0x800 0x100>; 675 699 #address-cells = <1>; 676 700 #size-cells = <1>; 677 701 ranges = <0 0x800 0x100>; 678 702 679 - l4_rtc_clkctrl: l4-rtc-clkctrl@0 { 703 + l4_rtc_clkctrl: clock@0 { 680 704 compatible = "ti,clkctrl"; 705 + clock-output-names = "l4_rtc_clkctrl"; 681 706 reg = <0x0 0x4>; 682 707 #clock-cells = <2>; 683 708 }; 684 709 }; 685 710 686 - gfx_l3_cm: gfx-l3-cm@900 { 711 + gfx_l3_cm: clock@900 { 687 712 compatible = "ti,omap4-cm"; 713 + clock-output-names = "gfx_l3_cm"; 688 714 reg = <0x900 0x100>; 689 715 #address-cells = <1>; 690 716 #size-cells = <1>; 691 717 ranges = <0 0x900 0x100>; 692 718 693 - gfx_l3_clkctrl: gfx-l3-clkctrl@0 { 719 + gfx_l3_clkctrl: clock@0 { 694 720 compatible = "ti,clkctrl"; 721 + clock-output-names = "gfx_l3_clkctrl"; 695 722 reg = <0x0 0x8>; 696 723 #clock-cells = <2>; 697 724 }; 698 725 }; 699 726 700 - l4_cefuse_cm: l4-cefuse-cm@a00 { 727 + l4_cefuse_cm: clock@a00 { 701 728 compatible = "ti,omap4-cm"; 729 + clock-output-names = "l4_cefuse_cm"; 702 730 reg = <0xa00 0x100>; 703 731 #address-cells = <1>; 704 732 #size-cells = <1>; 705 733 ranges = <0 0xa00 0x100>; 706 734 707 - l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { 735 + l4_cefuse_clkctrl: clock@0 { 708 736 compatible = "ti,clkctrl"; 737 + clock-output-names = "l4_cefuse_clkctrl"; 709 738 reg = <0x0 0x24>; 710 739 #clock-cells = <2>; 711 740 };

+226 -113

arch/arm/boot/dts/am43xx-clocks.dtsi

··· 5 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 6 */ 7 7 &scm_clocks { 8 - sys_clkin_ck: sys_clkin_ck@40 { 8 + sys_clkin_ck: clock-sys-clkin-31@40 { 9 9 #clock-cells = <0>; 10 10 compatible = "ti,mux-clock"; 11 + clock-output-names = "sys_clkin_ck"; 11 12 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; 12 13 ti,bit-shift = <31>; 13 14 reg = <0x0040>; 14 15 }; 15 16 16 - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { 17 + crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { 17 18 #clock-cells = <0>; 18 19 compatible = "ti,mux-clock"; 20 + clock-output-names = "crystal_freq_sel_ck"; 19 21 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 20 22 ti,bit-shift = <29>; 21 23 reg = <0x0040>; 22 24 }; 23 25 24 - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { 26 + sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { 25 27 #clock-cells = <0>; 26 28 compatible = "ti,mux-clock"; 29 + clock-output-names = "sysboot_freq_sel_ck"; 27 30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 28 31 ti,bit-shift = <22>; 29 32 reg = <0x0040>; 30 33 }; 31 34 32 - adc_tsc_fck: adc_tsc_fck { 35 + adc_tsc_fck: clock-adc-tsc-fck { 33 36 #clock-cells = <0>; 34 37 compatible = "fixed-factor-clock"; 38 + clock-output-names = "adc_tsc_fck"; 35 39 clocks = <&sys_clkin_ck>; 36 40 clock-mult = <1>; 37 41 clock-div = <1>; 38 42 }; 39 43 40 - dcan0_fck: dcan0_fck { 44 + dcan0_fck: clock-dcan0-fck { 41 45 #clock-cells = <0>; 42 46 compatible = "fixed-factor-clock"; 47 + clock-output-names = "dcan0_fck"; 43 48 clocks = <&sys_clkin_ck>; 44 49 clock-mult = <1>; 45 50 clock-div = <1>; 46 51 }; 47 52 48 - dcan1_fck: dcan1_fck { 53 + dcan1_fck: clock-dcan1-fck { 49 54 #clock-cells = <0>; 50 55 compatible = "fixed-factor-clock"; 56 + clock-output-names = "dcan1_fck"; 51 57 clocks = <&sys_clkin_ck>; 52 58 clock-mult = <1>; 53 59 clock-div = <1>; 54 60 }; 55 61 56 - mcasp0_fck: mcasp0_fck { 62 + mcasp0_fck: clock-mcasp0-fck { 57 63 #clock-cells = <0>; 58 64 compatible = "fixed-factor-clock"; 65 + clock-output-names = "mcasp0_fck"; 59 66 clocks = <&sys_clkin_ck>; 60 67 clock-mult = <1>; 61 68 clock-div = <1>; 62 69 }; 63 70 64 - mcasp1_fck: mcasp1_fck { 71 + mcasp1_fck: clock-mcasp1-fck { 65 72 #clock-cells = <0>; 66 73 compatible = "fixed-factor-clock"; 74 + clock-output-names = "mcasp1_fck"; 67 75 clocks = <&sys_clkin_ck>; 68 76 clock-mult = <1>; 69 77 clock-div = <1>; 70 78 }; 71 79 72 - smartreflex0_fck: smartreflex0_fck { 80 + smartreflex0_fck: clock-smartreflex0-fck { 73 81 #clock-cells = <0>; 74 82 compatible = "fixed-factor-clock"; 83 + clock-output-names = "smartreflex0_fck"; 75 84 clocks = <&sys_clkin_ck>; 76 85 clock-mult = <1>; 77 86 clock-div = <1>; 78 87 }; 79 88 80 - smartreflex1_fck: smartreflex1_fck { 89 + smartreflex1_fck: clock-smartreflex1-fck { 81 90 #clock-cells = <0>; 82 91 compatible = "fixed-factor-clock"; 92 + clock-output-names = "smartreflex1_fck"; 83 93 clocks = <&sys_clkin_ck>; 84 94 clock-mult = <1>; 85 95 clock-div = <1>; 86 96 }; 87 97 88 - sha0_fck: sha0_fck { 98 + sha0_fck: clock-sha0-fck { 89 99 #clock-cells = <0>; 90 100 compatible = "fixed-factor-clock"; 101 + clock-output-names = "sha0_fck"; 91 102 clocks = <&sys_clkin_ck>; 92 103 clock-mult = <1>; 93 104 clock-div = <1>; 94 105 }; 95 106 96 - aes0_fck: aes0_fck { 107 + aes0_fck: clock-aes0-fck { 97 108 #clock-cells = <0>; 98 109 compatible = "fixed-factor-clock"; 110 + clock-output-names = "aes0_fck"; 99 111 clocks = <&sys_clkin_ck>; 100 112 clock-mult = <1>; 101 113 clock-div = <1>; 102 114 }; 103 115 104 - rng_fck: rng_fck { 116 + rng_fck: clock-rng-fck { 105 117 #clock-cells = <0>; 106 118 compatible = "fixed-factor-clock"; 119 + clock-output-names = "rng_fck"; 107 120 clocks = <&sys_clkin_ck>; 108 121 clock-mult = <1>; 109 122 clock-div = <1>; 110 123 }; 111 124 112 - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { 125 + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { 113 126 #clock-cells = <0>; 114 127 compatible = "ti,gate-clock"; 128 + clock-output-names = "ehrpwm0_tbclk"; 115 129 clocks = <&l4ls_gclk>; 116 130 ti,bit-shift = <0>; 117 131 reg = <0x0664>; 118 132 }; 119 133 120 - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { 134 + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { 121 135 #clock-cells = <0>; 122 136 compatible = "ti,gate-clock"; 137 + clock-output-names = "ehrpwm1_tbclk"; 123 138 clocks = <&l4ls_gclk>; 124 139 ti,bit-shift = <1>; 125 140 reg = <0x0664>; 126 141 }; 127 142 128 - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { 143 + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { 129 144 #clock-cells = <0>; 130 145 compatible = "ti,gate-clock"; 146 + clock-output-names = "ehrpwm2_tbclk"; 131 147 clocks = <&l4ls_gclk>; 132 148 ti,bit-shift = <2>; 133 149 reg = <0x0664>; 134 150 }; 135 151 136 - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { 152 + ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { 137 153 #clock-cells = <0>; 138 154 compatible = "ti,gate-clock"; 155 + clock-output-names = "ehrpwm3_tbclk"; 139 156 clocks = <&l4ls_gclk>; 140 157 ti,bit-shift = <4>; 141 158 reg = <0x0664>; 142 159 }; 143 160 144 - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { 161 + ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { 145 162 #clock-cells = <0>; 146 163 compatible = "ti,gate-clock"; 164 + clock-output-names = "ehrpwm4_tbclk"; 147 165 clocks = <&l4ls_gclk>; 148 166 ti,bit-shift = <5>; 149 167 reg = <0x0664>; 150 168 }; 151 169 152 - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { 170 + ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { 153 171 #clock-cells = <0>; 154 172 compatible = "ti,gate-clock"; 173 + clock-output-names = "ehrpwm5_tbclk"; 155 174 clocks = <&l4ls_gclk>; 156 175 ti,bit-shift = <6>; 157 176 reg = <0x0664>; 158 177 }; 159 178 }; 160 179 &prcm_clocks { 161 - clk_32768_ck: clk_32768_ck { 180 + clk_32768_ck: clock-clk-32768 { 162 181 #clock-cells = <0>; 163 182 compatible = "fixed-clock"; 183 + clock-output-names = "clk_32768_ck"; 164 184 clock-frequency = <32768>; 165 185 }; 166 186 167 - clk_rc32k_ck: clk_rc32k_ck { 187 + clk_rc32k_ck: clock-clk-rc32k { 168 188 #clock-cells = <0>; 169 189 compatible = "fixed-clock"; 190 + clock-output-names = "clk_rc32k_ck"; 170 191 clock-frequency = <32768>; 171 192 }; 172 193 173 - virt_19200000_ck: virt_19200000_ck { 194 + virt_19200000_ck: clock-virt-19200000 { 174 195 #clock-cells = <0>; 175 196 compatible = "fixed-clock"; 197 + clock-output-names = "virt_19200000_ck"; 176 198 clock-frequency = <19200000>; 177 199 }; 178 200 179 - virt_24000000_ck: virt_24000000_ck { 201 + virt_24000000_ck: clock-virt-24000000 { 180 202 #clock-cells = <0>; 181 203 compatible = "fixed-clock"; 204 + clock-output-names = "virt_24000000_ck"; 182 205 clock-frequency = <24000000>; 183 206 }; 184 207 185 - virt_25000000_ck: virt_25000000_ck { 208 + virt_25000000_ck: clock-virt-25000000 { 186 209 #clock-cells = <0>; 187 210 compatible = "fixed-clock"; 211 + clock-output-names = "virt_25000000_ck"; 188 212 clock-frequency = <25000000>; 189 213 }; 190 214 191 - virt_26000000_ck: virt_26000000_ck { 215 + virt_26000000_ck: clock-virt-26000000 { 192 216 #clock-cells = <0>; 193 217 compatible = "fixed-clock"; 218 + clock-output-names = "virt_26000000_ck"; 194 219 clock-frequency = <26000000>; 195 220 }; 196 221 197 - tclkin_ck: tclkin_ck { 222 + tclkin_ck: clock-tclkin { 198 223 #clock-cells = <0>; 199 224 compatible = "fixed-clock"; 225 + clock-output-names = "tclkin_ck"; 200 226 clock-frequency = <26000000>; 201 227 }; 202 228 203 - dpll_core_ck: dpll_core_ck@2d20 { 229 + dpll_core_ck: clock@2d20 { 204 230 #clock-cells = <0>; 205 231 compatible = "ti,am3-dpll-core-clock"; 232 + clock-output-names = "dpll_core_ck"; 206 233 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 207 234 reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; 208 235 }; 209 236 210 - dpll_core_x2_ck: dpll_core_x2_ck { 237 + dpll_core_x2_ck: clock-dpll-core-x2 { 211 238 #clock-cells = <0>; 212 239 compatible = "ti,am3-dpll-x2-clock"; 240 + clock-output-names = "dpll_core_x2_ck"; 213 241 clocks = <&dpll_core_ck>; 214 242 }; 215 243 216 - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { 244 + dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { 217 245 #clock-cells = <0>; 218 246 compatible = "ti,divider-clock"; 247 + clock-output-names = "dpll_core_m4_ck"; 219 248 clocks = <&dpll_core_x2_ck>; 220 249 ti,max-div = <31>; 221 250 ti,autoidle-shift = <8>; ··· 253 224 ti,invert-autoidle-bit; 254 225 }; 255 226 256 - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { 227 + dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { 257 228 #clock-cells = <0>; 258 229 compatible = "ti,divider-clock"; 230 + clock-output-names = "dpll_core_m5_ck"; 259 231 clocks = <&dpll_core_x2_ck>; 260 232 ti,max-div = <31>; 261 233 ti,autoidle-shift = <8>; ··· 265 235 ti,invert-autoidle-bit; 266 236 }; 267 237 268 - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { 238 + dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { 269 239 #clock-cells = <0>; 270 240 compatible = "ti,divider-clock"; 241 + clock-output-names = "dpll_core_m6_ck"; 271 242 clocks = <&dpll_core_x2_ck>; 272 243 ti,max-div = <31>; 273 244 ti,autoidle-shift = <8>; ··· 277 246 ti,invert-autoidle-bit; 278 247 }; 279 248 280 - dpll_mpu_ck: dpll_mpu_ck@2d60 { 249 + dpll_mpu_ck: clock@2d60 { 281 250 #clock-cells = <0>; 282 251 compatible = "ti,am3-dpll-clock"; 252 + clock-output-names = "dpll_mpu_ck"; 283 253 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 284 254 reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; 285 255 }; 286 256 287 - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { 257 + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { 288 258 #clock-cells = <0>; 289 259 compatible = "ti,divider-clock"; 260 + clock-output-names = "dpll_mpu_m2_ck"; 290 261 clocks = <&dpll_mpu_ck>; 291 262 ti,max-div = <31>; 292 263 ti,autoidle-shift = <8>; ··· 297 264 ti,invert-autoidle-bit; 298 265 }; 299 266 300 - mpu_periphclk: mpu_periphclk { 267 + mpu_periphclk: clock-mpu-periphclk { 301 268 #clock-cells = <0>; 302 269 compatible = "fixed-factor-clock"; 270 + clock-output-names = "mpu_periphclk"; 303 271 clocks = <&dpll_mpu_m2_ck>; 304 272 clock-mult = <1>; 305 273 clock-div = <2>; 306 274 }; 307 275 308 - dpll_ddr_ck: dpll_ddr_ck@2da0 { 276 + dpll_ddr_ck: clock@2da0 { 309 277 #clock-cells = <0>; 310 278 compatible = "ti,am3-dpll-clock"; 279 + clock-output-names = "dpll_ddr_ck"; 311 280 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 312 281 reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; 313 282 }; 314 283 315 - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { 284 + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { 316 285 #clock-cells = <0>; 317 286 compatible = "ti,divider-clock"; 287 + clock-output-names = "dpll_ddr_m2_ck"; 318 288 clocks = <&dpll_ddr_ck>; 319 289 ti,max-div = <31>; 320 290 ti,autoidle-shift = <8>; ··· 326 290 ti,invert-autoidle-bit; 327 291 }; 328 292 329 - dpll_disp_ck: dpll_disp_ck@2e20 { 293 + dpll_disp_ck: clock@2e20 { 330 294 #clock-cells = <0>; 331 295 compatible = "ti,am3-dpll-clock"; 296 + clock-output-names = "dpll_disp_ck"; 332 297 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 333 298 reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; 334 299 }; 335 300 336 - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { 301 + dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { 337 302 #clock-cells = <0>; 338 303 compatible = "ti,divider-clock"; 304 + clock-output-names = "dpll_disp_m2_ck"; 339 305 clocks = <&dpll_disp_ck>; 340 306 ti,max-div = <31>; 341 307 ti,autoidle-shift = <8>; ··· 347 309 ti,set-rate-parent; 348 310 }; 349 311 350 - dpll_per_ck: dpll_per_ck@2de0 { 312 + dpll_per_ck: clock@2de0 { 351 313 #clock-cells = <0>; 352 314 compatible = "ti,am3-dpll-j-type-clock"; 315 + clock-output-names = "dpll_per_ck"; 353 316 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 354 317 reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; 355 318 }; 356 319 357 - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { 320 + dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { 358 321 #clock-cells = <0>; 359 322 compatible = "ti,divider-clock"; 323 + clock-output-names = "dpll_per_m2_ck"; 360 324 clocks = <&dpll_per_ck>; 361 325 ti,max-div = <127>; 362 326 ti,autoidle-shift = <8>; ··· 367 327 ti,invert-autoidle-bit; 368 328 }; 369 329 370 - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 330 + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { 371 331 #clock-cells = <0>; 372 332 compatible = "fixed-factor-clock"; 333 + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; 373 334 clocks = <&dpll_per_m2_ck>; 374 335 clock-mult = <1>; 375 336 clock-div = <4>; 376 337 }; 377 338 378 - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 339 + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { 379 340 #clock-cells = <0>; 380 341 compatible = "fixed-factor-clock"; 342 + clock-output-names = "dpll_per_m2_div4_ck"; 381 343 clocks = <&dpll_per_m2_ck>; 382 344 clock-mult = <1>; 383 345 clock-div = <4>; 384 346 }; 385 347 386 - clk_24mhz: clk_24mhz { 348 + clk_24mhz: clock-clk-24mhz { 387 349 #clock-cells = <0>; 388 350 compatible = "fixed-factor-clock"; 351 + clock-output-names = "clk_24mhz"; 389 352 clocks = <&dpll_per_m2_ck>; 390 353 clock-mult = <1>; 391 354 clock-div = <8>; 392 355 }; 393 356 394 - clkdiv32k_ck: clkdiv32k_ck { 357 + clkdiv32k_ck: clock-clkdiv32k { 395 358 #clock-cells = <0>; 396 359 compatible = "fixed-factor-clock"; 360 + clock-output-names = "clkdiv32k_ck"; 397 361 clocks = <&clk_24mhz>; 398 362 clock-mult = <1>; 399 363 clock-div = <732>; 400 364 }; 401 365 402 - clkdiv32k_ick: clkdiv32k_ick@2a38 { 366 + clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { 403 367 #clock-cells = <0>; 404 368 compatible = "ti,gate-clock"; 369 + clock-output-names = "clkdiv32k_ick"; 405 370 clocks = <&clkdiv32k_ck>; 406 371 ti,bit-shift = <8>; 407 372 reg = <0x2a38>; 408 373 }; 409 374 410 - sysclk_div: sysclk_div { 375 + sysclk_div: clock-sysclk-div { 411 376 #clock-cells = <0>; 412 377 compatible = "fixed-factor-clock"; 378 + clock-output-names = "sysclk_div"; 413 379 clocks = <&dpll_core_m4_ck>; 414 380 clock-mult = <1>; 415 381 clock-div = <1>; 416 382 }; 417 383 418 - pruss_ocp_gclk: pruss_ocp_gclk@4248 { 384 + pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { 419 385 #clock-cells = <0>; 420 386 compatible = "ti,mux-clock"; 387 + clock-output-names = "pruss_ocp_gclk"; 421 388 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; 422 389 reg = <0x4248>; 423 390 }; 424 391 425 - clk_32k_tpm_ck: clk_32k_tpm_ck { 392 + clk_32k_tpm_ck: clock-clk-32k-tpm { 426 393 #clock-cells = <0>; 427 394 compatible = "fixed-clock"; 395 + clock-output-names = "clk_32k_tpm_ck"; 428 396 clock-frequency = <32768>; 429 397 }; 430 398 431 - timer1_fck: timer1_fck@4200 { 399 + timer1_fck: clock-timer1-fck@4200 { 432 400 #clock-cells = <0>; 433 401 compatible = "ti,mux-clock"; 402 + clock-output-names = "timer1_fck"; 434 403 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; 435 404 reg = <0x4200>; 436 405 }; 437 406 438 - timer2_fck: timer2_fck@4204 { 407 + timer2_fck: clock-timer2-fck@4204 { 439 408 #clock-cells = <0>; 440 409 compatible = "ti,mux-clock"; 410 + clock-output-names = "timer2_fck"; 441 411 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 442 412 reg = <0x4204>; 443 413 }; 444 414 445 - timer3_fck: timer3_fck@4208 { 415 + timer3_fck: clock-timer3-fck@4208 { 446 416 #clock-cells = <0>; 447 417 compatible = "ti,mux-clock"; 418 + clock-output-names = "timer3_fck"; 448 419 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 449 420 reg = <0x4208>; 450 421 }; 451 422 452 - timer4_fck: timer4_fck@420c { 423 + timer4_fck: clock-timer4-fck@420c { 453 424 #clock-cells = <0>; 454 425 compatible = "ti,mux-clock"; 426 + clock-output-names = "timer4_fck"; 455 427 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 456 428 reg = <0x420c>; 457 429 }; 458 430 459 - timer5_fck: timer5_fck@4210 { 431 + timer5_fck: clock-timer5-fck@4210 { 460 432 #clock-cells = <0>; 461 433 compatible = "ti,mux-clock"; 434 + clock-output-names = "timer5_fck"; 462 435 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 463 436 reg = <0x4210>; 464 437 }; 465 438 466 - timer6_fck: timer6_fck@4214 { 439 + timer6_fck: clock-timer6-fck@4214 { 467 440 #clock-cells = <0>; 468 441 compatible = "ti,mux-clock"; 442 + clock-output-names = "timer6_fck"; 469 443 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 470 444 reg = <0x4214>; 471 445 }; 472 446 473 - timer7_fck: timer7_fck@4218 { 447 + timer7_fck: clock-timer7-fck@4218 { 474 448 #clock-cells = <0>; 475 449 compatible = "ti,mux-clock"; 450 + clock-output-names = "timer7_fck"; 476 451 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 477 452 reg = <0x4218>; 478 453 }; 479 454 480 - wdt1_fck: wdt1_fck@422c { 455 + wdt1_fck: clock-wdt1-fck@422c { 481 456 #clock-cells = <0>; 482 457 compatible = "ti,mux-clock"; 458 + clock-output-names = "wdt1_fck"; 483 459 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 484 460 reg = <0x422c>; 485 461 }; ··· 507 451 reg = <0x424c>; 508 452 }; 509 453 510 - l3_gclk: l3_gclk { 454 + l3_gclk: clock-l3-gclk { 511 455 #clock-cells = <0>; 512 456 compatible = "fixed-factor-clock"; 457 + clock-output-names = "l3_gclk"; 513 458 clocks = <&dpll_core_m4_ck>; 514 459 clock-mult = <1>; 515 460 clock-div = <1>; 516 461 }; 517 462 518 - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 463 + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { 519 464 #clock-cells = <0>; 520 465 compatible = "fixed-factor-clock"; 466 + clock-output-names = "dpll_core_m4_div2_ck"; 521 467 clocks = <&sysclk_div>; 522 468 clock-mult = <1>; 523 469 clock-div = <2>; 524 470 }; 525 471 526 - l4hs_gclk: l4hs_gclk { 472 + l4hs_gclk: clock-l4hs-gclk { 527 473 #clock-cells = <0>; 528 474 compatible = "fixed-factor-clock"; 475 + clock-output-names = "l4hs_gclk"; 529 476 clocks = <&dpll_core_m4_ck>; 530 477 clock-mult = <1>; 531 478 clock-div = <1>; 532 479 }; 533 480 534 - l3s_gclk: l3s_gclk { 481 + l3s_gclk: clock-l3s-gclk { 535 482 #clock-cells = <0>; 536 483 compatible = "fixed-factor-clock"; 484 + clock-output-names = "l3s_gclk"; 537 485 clocks = <&dpll_core_m4_div2_ck>; 538 486 clock-mult = <1>; 539 487 clock-div = <1>; 540 488 }; 541 489 542 - l4ls_gclk: l4ls_gclk { 490 + l4ls_gclk: clock-l4ls-gclk { 543 491 #clock-cells = <0>; 544 492 compatible = "fixed-factor-clock"; 493 + clock-output-names = "l4ls_gclk"; 545 494 clocks = <&dpll_core_m4_div2_ck>; 546 495 clock-mult = <1>; 547 496 clock-div = <1>; 548 497 }; 549 498 550 - cpsw_125mhz_gclk: cpsw_125mhz_gclk { 499 + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { 551 500 #clock-cells = <0>; 552 501 compatible = "fixed-factor-clock"; 502 + clock-output-names = "cpsw_125mhz_gclk"; 553 503 clocks = <&dpll_core_m5_ck>; 554 504 clock-mult = <1>; 555 505 clock-div = <2>; 556 506 }; 557 507 558 - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { 508 + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { 559 509 #clock-cells = <0>; 560 510 compatible = "ti,mux-clock"; 511 + clock-output-names = "cpsw_cpts_rft_clk"; 561 512 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; 562 513 reg = <0x4238>; 563 514 }; 564 515 565 - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { 516 + dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { 566 517 #clock-cells = <0>; 567 518 compatible = "ti,divider-clock"; 519 + clock-output-names = "dpll_clksel_mac_clk"; 568 520 clocks = <&dpll_core_m5_ck>; 569 521 reg = <0x4234>; 570 522 ti,bit-shift = <2>; 571 523 ti,dividers = <2>, <5>; 572 524 }; 573 525 574 - clk_32k_mosc_ck: clk_32k_mosc_ck { 526 + clk_32k_mosc_ck: clock-clk-32k-mosc { 575 527 #clock-cells = <0>; 576 528 compatible = "fixed-clock"; 529 + clock-output-names = "clk_32k_mosc_ck"; 577 530 clock-frequency = <32768>; 578 531 }; 579 532 580 - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { 533 + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { 581 534 #clock-cells = <0>; 582 535 compatible = "ti,mux-clock"; 536 + clock-output-names = "gpio0_dbclk_mux_ck"; 583 537 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; 584 538 reg = <0x4240>; 585 539 }; 586 540 587 - mmc_clk: mmc_clk { 541 + mmc_clk: clock-mmc { 588 542 #clock-cells = <0>; 589 543 compatible = "fixed-factor-clock"; 544 + clock-output-names = "mmc_clk"; 590 545 clocks = <&dpll_per_m2_ck>; 591 546 clock-mult = <1>; 592 547 clock-div = <2>; 593 548 }; 594 549 595 - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { 550 + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { 596 551 #clock-cells = <0>; 597 552 compatible = "ti,mux-clock"; 553 + clock-output-names = "gfx_fclk_clksel_ck"; 598 554 clocks = <&sysclk_div>, <&dpll_per_m2_ck>; 599 555 ti,bit-shift = <1>; 600 556 reg = <0x423c>; 601 557 }; 602 558 603 - gfx_fck_div_ck: gfx_fck_div_ck@423c { 559 + gfx_fck_div_ck: clock-gfx-fck-div@423c { 604 560 #clock-cells = <0>; 605 561 compatible = "ti,divider-clock"; 562 + clock-output-names = "gfx_fck_div_ck"; 606 563 clocks = <&gfx_fclk_clksel_ck>; 607 564 reg = <0x423c>; 608 565 ti,max-div = <2>; 609 566 }; 610 567 611 - disp_clk: disp_clk@4244 { 568 + disp_clk: clock-disp@4244 { 612 569 #clock-cells = <0>; 613 570 compatible = "ti,mux-clock"; 571 + clock-output-names = "disp_clk"; 614 572 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 615 573 reg = <0x4244>; 616 574 ti,set-rate-parent; 617 575 }; 618 576 619 - dpll_extdev_ck: dpll_extdev_ck@2e60 { 577 + dpll_extdev_ck: clock@2e60 { 620 578 #clock-cells = <0>; 621 579 compatible = "ti,am3-dpll-clock"; 580 + clock-output-names = "dpll_extdev_ck"; 622 581 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 623 582 reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; 624 583 }; 625 584 626 - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { 585 + dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { 627 586 #clock-cells = <0>; 628 587 compatible = "ti,divider-clock"; 588 + clock-output-names = "dpll_extdev_m2_ck"; 629 589 clocks = <&dpll_extdev_ck>; 630 590 ti,max-div = <127>; 631 591 ti,autoidle-shift = <8>; ··· 650 578 ti,invert-autoidle-bit; 651 579 }; 652 580 653 - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { 581 + mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { 654 582 #clock-cells = <0>; 655 583 compatible = "ti,mux-clock"; 584 + clock-output-names = "mux_synctimer32k_ck"; 656 585 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; 657 586 reg = <0x4230>; 658 587 }; 659 588 660 - timer8_fck: timer8_fck@421c { 589 + timer8_fck: clock-timer8-fck@421c { 661 590 #clock-cells = <0>; 662 591 compatible = "ti,mux-clock"; 592 + clock-output-names = "timer8_fck"; 663 593 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 664 594 reg = <0x421c>; 665 595 }; 666 596 667 - timer9_fck: timer9_fck@4220 { 597 + timer9_fck: clock-timer9-fck@4220 { 668 598 #clock-cells = <0>; 669 599 compatible = "ti,mux-clock"; 600 + clock-output-names = "timer9_fck"; 670 601 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 671 602 reg = <0x4220>; 672 603 }; 673 604 674 - timer10_fck: timer10_fck@4224 { 605 + timer10_fck: clock-timer10-fck@4224 { 675 606 #clock-cells = <0>; 676 607 compatible = "ti,mux-clock"; 608 + clock-output-names = "timer10_fck"; 677 609 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 678 610 reg = <0x4224>; 679 611 }; 680 612 681 - timer11_fck: timer11_fck@4228 { 613 + timer11_fck: clock-timer11-fck@4228 { 682 614 #clock-cells = <0>; 683 615 compatible = "ti,mux-clock"; 616 + clock-output-names = "timer11_fck"; 684 617 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 685 618 reg = <0x4228>; 686 619 }; 687 620 688 - cpsw_50m_clkdiv: cpsw_50m_clkdiv { 621 + cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { 689 622 #clock-cells = <0>; 690 623 compatible = "fixed-factor-clock"; 624 + clock-output-names = "cpsw_50m_clkdiv"; 691 625 clocks = <&dpll_core_m5_ck>; 692 626 clock-mult = <1>; 693 627 clock-div = <1>; 694 628 }; 695 629 696 - cpsw_5m_clkdiv: cpsw_5m_clkdiv { 630 + cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { 697 631 #clock-cells = <0>; 698 632 compatible = "fixed-factor-clock"; 633 + clock-output-names = "cpsw_5m_clkdiv"; 699 634 clocks = <&cpsw_50m_clkdiv>; 700 635 clock-mult = <1>; 701 636 clock-div = <10>; 702 637 }; 703 638 704 - dpll_ddr_x2_ck: dpll_ddr_x2_ck { 639 + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 705 640 #clock-cells = <0>; 706 641 compatible = "ti,am3-dpll-x2-clock"; 642 + clock-output-names = "dpll_ddr_x2_ck"; 707 643 clocks = <&dpll_ddr_ck>; 708 644 }; 709 645 710 - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { 646 + dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { 711 647 #clock-cells = <0>; 712 648 compatible = "ti,divider-clock"; 649 + clock-output-names = "dpll_ddr_m4_ck"; 713 650 clocks = <&dpll_ddr_x2_ck>; 714 651 ti,max-div = <31>; 715 652 ti,autoidle-shift = <8>; ··· 727 646 ti,invert-autoidle-bit; 728 647 }; 729 648 730 - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { 649 + dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { 731 650 #clock-cells = <0>; 732 651 compatible = "ti,fixed-factor-clock"; 652 + clock-output-names = "dpll_per_clkdcoldo"; 733 653 clocks = <&dpll_per_ck>; 734 654 ti,clock-mult = <1>; 735 655 ti,clock-div = <1>; ··· 739 657 ti,invert-autoidle-bit; 740 658 }; 741 659 742 - dll_aging_clk_div: dll_aging_clk_div@4250 { 660 + dll_aging_clk_div: clock-dll-aging-clk-div@4250 { 743 661 #clock-cells = <0>; 744 662 compatible = "ti,divider-clock"; 663 + clock-output-names = "dll_aging_clk_div"; 745 664 clocks = <&sys_clkin_ck>; 746 665 reg = <0x4250>; 747 666 ti,dividers = <8>, <16>, <32>; 748 667 }; 749 668 750 - div_core_25m_ck: div_core_25m_ck { 669 + div_core_25m_ck: clock-div-core-25m { 751 670 #clock-cells = <0>; 752 671 compatible = "fixed-factor-clock"; 672 + clock-output-names = "div_core_25m_ck"; 753 673 clocks = <&sysclk_div>; 754 674 clock-mult = <1>; 755 675 clock-div = <8>; 756 676 }; 757 677 758 - func_12m_clk: func_12m_clk { 678 + func_12m_clk: clock-func-12m { 759 679 #clock-cells = <0>; 760 680 compatible = "fixed-factor-clock"; 681 + clock-output-names = "func_12m_clk"; 761 682 clocks = <&dpll_per_m2_ck>; 762 683 clock-mult = <1>; 763 684 clock-div = <16>; 764 685 }; 765 686 766 - vtp_clk_div: vtp_clk_div { 687 + vtp_clk_div: clock-vtp-clk-div { 767 688 #clock-cells = <0>; 768 689 compatible = "fixed-factor-clock"; 690 + clock-output-names = "vtp_clk_div"; 769 691 clocks = <&sys_clkin_ck>; 770 692 clock-mult = <1>; 771 693 clock-div = <2>; 772 694 }; 773 695 774 - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { 696 + usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { 775 697 #clock-cells = <0>; 776 698 compatible = "ti,mux-clock"; 699 + clock-output-names = "usbphy_32khz_clkmux"; 777 700 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; 778 701 reg = <0x4260>; 779 702 }; 780 703 781 - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { 704 + usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { 782 705 #clock-cells = <0>; 783 706 compatible = "ti,gate-clock"; 707 + clock-output-names = "usb_phy0_always_on_clk32k"; 784 708 clocks = <&usbphy_32khz_clkmux>; 785 709 ti,bit-shift = <8>; 786 710 reg = <0x2a40>; 787 711 }; 788 712 789 - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { 713 + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { 790 714 #clock-cells = <0>; 791 715 compatible = "ti,gate-clock"; 716 + clock-output-names = "usb_phy1_always_on_clk32k"; 792 717 clocks = <&usbphy_32khz_clkmux>; 793 718 ti,bit-shift = <8>; 794 719 reg = <0x2a48>; 795 720 }; 796 721 797 - clkout1_osc_div_ck: clkout1-osc-div-ck { 722 + clkout1_osc_div_ck: clock-clkout1-osc-div-ck { 798 723 #clock-cells = <0>; 799 724 compatible = "ti,divider-clock"; 725 + clock-output-names = "clkout1_osc_div_ck"; 800 726 clocks = <&sys_clkin_ck>; 801 727 ti,bit-shift = <20>; 802 728 ti,max-div = <4>; 803 729 reg = <0x4100>; 804 730 }; 805 731 806 - clkout1_src2_mux_ck: clkout1-src2-mux-ck { 732 + clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { 807 733 #clock-cells = <0>; 808 734 compatible = "ti,mux-clock"; 735 + clock-output-names = "clkout1_src2_mux_ck"; 809 736 clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, 810 737 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, 811 738 <&dpll_mpu_m2_ck>; 812 739 reg = <0x4100>; 813 740 }; 814 741 815 - clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { 742 + clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { 816 743 #clock-cells = <0>; 817 744 compatible = "ti,divider-clock"; 745 + clock-output-names = "clkout1_src2_pre_div_ck"; 818 746 clocks = <&clkout1_src2_mux_ck>; 819 747 ti,bit-shift = <4>; 820 748 ti,max-div = <8>; 821 749 reg = <0x4100>; 822 750 }; 823 751 824 - clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { 752 + clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { 825 753 #clock-cells = <0>; 826 754 compatible = "ti,divider-clock"; 755 + clock-output-names = "clkout1_src2_post_div_ck"; 827 756 clocks = <&clkout1_src2_pre_div_ck>; 828 757 ti,bit-shift = <8>; 829 758 ti,max-div = <32>; ··· 842 749 reg = <0x4100>; 843 750 }; 844 751 845 - clkout1_mux_ck: clkout1-mux-ck { 752 + clkout1_mux_ck: clock-clkout1-mux-ck { 846 753 #clock-cells = <0>; 847 754 compatible = "ti,mux-clock"; 755 + clock-output-names = "clkout1_mux_ck"; 848 756 clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, 849 757 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; 850 758 ti,bit-shift = <16>; 851 759 reg = <0x4100>; 852 760 }; 853 761 854 - clkout1_ck: clkout1-ck { 762 + clkout1_ck: clock-clkout1-ck { 855 763 #clock-cells = <0>; 856 764 compatible = "ti,gate-clock"; 765 + clock-output-names = "clkout1_ck"; 857 766 clocks = <&clkout1_mux_ck>; 858 767 ti,bit-shift = <23>; 859 768 reg = <0x4100>; ··· 863 768 }; 864 769 865 770 &prcm { 866 - wkup_cm: wkup-cm@2800 { 771 + wkup_cm: clock@2800 { 867 772 compatible = "ti,omap4-cm"; 773 + clock-output-names = "wkup_cm"; 868 774 reg = <0x2800 0x400>; 869 775 #address-cells = <1>; 870 776 #size-cells = <1>; 871 777 ranges = <0 0x2800 0x400>; 872 778 873 - l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { 779 + l3s_tsc_clkctrl: clock@120 { 874 780 compatible = "ti,clkctrl"; 781 + clock-output-names = "l3s_tsc_clkctrl"; 875 782 reg = <0x120 0x4>; 876 783 #clock-cells = <2>; 877 784 }; 878 785 879 - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { 786 + l4_wkup_aon_clkctrl: clock@228 { 880 787 compatible = "ti,clkctrl"; 788 + clock-output-names = "l4_wkup_aon_clkctrl"; 881 789 reg = <0x228 0xc>; 882 790 #clock-cells = <2>; 883 791 }; 884 792 885 - l4_wkup_clkctrl: l4-wkup-clkctrl@220 { 793 + l4_wkup_clkctrl: clock@220 { 886 794 compatible = "ti,clkctrl"; 795 + clock-output-names = "l4_wkup_clkctrl"; 887 796 reg = <0x220 0x4>, <0x328 0x44>; 888 797 #clock-cells = <2>; 889 798 }; 890 799 891 800 }; 892 801 893 - mpu_cm: mpu-cm@8300 { 802 + mpu_cm: clock@8300 { 894 803 compatible = "ti,omap4-cm"; 804 + clock-output-names = "mpu_cm"; 895 805 reg = <0x8300 0x100>; 896 806 #address-cells = <1>; 897 807 #size-cells = <1>; 898 808 ranges = <0 0x8300 0x100>; 899 809 900 - mpu_clkctrl: mpu-clkctrl@20 { 810 + mpu_clkctrl: clock@20 { 901 811 compatible = "ti,clkctrl"; 812 + clock-output-names = "mpu_clkctrl"; 902 813 reg = <0x20 0x4>; 903 814 #clock-cells = <2>; 904 815 }; 905 816 }; 906 817 907 - gfx_l3_cm: gfx-l3-cm@8400 { 818 + gfx_l3_cm: clock@8400 { 908 819 compatible = "ti,omap4-cm"; 820 + clock-output-names = "gfx_l3_cm"; 909 821 reg = <0x8400 0x100>; 910 822 #address-cells = <1>; 911 823 #size-cells = <1>; 912 824 ranges = <0 0x8400 0x100>; 913 825 914 - gfx_l3_clkctrl: gfx-l3-clkctrl@20 { 826 + gfx_l3_clkctrl: clock@20 { 915 827 compatible = "ti,clkctrl"; 828 + clock-output-names = "gfx_l3_clkctrl"; 916 829 reg = <0x20 0x4>; 917 830 #clock-cells = <2>; 918 831 }; 919 832 }; 920 833 921 - l4_rtc_cm: l4-rtc-cm@8500 { 834 + l4_rtc_cm: clock@8500 { 922 835 compatible = "ti,omap4-cm"; 836 + clock-output-names = "l4_rtc_cm"; 923 837 reg = <0x8500 0x100>; 924 838 #address-cells = <1>; 925 839 #size-cells = <1>; 926 840 ranges = <0 0x8500 0x100>; 927 841 928 - l4_rtc_clkctrl: l4-rtc-clkctrl@20 { 842 + l4_rtc_clkctrl: clock@20 { 929 843 compatible = "ti,clkctrl"; 844 + clock-output-names = "l4_rtc_clkctrl"; 930 845 reg = <0x20 0x4>; 931 846 #clock-cells = <2>; 932 847 }; 933 848 }; 934 849 935 - per_cm: per-cm@8800 { 850 + per_cm: clock@8800 { 936 851 compatible = "ti,omap4-cm"; 852 + clock-output-names = "per_cm"; 937 853 reg = <0x8800 0xc00>; 938 854 #address-cells = <1>; 939 855 #size-cells = <1>; 940 856 ranges = <0 0x8800 0xc00>; 941 857 942 - l3_clkctrl: l3-clkctrl@20 { 858 + l3_clkctrl: clock@20 { 943 859 compatible = "ti,clkctrl"; 860 + clock-output-names = "l3_clkctrl"; 944 861 reg = <0x20 0x3c>, <0x78 0x2c>; 945 862 #clock-cells = <2>; 946 863 }; 947 864 948 - l3s_clkctrl: l3s-clkctrl@68 { 865 + l3s_clkctrl: clock@68 { 949 866 compatible = "ti,clkctrl"; 867 + clock-output-names = "l3s_clkctrl"; 950 868 reg = <0x68 0xc>, <0x220 0x4c>; 951 869 #clock-cells = <2>; 952 870 }; 953 871 954 - pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { 872 + pruss_ocp_clkctrl: clock@320 { 955 873 compatible = "ti,clkctrl"; 874 + clock-output-names = "pruss_ocp_clkctrl"; 956 875 reg = <0x320 0x4>; 957 876 #clock-cells = <2>; 958 877 }; 959 878 960 - l4ls_clkctrl: l4ls-clkctrl@420 { 879 + l4ls_clkctrl: clock@420 { 961 880 compatible = "ti,clkctrl"; 881 + clock-output-names = "l4ls_clkctrl"; 962 882 reg = <0x420 0x1a4>; 963 883 #clock-cells = <2>; 964 884 }; 965 885 966 - emif_clkctrl: emif-clkctrl@720 { 886 + emif_clkctrl: clock@720 { 967 887 compatible = "ti,clkctrl"; 888 + clock-output-names = "emif_clkctrl"; 968 889 reg = <0x720 0x4>; 969 890 #clock-cells = <2>; 970 891 }; 971 892 972 - dss_clkctrl: dss-clkctrl@a20 { 893 + dss_clkctrl: clock@a20 { 973 894 compatible = "ti,clkctrl"; 895 + clock-output-names = "dss_clkctrl"; 974 896 reg = <0xa20 0x4>; 975 897 #clock-cells = <2>; 976 898 }; 977 899 978 - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { 900 + cpsw_125mhz_clkctrl: clock@b20 { 979 901 compatible = "ti,clkctrl"; 902 + clock-output-names = "cpsw_125mhz_clkctrl"; 980 903 reg = <0xb20 0x4>; 981 904 #clock-cells = <2>; 982 905 };

+462 -231

arch/arm/boot/dts/dra7xx-clocks.dtsi

··· 5 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 6 */ 7 7 &cm_core_aon_clocks { 8 - atl_clkin0_ck: atl_clkin0_ck { 8 + atl_clkin0_ck: clock-atl-clkin0 { 9 9 #clock-cells = <0>; 10 10 compatible = "ti,dra7-atl-clock"; 11 + clock-output-names = "atl_clkin0_ck"; 11 12 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 12 13 }; 13 14 14 - atl_clkin1_ck: atl_clkin1_ck { 15 + atl_clkin1_ck: clock-atl-clkin1 { 15 16 #clock-cells = <0>; 16 17 compatible = "ti,dra7-atl-clock"; 18 + clock-output-names = "atl_clkin1_ck"; 17 19 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 18 20 }; 19 21 20 - atl_clkin2_ck: atl_clkin2_ck { 22 + atl_clkin2_ck: clock-atl-clkin2 { 21 23 #clock-cells = <0>; 22 24 compatible = "ti,dra7-atl-clock"; 25 + clock-output-names = "atl_clkin2_ck"; 23 26 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 24 27 }; 25 28 26 - atl_clkin3_ck: atl_clkin3_ck { 29 + atl_clkin3_ck: clock-atl-clkin3 { 27 30 #clock-cells = <0>; 28 31 compatible = "ti,dra7-atl-clock"; 32 + clock-output-names = "atl_clkin3_ck"; 29 33 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 30 34 }; 31 35 32 - hdmi_clkin_ck: hdmi_clkin_ck { 36 + hdmi_clkin_ck: clock-hdmi-clkin { 33 37 #clock-cells = <0>; 34 38 compatible = "fixed-clock"; 39 + clock-output-names = "hdmi_clkin_ck"; 35 40 clock-frequency = <0>; 36 41 }; 37 42 38 - mlb_clkin_ck: mlb_clkin_ck { 43 + mlb_clkin_ck: clock-mlb-clkin { 39 44 #clock-cells = <0>; 40 45 compatible = "fixed-clock"; 46 + clock-output-names = "mlb_clkin_ck"; 41 47 clock-frequency = <0>; 42 48 }; 43 49 44 - mlbp_clkin_ck: mlbp_clkin_ck { 50 + mlbp_clkin_ck: clock-mlbp-clkin { 45 51 #clock-cells = <0>; 46 52 compatible = "fixed-clock"; 53 + clock-output-names = "mlbp_clkin_ck"; 47 54 clock-frequency = <0>; 48 55 }; 49 56 50 - pciesref_acs_clk_ck: pciesref_acs_clk_ck { 57 + pciesref_acs_clk_ck: clock-pciesref-acs { 51 58 #clock-cells = <0>; 52 59 compatible = "fixed-clock"; 60 + clock-output-names = "pciesref_acs_clk_ck"; 53 61 clock-frequency = <100000000>; 54 62 }; 55 63 56 - ref_clkin0_ck: ref_clkin0_ck { 64 + ref_clkin0_ck: clock-ref-clkin0 { 57 65 #clock-cells = <0>; 58 66 compatible = "fixed-clock"; 67 + clock-output-names = "ref_clkin0_ck"; 59 68 clock-frequency = <0>; 60 69 }; 61 70 62 - ref_clkin1_ck: ref_clkin1_ck { 71 + ref_clkin1_ck: clock-ref-clkin1 { 63 72 #clock-cells = <0>; 64 73 compatible = "fixed-clock"; 74 + clock-output-names = "ref_clkin1_ck"; 65 75 clock-frequency = <0>; 66 76 }; 67 77 68 - ref_clkin2_ck: ref_clkin2_ck { 78 + ref_clkin2_ck: clock-ref-clkin2 { 69 79 #clock-cells = <0>; 70 80 compatible = "fixed-clock"; 81 + clock-output-names = "ref_clkin2_ck"; 71 82 clock-frequency = <0>; 72 83 }; 73 84 74 - ref_clkin3_ck: ref_clkin3_ck { 85 + ref_clkin3_ck: clock-ref-clkin3 { 75 86 #clock-cells = <0>; 76 87 compatible = "fixed-clock"; 88 + clock-output-names = "ref_clkin3_ck"; 77 89 clock-frequency = <0>; 78 90 }; 79 91 80 - rmii_clk_ck: rmii_clk_ck { 92 + rmii_clk_ck: clock-rmii { 81 93 #clock-cells = <0>; 82 94 compatible = "fixed-clock"; 95 + clock-output-names = "rmii_clk_ck"; 83 96 clock-frequency = <0>; 84 97 }; 85 98 86 - sdvenc_clkin_ck: sdvenc_clkin_ck { 99 + sdvenc_clkin_ck: clock-sdvenc-clkin { 87 100 #clock-cells = <0>; 88 101 compatible = "fixed-clock"; 102 + clock-output-names = "sdvenc_clkin_ck"; 89 103 clock-frequency = <0>; 90 104 }; 91 105 92 - secure_32k_clk_src_ck: secure_32k_clk_src_ck { 106 + secure_32k_clk_src_ck: clock-secure-32k-clk-src { 93 107 #clock-cells = <0>; 94 108 compatible = "fixed-clock"; 109 + clock-output-names = "secure_32k_clk_src_ck"; 95 110 clock-frequency = <32768>; 96 111 }; 97 112 98 - sys_clk32_crystal_ck: sys_clk32_crystal_ck { 113 + sys_clk32_crystal_ck: clock-sys-clk32-crystal { 99 114 #clock-cells = <0>; 100 115 compatible = "fixed-clock"; 116 + clock-output-names = "sys_clk32_crystal_ck"; 101 117 clock-frequency = <32768>; 102 118 }; 103 119 104 - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { 120 + sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { 105 121 #clock-cells = <0>; 106 122 compatible = "fixed-factor-clock"; 123 + clock-output-names = "sys_clk32_pseudo_ck"; 107 124 clocks = <&sys_clkin1>; 108 125 clock-mult = <1>; 109 126 clock-div = <610>; 110 127 }; 111 128 112 - virt_12000000_ck: virt_12000000_ck { 129 + virt_12000000_ck: clock-virt-12000000 { 113 130 #clock-cells = <0>; 114 131 compatible = "fixed-clock"; 132 + clock-output-names = "virt_12000000_ck"; 115 133 clock-frequency = <12000000>; 116 134 }; 117 135 118 - virt_13000000_ck: virt_13000000_ck { 136 + virt_13000000_ck: clock-virt-13000000 { 119 137 #clock-cells = <0>; 120 138 compatible = "fixed-clock"; 139 + clock-output-names = "virt_13000000_ck"; 121 140 clock-frequency = <13000000>; 122 141 }; 123 142 124 - virt_16800000_ck: virt_16800000_ck { 143 + virt_16800000_ck: clock-virt-16800000 { 125 144 #clock-cells = <0>; 126 145 compatible = "fixed-clock"; 146 + clock-output-names = "virt_16800000_ck"; 127 147 clock-frequency = <16800000>; 128 148 }; 129 149 130 - virt_19200000_ck: virt_19200000_ck { 150 + virt_19200000_ck: clock-virt-19200000 { 131 151 #clock-cells = <0>; 132 152 compatible = "fixed-clock"; 153 + clock-output-names = "virt_19200000_ck"; 133 154 clock-frequency = <19200000>; 134 155 }; 135 156 136 - virt_20000000_ck: virt_20000000_ck { 157 + virt_20000000_ck: clock-virt-20000000 { 137 158 #clock-cells = <0>; 138 159 compatible = "fixed-clock"; 160 + clock-output-names = "virt_20000000_ck"; 139 161 clock-frequency = <20000000>; 140 162 }; 141 163 142 - virt_26000000_ck: virt_26000000_ck { 164 + virt_26000000_ck: clock-virt-26000000 { 143 165 #clock-cells = <0>; 144 166 compatible = "fixed-clock"; 167 + clock-output-names = "virt_26000000_ck"; 145 168 clock-frequency = <26000000>; 146 169 }; 147 170 148 - virt_27000000_ck: virt_27000000_ck { 171 + virt_27000000_ck: clock-virt-27000000 { 149 172 #clock-cells = <0>; 150 173 compatible = "fixed-clock"; 174 + clock-output-names = "virt_27000000_ck"; 151 175 clock-frequency = <27000000>; 152 176 }; 153 177 154 - virt_38400000_ck: virt_38400000_ck { 178 + virt_38400000_ck: clock-virt-38400000 { 155 179 #clock-cells = <0>; 156 180 compatible = "fixed-clock"; 181 + clock-output-names = "virt_38400000_ck"; 157 182 clock-frequency = <38400000>; 158 183 }; 159 184 160 - sys_clkin2: sys_clkin2 { 185 + sys_clkin2: clock-sys-clkin2 { 161 186 #clock-cells = <0>; 162 187 compatible = "fixed-clock"; 188 + clock-output-names = "sys_clkin2"; 163 189 clock-frequency = <22579200>; 164 190 }; 165 191 166 - usb_otg_clkin_ck: usb_otg_clkin_ck { 192 + usb_otg_clkin_ck: clock-usb-otg-clkin { 167 193 #clock-cells = <0>; 168 194 compatible = "fixed-clock"; 195 + clock-output-names = "usb_otg_clkin_ck"; 169 196 clock-frequency = <0>; 170 197 }; 171 198 172 - video1_clkin_ck: video1_clkin_ck { 199 + video1_clkin_ck: clock-video1-clkin { 173 200 #clock-cells = <0>; 174 201 compatible = "fixed-clock"; 202 + clock-output-names = "video1_clkin_ck"; 175 203 clock-frequency = <0>; 176 204 }; 177 205 178 - video1_m2_clkin_ck: video1_m2_clkin_ck { 206 + video1_m2_clkin_ck: clock-video1-m2-clkin { 179 207 #clock-cells = <0>; 180 208 compatible = "fixed-clock"; 209 + clock-output-names = "video1_m2_clkin_ck"; 181 210 clock-frequency = <0>; 182 211 }; 183 212 184 - video2_clkin_ck: video2_clkin_ck { 213 + video2_clkin_ck: clock-video2-clkin { 185 214 #clock-cells = <0>; 186 215 compatible = "fixed-clock"; 216 + clock-output-names = "video2_clkin_ck"; 187 217 clock-frequency = <0>; 188 218 }; 189 219 190 - video2_m2_clkin_ck: video2_m2_clkin_ck { 220 + video2_m2_clkin_ck: clock-video2-m2-clkin { 191 221 #clock-cells = <0>; 192 222 compatible = "fixed-clock"; 223 + clock-output-names = "video2_m2_clkin_ck"; 193 224 clock-frequency = <0>; 194 225 }; 195 226 196 - dpll_abe_ck: dpll_abe_ck@1e0 { 227 + dpll_abe_ck: clock@1e0 { 197 228 #clock-cells = <0>; 198 229 compatible = "ti,omap4-dpll-m4xen-clock"; 230 + clock-output-names = "dpll_abe_ck"; 199 231 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; 200 232 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 201 233 }; 202 234 203 - dpll_abe_x2_ck: dpll_abe_x2_ck { 235 + dpll_abe_x2_ck: clock-dpll-abe-x2 { 204 236 #clock-cells = <0>; 205 237 compatible = "ti,omap4-dpll-x2-clock"; 238 + clock-output-names = "dpll_abe_x2_ck"; 206 239 clocks = <&dpll_abe_ck>; 207 240 }; 208 241 209 - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { 242 + dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { 210 243 #clock-cells = <0>; 211 244 compatible = "ti,divider-clock"; 245 + clock-output-names = "dpll_abe_m2x2_ck"; 212 246 clocks = <&dpll_abe_x2_ck>; 213 247 ti,max-div = <31>; 214 248 ti,autoidle-shift = <8>; ··· 251 217 ti,invert-autoidle-bit; 252 218 }; 253 219 254 - abe_clk: abe_clk@108 { 220 + abe_clk: clock-abe@108 { 255 221 #clock-cells = <0>; 256 222 compatible = "ti,divider-clock"; 223 + clock-output-names = "abe_clk"; 257 224 clocks = <&dpll_abe_m2x2_ck>; 258 225 ti,max-div = <4>; 259 226 reg = <0x0108>; 260 227 ti,index-power-of-two; 261 228 }; 262 229 263 - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { 230 + dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { 264 231 #clock-cells = <0>; 265 232 compatible = "ti,divider-clock"; 233 + clock-output-names = "dpll_abe_m2_ck"; 266 234 clocks = <&dpll_abe_ck>; 267 235 ti,max-div = <31>; 268 236 ti,autoidle-shift = <8>; ··· 273 237 ti,invert-autoidle-bit; 274 238 }; 275 239 276 - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { 240 + dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { 277 241 #clock-cells = <0>; 278 242 compatible = "ti,divider-clock"; 243 + clock-output-names = "dpll_abe_m3x2_ck"; 279 244 clocks = <&dpll_abe_x2_ck>; 280 245 ti,max-div = <31>; 281 246 ti,autoidle-shift = <8>; ··· 285 248 ti,invert-autoidle-bit; 286 249 }; 287 250 288 - dpll_core_byp_mux: dpll_core_byp_mux@12c { 251 + dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { 289 252 #clock-cells = <0>; 290 253 compatible = "ti,mux-clock"; 254 + clock-output-names = "dpll_core_byp_mux"; 291 255 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 292 256 ti,bit-shift = <23>; 293 257 reg = <0x012c>; 294 258 }; 295 259 296 - dpll_core_ck: dpll_core_ck@120 { 260 + dpll_core_ck: clock@120 { 297 261 #clock-cells = <0>; 298 262 compatible = "ti,omap4-dpll-core-clock"; 263 + clock-output-names = "dpll_core_ck"; 299 264 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; 300 265 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 301 266 }; 302 267 303 - dpll_core_x2_ck: dpll_core_x2_ck { 268 + dpll_core_x2_ck: clock-dpll-core-x2 { 304 269 #clock-cells = <0>; 305 270 compatible = "ti,omap4-dpll-x2-clock"; 271 + clock-output-names = "dpll_core_x2_ck"; 306 272 clocks = <&dpll_core_ck>; 307 273 }; 308 274 309 - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { 275 + dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { 310 276 #clock-cells = <0>; 311 277 compatible = "ti,divider-clock"; 278 + clock-output-names = "dpll_core_h12x2_ck"; 312 279 clocks = <&dpll_core_x2_ck>; 313 280 ti,max-div = <63>; 314 281 ti,autoidle-shift = <8>; ··· 321 280 ti,invert-autoidle-bit; 322 281 }; 323 282 324 - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { 283 + mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { 325 284 #clock-cells = <0>; 326 285 compatible = "fixed-factor-clock"; 286 + clock-output-names = "mpu_dpll_hs_clk_div"; 327 287 clocks = <&dpll_core_h12x2_ck>; 328 288 clock-mult = <1>; 329 289 clock-div = <1>; 330 290 }; 331 291 332 - dpll_mpu_ck: dpll_mpu_ck@160 { 292 + dpll_mpu_ck: clock@160 { 333 293 #clock-cells = <0>; 334 294 compatible = "ti,omap5-mpu-dpll-clock"; 295 + clock-output-names = "dpll_mpu_ck"; 335 296 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; 336 297 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 337 298 }; 338 299 339 - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { 300 + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { 340 301 #clock-cells = <0>; 341 302 compatible = "ti,divider-clock"; 303 + clock-output-names = "dpll_mpu_m2_ck"; 342 304 clocks = <&dpll_mpu_ck>; 343 305 ti,max-div = <31>; 344 306 ti,autoidle-shift = <8>; ··· 350 306 ti,invert-autoidle-bit; 351 307 }; 352 308 353 - mpu_dclk_div: mpu_dclk_div { 309 + mpu_dclk_div: clock-mpu-dclk-div { 354 310 #clock-cells = <0>; 355 311 compatible = "fixed-factor-clock"; 312 + clock-output-names = "mpu_dclk_div"; 356 313 clocks = <&dpll_mpu_m2_ck>; 357 314 clock-mult = <1>; 358 315 clock-div = <1>; 359 316 }; 360 317 361 - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { 318 + dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { 362 319 #clock-cells = <0>; 363 320 compatible = "fixed-factor-clock"; 321 + clock-output-names = "dsp_dpll_hs_clk_div"; 364 322 clocks = <&dpll_core_h12x2_ck>; 365 323 clock-mult = <1>; 366 324 clock-div = <1>; 367 325 }; 368 326 369 - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { 327 + dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { 370 328 #clock-cells = <0>; 371 329 compatible = "ti,mux-clock"; 330 + clock-output-names = "dpll_dsp_byp_mux"; 372 331 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 373 332 ti,bit-shift = <23>; 374 333 reg = <0x0240>; 375 334 }; 376 335 377 - dpll_dsp_ck: dpll_dsp_ck@234 { 336 + dpll_dsp_ck: clock@234 { 378 337 #clock-cells = <0>; 379 338 compatible = "ti,omap4-dpll-clock"; 339 + clock-output-names = "dpll_dsp_ck"; 380 340 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; 381 341 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; 382 342 assigned-clocks = <&dpll_dsp_ck>; 383 343 assigned-clock-rates = <600000000>; 384 344 }; 385 345 386 - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { 346 + dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { 387 347 #clock-cells = <0>; 388 348 compatible = "ti,divider-clock"; 349 + clock-output-names = "dpll_dsp_m2_ck"; 389 350 clocks = <&dpll_dsp_ck>; 390 351 ti,max-div = <31>; 391 352 ti,autoidle-shift = <8>; ··· 401 352 assigned-clock-rates = <600000000>; 402 353 }; 403 354 404 - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { 355 + iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { 405 356 #clock-cells = <0>; 406 357 compatible = "fixed-factor-clock"; 358 + clock-output-names = "iva_dpll_hs_clk_div"; 407 359 clocks = <&dpll_core_h12x2_ck>; 408 360 clock-mult = <1>; 409 361 clock-div = <1>; 410 362 }; 411 363 412 - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { 364 + dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { 413 365 #clock-cells = <0>; 414 366 compatible = "ti,mux-clock"; 367 + clock-output-names = "dpll_iva_byp_mux"; 415 368 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 416 369 ti,bit-shift = <23>; 417 370 reg = <0x01ac>; 418 371 }; 419 372 420 - dpll_iva_ck: dpll_iva_ck@1a0 { 373 + dpll_iva_ck: clock@1a0 { 421 374 #clock-cells = <0>; 422 375 compatible = "ti,omap4-dpll-clock"; 376 + clock-output-names = "dpll_iva_ck"; 423 377 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; 424 378 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 425 379 assigned-clocks = <&dpll_iva_ck>; 426 380 assigned-clock-rates = <1165000000>; 427 381 }; 428 382 429 - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { 383 + dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { 430 384 #clock-cells = <0>; 431 385 compatible = "ti,divider-clock"; 386 + clock-output-names = "dpll_iva_m2_ck"; 432 387 clocks = <&dpll_iva_ck>; 433 388 ti,max-div = <31>; 434 389 ti,autoidle-shift = <8>; ··· 443 390 assigned-clock-rates = <388333334>; 444 391 }; 445 392 446 - iva_dclk: iva_dclk { 393 + iva_dclk: clock-iva-dclk { 447 394 #clock-cells = <0>; 448 395 compatible = "fixed-factor-clock"; 396 + clock-output-names = "iva_dclk"; 449 397 clocks = <&dpll_iva_m2_ck>; 450 398 clock-mult = <1>; 451 399 clock-div = <1>; 452 400 }; 453 401 454 - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { 402 + dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { 455 403 #clock-cells = <0>; 456 404 compatible = "ti,mux-clock"; 405 + clock-output-names = "dpll_gpu_byp_mux"; 457 406 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 458 407 ti,bit-shift = <23>; 459 408 reg = <0x02e4>; 460 409 }; 461 410 462 - dpll_gpu_ck: dpll_gpu_ck@2d8 { 411 + dpll_gpu_ck: clock@2d8 { 463 412 #clock-cells = <0>; 464 413 compatible = "ti,omap4-dpll-clock"; 414 + clock-output-names = "dpll_gpu_ck"; 465 415 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; 466 416 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; 467 417 assigned-clocks = <&dpll_gpu_ck>; 468 418 assigned-clock-rates = <1277000000>; 469 419 }; 470 420 471 - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { 421 + dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { 472 422 #clock-cells = <0>; 473 423 compatible = "ti,divider-clock"; 424 + clock-output-names = "dpll_gpu_m2_ck"; 474 425 clocks = <&dpll_gpu_ck>; 475 426 ti,max-div = <31>; 476 427 ti,autoidle-shift = <8>; ··· 485 428 assigned-clock-rates = <425666667>; 486 429 }; 487 430 488 - dpll_core_m2_ck: dpll_core_m2_ck@130 { 431 + dpll_core_m2_ck: clock-dpll-core-m2-8@130 { 489 432 #clock-cells = <0>; 490 433 compatible = "ti,divider-clock"; 434 + clock-output-names = "dpll_core_m2_ck"; 491 435 clocks = <&dpll_core_ck>; 492 436 ti,max-div = <31>; 493 437 ti,autoidle-shift = <8>; ··· 497 439 ti,invert-autoidle-bit; 498 440 }; 499 441 500 - core_dpll_out_dclk_div: core_dpll_out_dclk_div { 442 + core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { 501 443 #clock-cells = <0>; 502 444 compatible = "fixed-factor-clock"; 445 + clock-output-names = "core_dpll_out_dclk_div"; 503 446 clocks = <&dpll_core_m2_ck>; 504 447 clock-mult = <1>; 505 448 clock-div = <1>; 506 449 }; 507 450 508 - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { 451 + dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { 509 452 #clock-cells = <0>; 510 453 compatible = "ti,mux-clock"; 454 + clock-output-names = "dpll_ddr_byp_mux"; 511 455 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 512 456 ti,bit-shift = <23>; 513 457 reg = <0x021c>; 514 458 }; 515 459 516 - dpll_ddr_ck: dpll_ddr_ck@210 { 460 + dpll_ddr_ck: clock@210 { 517 461 #clock-cells = <0>; 518 462 compatible = "ti,omap4-dpll-clock"; 463 + clock-output-names = "dpll_ddr_ck"; 519 464 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; 520 465 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; 521 466 }; 522 467 523 - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { 468 + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { 524 469 #clock-cells = <0>; 525 470 compatible = "ti,divider-clock"; 471 + clock-output-names = "dpll_ddr_m2_ck"; 526 472 clocks = <&dpll_ddr_ck>; 527 473 ti,max-div = <31>; 528 474 ti,autoidle-shift = <8>; ··· 535 473 ti,invert-autoidle-bit; 536 474 }; 537 475 538 - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { 476 + dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { 539 477 #clock-cells = <0>; 540 478 compatible = "ti,mux-clock"; 479 + clock-output-names = "dpll_gmac_byp_mux"; 541 480 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 542 481 ti,bit-shift = <23>; 543 482 reg = <0x02b4>; 544 483 }; 545 484 546 - dpll_gmac_ck: dpll_gmac_ck@2a8 { 485 + dpll_gmac_ck: clock@2a8 { 547 486 #clock-cells = <0>; 548 487 compatible = "ti,omap4-dpll-clock"; 488 + clock-output-names = "dpll_gmac_ck"; 549 489 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; 550 490 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; 551 491 }; 552 492 553 - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { 493 + dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { 554 494 #clock-cells = <0>; 555 495 compatible = "ti,divider-clock"; 496 + clock-output-names = "dpll_gmac_m2_ck"; 556 497 clocks = <&dpll_gmac_ck>; 557 498 ti,max-div = <31>; 558 499 ti,autoidle-shift = <8>; ··· 564 499 ti,invert-autoidle-bit; 565 500 }; 566 501 567 - video2_dclk_div: video2_dclk_div { 502 + video2_dclk_div: clock-video2-dclk-div { 568 503 #clock-cells = <0>; 569 504 compatible = "fixed-factor-clock"; 505 + clock-output-names = "video2_dclk_div"; 570 506 clocks = <&video2_m2_clkin_ck>; 571 507 clock-mult = <1>; 572 508 clock-div = <1>; 573 509 }; 574 510 575 - video1_dclk_div: video1_dclk_div { 511 + video1_dclk_div: clock-video1-dclk-div { 576 512 #clock-cells = <0>; 577 513 compatible = "fixed-factor-clock"; 514 + clock-output-names = "video1_dclk_div"; 578 515 clocks = <&video1_m2_clkin_ck>; 579 516 clock-mult = <1>; 580 517 clock-div = <1>; 581 518 }; 582 519 583 - hdmi_dclk_div: hdmi_dclk_div { 520 + hdmi_dclk_div: clock-hdmi-dclk-div { 584 521 #clock-cells = <0>; 585 522 compatible = "fixed-factor-clock"; 523 + clock-output-names = "hdmi_dclk_div"; 586 524 clocks = <&hdmi_clkin_ck>; 587 525 clock-mult = <1>; 588 526 clock-div = <1>; 589 527 }; 590 528 591 - per_dpll_hs_clk_div: per_dpll_hs_clk_div { 529 + per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { 592 530 #clock-cells = <0>; 593 531 compatible = "fixed-factor-clock"; 532 + clock-output-names = "per_dpll_hs_clk_div"; 594 533 clocks = <&dpll_abe_m3x2_ck>; 595 534 clock-mult = <1>; 596 535 clock-div = <2>; 597 536 }; 598 537 599 - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { 538 + usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { 600 539 #clock-cells = <0>; 601 540 compatible = "fixed-factor-clock"; 541 + clock-output-names = "usb_dpll_hs_clk_div"; 602 542 clocks = <&dpll_abe_m3x2_ck>; 603 543 clock-mult = <1>; 604 544 clock-div = <3>; 605 545 }; 606 546 607 - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { 547 + eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { 608 548 #clock-cells = <0>; 609 549 compatible = "fixed-factor-clock"; 550 + clock-output-names = "eve_dpll_hs_clk_div"; 610 551 clocks = <&dpll_core_h12x2_ck>; 611 552 clock-mult = <1>; 612 553 clock-div = <1>; 613 554 }; 614 555 615 - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { 556 + dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { 616 557 #clock-cells = <0>; 617 558 compatible = "ti,mux-clock"; 559 + clock-output-names = "dpll_eve_byp_mux"; 618 560 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 619 561 ti,bit-shift = <23>; 620 562 reg = <0x0290>; 621 563 }; 622 564 623 - dpll_eve_ck: dpll_eve_ck@284 { 565 + dpll_eve_ck: clock@284 { 624 566 #clock-cells = <0>; 625 567 compatible = "ti,omap4-dpll-clock"; 568 + clock-output-names = "dpll_eve_ck"; 626 569 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; 627 570 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; 628 571 }; 629 572 630 - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { 573 + dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { 631 574 #clock-cells = <0>; 632 575 compatible = "ti,divider-clock"; 576 + clock-output-names = "dpll_eve_m2_ck"; 633 577 clocks = <&dpll_eve_ck>; 634 578 ti,max-div = <31>; 635 579 ti,autoidle-shift = <8>; ··· 647 573 ti,invert-autoidle-bit; 648 574 }; 649 575 650 - eve_dclk_div: eve_dclk_div { 576 + eve_dclk_div: clock-eve-dclk-div { 651 577 #clock-cells = <0>; 652 578 compatible = "fixed-factor-clock"; 579 + clock-output-names = "eve_dclk_div"; 653 580 clocks = <&dpll_eve_m2_ck>; 654 581 clock-mult = <1>; 655 582 clock-div = <1>; 656 583 }; 657 584 658 - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { 585 + dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { 659 586 #clock-cells = <0>; 660 587 compatible = "ti,divider-clock"; 588 + clock-output-names = "dpll_core_h13x2_ck"; 661 589 clocks = <&dpll_core_x2_ck>; 662 590 ti,max-div = <63>; 663 591 ti,autoidle-shift = <8>; ··· 668 592 ti,invert-autoidle-bit; 669 593 }; 670 594 671 - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { 595 + dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { 672 596 #clock-cells = <0>; 673 597 compatible = "ti,divider-clock"; 598 + clock-output-names = "dpll_core_h14x2_ck"; 674 599 clocks = <&dpll_core_x2_ck>; 675 600 ti,max-div = <63>; 676 601 ti,autoidle-shift = <8>; ··· 680 603 ti,invert-autoidle-bit; 681 604 }; 682 605 683 - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { 606 + dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { 684 607 #clock-cells = <0>; 685 608 compatible = "ti,divider-clock"; 609 + clock-output-names = "dpll_core_h22x2_ck"; 686 610 clocks = <&dpll_core_x2_ck>; 687 611 ti,max-div = <63>; 688 612 ti,autoidle-shift = <8>; ··· 692 614 ti,invert-autoidle-bit; 693 615 }; 694 616 695 - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { 617 + dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { 696 618 #clock-cells = <0>; 697 619 compatible = "ti,divider-clock"; 620 + clock-output-names = "dpll_core_h23x2_ck"; 698 621 clocks = <&dpll_core_x2_ck>; 699 622 ti,max-div = <63>; 700 623 ti,autoidle-shift = <8>; ··· 704 625 ti,invert-autoidle-bit; 705 626 }; 706 627 707 - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { 628 + dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { 708 629 #clock-cells = <0>; 709 630 compatible = "ti,divider-clock"; 631 + clock-output-names = "dpll_core_h24x2_ck"; 710 632 clocks = <&dpll_core_x2_ck>; 711 633 ti,max-div = <63>; 712 634 ti,autoidle-shift = <8>; ··· 716 636 ti,invert-autoidle-bit; 717 637 }; 718 638 719 - dpll_ddr_x2_ck: dpll_ddr_x2_ck { 639 + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 720 640 #clock-cells = <0>; 721 641 compatible = "ti,omap4-dpll-x2-clock"; 642 + clock-output-names = "dpll_ddr_x2_ck"; 722 643 clocks = <&dpll_ddr_ck>; 723 644 }; 724 645 725 - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { 646 + dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { 726 647 #clock-cells = <0>; 727 648 compatible = "ti,divider-clock"; 649 + clock-output-names = "dpll_ddr_h11x2_ck"; 728 650 clocks = <&dpll_ddr_x2_ck>; 729 651 ti,max-div = <63>; 730 652 ti,autoidle-shift = <8>; ··· 735 653 ti,invert-autoidle-bit; 736 654 }; 737 655 738 - dpll_dsp_x2_ck: dpll_dsp_x2_ck { 656 + dpll_dsp_x2_ck: clock-dpll-dsp-x2 { 739 657 #clock-cells = <0>; 740 658 compatible = "ti,omap4-dpll-x2-clock"; 659 + clock-output-names = "dpll_dsp_x2_ck"; 741 660 clocks = <&dpll_dsp_ck>; 742 661 }; 743 662 744 - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { 663 + dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { 745 664 #clock-cells = <0>; 746 665 compatible = "ti,divider-clock"; 666 + clock-output-names = "dpll_dsp_m3x2_ck"; 747 667 clocks = <&dpll_dsp_x2_ck>; 748 668 ti,max-div = <31>; 749 669 ti,autoidle-shift = <8>; ··· 756 672 assigned-clock-rates = <400000000>; 757 673 }; 758 674 759 - dpll_gmac_x2_ck: dpll_gmac_x2_ck { 675 + dpll_gmac_x2_ck: clock-dpll-gmac-x2 { 760 676 #clock-cells = <0>; 761 677 compatible = "ti,omap4-dpll-x2-clock"; 678 + clock-output-names = "dpll_gmac_x2_ck"; 762 679 clocks = <&dpll_gmac_ck>; 763 680 }; 764 681 765 - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { 682 + dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { 766 683 #clock-cells = <0>; 767 684 compatible = "ti,divider-clock"; 685 + clock-output-names = "dpll_gmac_h11x2_ck"; 768 686 clocks = <&dpll_gmac_x2_ck>; 769 687 ti,max-div = <63>; 770 688 ti,autoidle-shift = <8>; ··· 775 689 ti,invert-autoidle-bit; 776 690 }; 777 691 778 - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { 692 + dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { 779 693 #clock-cells = <0>; 780 694 compatible = "ti,divider-clock"; 695 + clock-output-names = "dpll_gmac_h12x2_ck"; 781 696 clocks = <&dpll_gmac_x2_ck>; 782 697 ti,max-div = <63>; 783 698 ti,autoidle-shift = <8>; ··· 787 700 ti,invert-autoidle-bit; 788 701 }; 789 702 790 - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { 703 + dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { 791 704 #clock-cells = <0>; 792 705 compatible = "ti,divider-clock"; 706 + clock-output-names = "dpll_gmac_h13x2_ck"; 793 707 clocks = <&dpll_gmac_x2_ck>; 794 708 ti,max-div = <63>; 795 709 ti,autoidle-shift = <8>; ··· 799 711 ti,invert-autoidle-bit; 800 712 }; 801 713 802 - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { 714 + dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { 803 715 #clock-cells = <0>; 804 716 compatible = "ti,divider-clock"; 717 + clock-output-names = "dpll_gmac_m3x2_ck"; 805 718 clocks = <&dpll_gmac_x2_ck>; 806 719 ti,max-div = <31>; 807 720 ti,autoidle-shift = <8>; ··· 811 722 ti,invert-autoidle-bit; 812 723 }; 813 724 814 - gmii_m_clk_div: gmii_m_clk_div { 725 + gmii_m_clk_div: clock-gmii-m-clk-div { 815 726 #clock-cells = <0>; 816 727 compatible = "fixed-factor-clock"; 728 + clock-output-names = "gmii_m_clk_div"; 817 729 clocks = <&dpll_gmac_h11x2_ck>; 818 730 clock-mult = <1>; 819 731 clock-div = <2>; 820 732 }; 821 733 822 - hdmi_clk2_div: hdmi_clk2_div { 734 + hdmi_clk2_div: clock-hdmi-clk2-div { 823 735 #clock-cells = <0>; 824 736 compatible = "fixed-factor-clock"; 737 + clock-output-names = "hdmi_clk2_div"; 825 738 clocks = <&hdmi_clkin_ck>; 826 739 clock-mult = <1>; 827 740 clock-div = <1>; 828 741 }; 829 742 830 - hdmi_div_clk: hdmi_div_clk { 743 + hdmi_div_clk: clock-hdmi-div { 831 744 #clock-cells = <0>; 832 745 compatible = "fixed-factor-clock"; 746 + clock-output-names = "hdmi_div_clk"; 833 747 clocks = <&hdmi_clkin_ck>; 834 748 clock-mult = <1>; 835 749 clock-div = <1>; 836 750 }; 837 751 838 - l3_iclk_div: l3_iclk_div@100 { 752 + l3_iclk_div: clock-l3-iclk-div-4@100 { 839 753 #clock-cells = <0>; 840 754 compatible = "ti,divider-clock"; 755 + clock-output-names = "l3_iclk_div"; 841 756 ti,max-div = <2>; 842 757 ti,bit-shift = <4>; 843 758 reg = <0x0100>; ··· 849 756 ti,index-power-of-two; 850 757 }; 851 758 852 - l4_root_clk_div: l4_root_clk_div { 759 + l4_root_clk_div: clock-l4-root-clk-div { 853 760 #clock-cells = <0>; 854 761 compatible = "fixed-factor-clock"; 762 + clock-output-names = "l4_root_clk_div"; 855 763 clocks = <&l3_iclk_div>; 856 764 clock-mult = <1>; 857 765 clock-div = <2>; 858 766 }; 859 767 860 - video1_clk2_div: video1_clk2_div { 768 + video1_clk2_div: clock-video1-clk2-div { 861 769 #clock-cells = <0>; 862 770 compatible = "fixed-factor-clock"; 771 + clock-output-names = "video1_clk2_div"; 863 772 clocks = <&video1_clkin_ck>; 864 773 clock-mult = <1>; 865 774 clock-div = <1>; 866 775 }; 867 776 868 - video1_div_clk: video1_div_clk { 777 + video1_div_clk: clock-video1-div { 869 778 #clock-cells = <0>; 870 779 compatible = "fixed-factor-clock"; 780 + clock-output-names = "video1_div_clk"; 871 781 clocks = <&video1_clkin_ck>; 872 782 clock-mult = <1>; 873 783 clock-div = <1>; 874 784 }; 875 785 876 - video2_clk2_div: video2_clk2_div { 786 + video2_clk2_div: clock-video2-clk2-div { 877 787 #clock-cells = <0>; 878 788 compatible = "fixed-factor-clock"; 789 + clock-output-names = "video2_clk2_div"; 879 790 clocks = <&video2_clkin_ck>; 880 791 clock-mult = <1>; 881 792 clock-div = <1>; 882 793 }; 883 794 884 - video2_div_clk: video2_div_clk { 795 + video2_div_clk: clock-video2-div { 885 796 #clock-cells = <0>; 886 797 compatible = "fixed-factor-clock"; 798 + clock-output-names = "video2_div_clk"; 887 799 clocks = <&video2_clkin_ck>; 888 800 clock-mult = <1>; 889 801 clock-div = <1>; 890 802 }; 891 803 892 - dummy_ck: dummy_ck { 804 + dummy_ck: clock-dummy { 893 805 #clock-cells = <0>; 894 806 compatible = "fixed-clock"; 807 + clock-output-names = "dummy_ck"; 895 808 clock-frequency = <0>; 896 809 }; 897 810 }; 898 811 &prm_clocks { 899 - sys_clkin1: sys_clkin1@110 { 812 + sys_clkin1: clock-sys-clkin1@110 { 900 813 #clock-cells = <0>; 901 814 compatible = "ti,mux-clock"; 815 + clock-output-names = "sys_clkin1"; 902 816 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 903 817 reg = <0x0110>; 904 818 ti,index-starts-at-one; 905 819 }; 906 820 907 - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { 821 + abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { 908 822 #clock-cells = <0>; 909 823 compatible = "ti,mux-clock"; 824 + clock-output-names = "abe_dpll_sys_clk_mux"; 910 825 clocks = <&sys_clkin1>, <&sys_clkin2>; 911 826 reg = <0x0118>; 912 827 }; 913 828 914 - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { 829 + abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { 915 830 #clock-cells = <0>; 916 831 compatible = "ti,mux-clock"; 832 + clock-output-names = "abe_dpll_bypass_clk_mux"; 917 833 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; 918 834 reg = <0x0114>; 919 835 }; 920 836 921 - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { 837 + abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { 922 838 #clock-cells = <0>; 923 839 compatible = "ti,mux-clock"; 840 + clock-output-names = "abe_dpll_clk_mux"; 924 841 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; 925 842 reg = <0x010c>; 926 843 }; 927 844 928 - abe_24m_fclk: abe_24m_fclk@11c { 845 + abe_24m_fclk: clock-abe-24m@11c { 929 846 #clock-cells = <0>; 930 847 compatible = "ti,divider-clock"; 848 + clock-output-names = "abe_24m_fclk"; 931 849 clocks = <&dpll_abe_m2x2_ck>; 932 850 reg = <0x011c>; 933 851 ti,dividers = <8>, <16>; 934 852 }; 935 853 936 - aess_fclk: aess_fclk@178 { 854 + aess_fclk: clock-aess@178 { 937 855 #clock-cells = <0>; 938 856 compatible = "ti,divider-clock"; 857 + clock-output-names = "aess_fclk"; 939 858 clocks = <&abe_clk>; 940 859 reg = <0x0178>; 941 860 ti,max-div = <2>; 942 861 }; 943 862 944 - abe_giclk_div: abe_giclk_div@174 { 863 + abe_giclk_div: clock-abe-giclk-div@174 { 945 864 #clock-cells = <0>; 946 865 compatible = "ti,divider-clock"; 866 + clock-output-names = "abe_giclk_div"; 947 867 clocks = <&aess_fclk>; 948 868 reg = <0x0174>; 949 869 ti,max-div = <2>; 950 870 }; 951 871 952 - abe_lp_clk_div: abe_lp_clk_div@1d8 { 872 + abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { 953 873 #clock-cells = <0>; 954 874 compatible = "ti,divider-clock"; 875 + clock-output-names = "abe_lp_clk_div"; 955 876 clocks = <&dpll_abe_m2x2_ck>; 956 877 reg = <0x01d8>; 957 878 ti,dividers = <16>, <32>; 958 879 }; 959 880 960 - abe_sys_clk_div: abe_sys_clk_div@120 { 881 + abe_sys_clk_div: clock-abe-sys-clk-div@120 { 961 882 #clock-cells = <0>; 962 883 compatible = "ti,divider-clock"; 884 + clock-output-names = "abe_sys_clk_div"; 963 885 clocks = <&sys_clkin1>; 964 886 reg = <0x0120>; 965 887 ti,max-div = <2>; 966 888 }; 967 889 968 - adc_gfclk_mux: adc_gfclk_mux@1dc { 890 + adc_gfclk_mux: clock-adc-gfclk-mux@1dc { 969 891 #clock-cells = <0>; 970 892 compatible = "ti,mux-clock"; 893 + clock-output-names = "adc_gfclk_mux"; 971 894 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; 972 895 reg = <0x01dc>; 973 896 }; 974 897 975 - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { 898 + sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { 976 899 #clock-cells = <0>; 977 900 compatible = "ti,divider-clock"; 901 + clock-output-names = "sys_clk1_dclk_div"; 978 902 clocks = <&sys_clkin1>; 979 903 ti,max-div = <64>; 980 904 reg = <0x01c8>; 981 905 ti,index-power-of-two; 982 906 }; 983 907 984 - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { 908 + sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { 985 909 #clock-cells = <0>; 986 910 compatible = "ti,divider-clock"; 911 + clock-output-names = "sys_clk2_dclk_div"; 987 912 clocks = <&sys_clkin2>; 988 913 ti,max-div = <64>; 989 914 reg = <0x01cc>; 990 915 ti,index-power-of-two; 991 916 }; 992 917 993 - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { 918 + per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { 994 919 #clock-cells = <0>; 995 920 compatible = "ti,divider-clock"; 921 + clock-output-names = "per_abe_x1_dclk_div"; 996 922 clocks = <&dpll_abe_m2_ck>; 997 923 ti,max-div = <64>; 998 924 reg = <0x01bc>; 999 925 ti,index-power-of-two; 1000 926 }; 1001 927 1002 - dsp_gclk_div: dsp_gclk_div@18c { 928 + dsp_gclk_div: clock-dsp-gclk-div@18c { 1003 929 #clock-cells = <0>; 1004 930 compatible = "ti,divider-clock"; 931 + clock-output-names = "dsp_gclk_div"; 1005 932 clocks = <&dpll_dsp_m2_ck>; 1006 933 ti,max-div = <64>; 1007 934 reg = <0x018c>; 1008 935 ti,index-power-of-two; 1009 936 }; 1010 937 1011 - gpu_dclk: gpu_dclk@1a0 { 938 + gpu_dclk: clock-gpu-dclk@1a0 { 1012 939 #clock-cells = <0>; 1013 940 compatible = "ti,divider-clock"; 941 + clock-output-names = "gpu_dclk"; 1014 942 clocks = <&dpll_gpu_m2_ck>; 1015 943 ti,max-div = <64>; 1016 944 reg = <0x01a0>; 1017 945 ti,index-power-of-two; 1018 946 }; 1019 947 1020 - emif_phy_dclk_div: emif_phy_dclk_div@190 { 948 + emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { 1021 949 #clock-cells = <0>; 1022 950 compatible = "ti,divider-clock"; 951 + clock-output-names = "emif_phy_dclk_div"; 1023 952 clocks = <&dpll_ddr_m2_ck>; 1024 953 ti,max-div = <64>; 1025 954 reg = <0x0190>; 1026 955 ti,index-power-of-two; 1027 956 }; 1028 957 1029 - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { 958 + gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { 1030 959 #clock-cells = <0>; 1031 960 compatible = "ti,divider-clock"; 961 + clock-output-names = "gmac_250m_dclk_div"; 1032 962 clocks = <&dpll_gmac_m2_ck>; 1033 963 ti,max-div = <64>; 1034 964 reg = <0x019c>; 1035 965 ti,index-power-of-two; 1036 966 }; 1037 967 1038 - gmac_main_clk: gmac_main_clk { 968 + gmac_main_clk: clock-gmac-main { 1039 969 #clock-cells = <0>; 1040 970 compatible = "fixed-factor-clock"; 971 + clock-output-names = "gmac_main_clk"; 1041 972 clocks = <&gmac_250m_dclk_div>; 1042 973 clock-mult = <1>; 1043 974 clock-div = <2>; 1044 975 }; 1045 976 1046 - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { 977 + l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { 1047 978 #clock-cells = <0>; 1048 979 compatible = "ti,divider-clock"; 980 + clock-output-names = "l3init_480m_dclk_div"; 1049 981 clocks = <&dpll_usb_m2_ck>; 1050 982 ti,max-div = <64>; 1051 983 reg = <0x01ac>; 1052 984 ti,index-power-of-two; 1053 985 }; 1054 986 1055 - usb_otg_dclk_div: usb_otg_dclk_div@184 { 987 + usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { 1056 988 #clock-cells = <0>; 1057 989 compatible = "ti,divider-clock"; 990 + clock-output-names = "usb_otg_dclk_div"; 1058 991 clocks = <&usb_otg_clkin_ck>; 1059 992 ti,max-div = <64>; 1060 993 reg = <0x0184>; 1061 994 ti,index-power-of-two; 1062 995 }; 1063 996 1064 - sata_dclk_div: sata_dclk_div@1c0 { 997 + sata_dclk_div: clock-sata-dclk-div@1c0 { 1065 998 #clock-cells = <0>; 1066 999 compatible = "ti,divider-clock"; 1000 + clock-output-names = "sata_dclk_div"; 1067 1001 clocks = <&sys_clkin1>; 1068 1002 ti,max-div = <64>; 1069 1003 reg = <0x01c0>; 1070 1004 ti,index-power-of-two; 1071 1005 }; 1072 1006 1073 - pcie2_dclk_div: pcie2_dclk_div@1b8 { 1007 + pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { 1074 1008 #clock-cells = <0>; 1075 1009 compatible = "ti,divider-clock"; 1010 + clock-output-names = "pcie2_dclk_div"; 1076 1011 clocks = <&dpll_pcie_ref_m2_ck>; 1077 1012 ti,max-div = <64>; 1078 1013 reg = <0x01b8>; 1079 1014 ti,index-power-of-two; 1080 1015 }; 1081 1016 1082 - pcie_dclk_div: pcie_dclk_div@1b4 { 1017 + pcie_dclk_div: clock-pcie-dclk-div@1b4 { 1083 1018 #clock-cells = <0>; 1084 1019 compatible = "ti,divider-clock"; 1020 + clock-output-names = "pcie_dclk_div"; 1085 1021 clocks = <&apll_pcie_m2_ck>; 1086 1022 ti,max-div = <64>; 1087 1023 reg = <0x01b4>; 1088 1024 ti,index-power-of-two; 1089 1025 }; 1090 1026 1091 - emu_dclk_div: emu_dclk_div@194 { 1027 + emu_dclk_div: clock-emu-dclk-div@194 { 1092 1028 #clock-cells = <0>; 1093 1029 compatible = "ti,divider-clock"; 1030 + clock-output-names = "emu_dclk_div"; 1094 1031 clocks = <&sys_clkin1>; 1095 1032 ti,max-div = <64>; 1096 1033 reg = <0x0194>; 1097 1034 ti,index-power-of-two; 1098 1035 }; 1099 1036 1100 - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { 1037 + secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { 1101 1038 #clock-cells = <0>; 1102 1039 compatible = "ti,divider-clock"; 1040 + clock-output-names = "secure_32k_dclk_div"; 1103 1041 clocks = <&secure_32k_clk_src_ck>; 1104 1042 ti,max-div = <64>; 1105 1043 reg = <0x01c4>; 1106 1044 ti,index-power-of-two; 1107 1045 }; 1108 1046 1109 - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { 1047 + clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { 1110 1048 #clock-cells = <0>; 1111 1049 compatible = "ti,mux-clock"; 1050 + clock-output-names = "clkoutmux0_clk_mux"; 1112 1051 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1113 1052 reg = <0x0158>; 1114 1053 }; 1115 1054 1116 - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { 1055 + clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { 1117 1056 #clock-cells = <0>; 1118 1057 compatible = "ti,mux-clock"; 1058 + clock-output-names = "clkoutmux1_clk_mux"; 1119 1059 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1120 1060 reg = <0x015c>; 1121 1061 }; 1122 1062 1123 - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { 1063 + clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { 1124 1064 #clock-cells = <0>; 1125 1065 compatible = "ti,mux-clock"; 1066 + clock-output-names = "clkoutmux2_clk_mux"; 1126 1067 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1127 1068 reg = <0x0160>; 1128 1069 }; 1129 1070 1130 - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { 1071 + custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { 1131 1072 #clock-cells = <0>; 1132 1073 compatible = "fixed-factor-clock"; 1074 + clock-output-names = "custefuse_sys_gfclk_div"; 1133 1075 clocks = <&sys_clkin1>; 1134 1076 clock-mult = <1>; 1135 1077 clock-div = <2>; 1136 1078 }; 1137 1079 1138 - eve_clk: eve_clk@180 { 1080 + eve_clk: clock-eve@180 { 1139 1081 #clock-cells = <0>; 1140 1082 compatible = "ti,mux-clock"; 1083 + clock-output-names = "eve_clk"; 1141 1084 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; 1142 1085 reg = <0x0180>; 1143 1086 }; 1144 1087 1145 - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { 1088 + hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { 1146 1089 #clock-cells = <0>; 1147 1090 compatible = "ti,mux-clock"; 1091 + clock-output-names = "hdmi_dpll_clk_mux"; 1148 1092 clocks = <&sys_clkin1>, <&sys_clkin2>; 1149 1093 reg = <0x0164>; 1150 1094 }; 1151 1095 1152 - mlb_clk: mlb_clk@134 { 1096 + mlb_clk: clock-mlb@134 { 1153 1097 #clock-cells = <0>; 1154 1098 compatible = "ti,divider-clock"; 1099 + clock-output-names = "mlb_clk"; 1155 1100 clocks = <&mlb_clkin_ck>; 1156 1101 ti,max-div = <64>; 1157 1102 reg = <0x0134>; 1158 1103 ti,index-power-of-two; 1159 1104 }; 1160 1105 1161 - mlbp_clk: mlbp_clk@130 { 1106 + mlbp_clk: clock-mlbp@130 { 1162 1107 #clock-cells = <0>; 1163 1108 compatible = "ti,divider-clock"; 1109 + clock-output-names = "mlbp_clk"; 1164 1110 clocks = <&mlbp_clkin_ck>; 1165 1111 ti,max-div = <64>; 1166 1112 reg = <0x0130>; 1167 1113 ti,index-power-of-two; 1168 1114 }; 1169 1115 1170 - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { 1116 + per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { 1171 1117 #clock-cells = <0>; 1172 1118 compatible = "ti,divider-clock"; 1119 + clock-output-names = "per_abe_x1_gfclk2_div"; 1173 1120 clocks = <&dpll_abe_m2_ck>; 1174 1121 ti,max-div = <64>; 1175 1122 reg = <0x0138>; 1176 1123 ti,index-power-of-two; 1177 1124 }; 1178 1125 1179 - timer_sys_clk_div: timer_sys_clk_div@144 { 1126 + timer_sys_clk_div: clock-timer-sys-clk-div@144 { 1180 1127 #clock-cells = <0>; 1181 1128 compatible = "ti,divider-clock"; 1129 + clock-output-names = "timer_sys_clk_div"; 1182 1130 clocks = <&sys_clkin1>; 1183 1131 reg = <0x0144>; 1184 1132 ti,max-div = <2>; 1185 1133 }; 1186 1134 1187 - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { 1135 + video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { 1188 1136 #clock-cells = <0>; 1189 1137 compatible = "ti,mux-clock"; 1138 + clock-output-names = "video1_dpll_clk_mux"; 1190 1139 clocks = <&sys_clkin1>, <&sys_clkin2>; 1191 1140 reg = <0x0168>; 1192 1141 }; 1193 1142 1194 - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { 1143 + video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { 1195 1144 #clock-cells = <0>; 1196 1145 compatible = "ti,mux-clock"; 1146 + clock-output-names = "video2_dpll_clk_mux"; 1197 1147 clocks = <&sys_clkin1>, <&sys_clkin2>; 1198 1148 reg = <0x016c>; 1199 1149 }; 1200 1150 1201 - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { 1151 + wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { 1202 1152 #clock-cells = <0>; 1203 1153 compatible = "ti,mux-clock"; 1154 + clock-output-names = "wkupaon_iclk_mux"; 1204 1155 clocks = <&sys_clkin1>, <&abe_lp_clk_div>; 1205 1156 reg = <0x0108>; 1206 1157 }; 1207 1158 }; 1208 1159 1209 1160 &cm_core_clocks { 1210 - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { 1161 + dpll_pcie_ref_ck: clock@200 { 1211 1162 #clock-cells = <0>; 1212 1163 compatible = "ti,omap4-dpll-clock"; 1164 + clock-output-names = "dpll_pcie_ref_ck"; 1213 1165 clocks = <&sys_clkin1>, <&sys_clkin1>; 1214 1166 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; 1215 1167 }; 1216 1168 1217 - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { 1169 + dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { 1218 1170 #clock-cells = <0>; 1219 1171 compatible = "ti,divider-clock"; 1172 + clock-output-names = "dpll_pcie_ref_m2ldo_ck"; 1220 1173 clocks = <&dpll_pcie_ref_ck>; 1221 1174 ti,max-div = <31>; 1222 1175 ti,autoidle-shift = <8>; ··· 1271 1132 ti,invert-autoidle-bit; 1272 1133 }; 1273 1134 1274 - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { 1135 + apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { 1275 1136 compatible = "ti,mux-clock"; 1137 + clock-output-names = "apll_pcie_in_clk_mux"; 1276 1138 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; 1277 1139 #clock-cells = <0>; 1278 1140 reg = <0x021c 0x4>; 1279 1141 ti,bit-shift = <7>; 1280 1142 }; 1281 1143 1282 - apll_pcie_ck: apll_pcie_ck@21c { 1144 + apll_pcie_ck: clock@21c { 1283 1145 #clock-cells = <0>; 1284 1146 compatible = "ti,dra7-apll-clock"; 1147 + clock-output-names = "apll_pcie_ck"; 1285 1148 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; 1286 1149 reg = <0x021c>, <0x0220>; 1287 1150 }; 1288 1151 1289 - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { 1152 + optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { 1290 1153 compatible = "ti,divider-clock"; 1154 + clock-output-names = "optfclk_pciephy_div"; 1291 1155 clocks = <&apll_pcie_ck>; 1292 1156 #clock-cells = <0>; 1293 1157 reg = <0x021c>; ··· 1299 1157 ti,max-div = <2>; 1300 1158 }; 1301 1159 1302 - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { 1160 + apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { 1303 1161 #clock-cells = <0>; 1304 1162 compatible = "fixed-factor-clock"; 1163 + clock-output-names = "apll_pcie_clkvcoldo"; 1305 1164 clocks = <&apll_pcie_ck>; 1306 1165 clock-mult = <1>; 1307 1166 clock-div = <1>; 1308 1167 }; 1309 1168 1310 - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { 1169 + apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { 1311 1170 #clock-cells = <0>; 1312 1171 compatible = "fixed-factor-clock"; 1172 + clock-output-names = "apll_pcie_clkvcoldo_div"; 1313 1173 clocks = <&apll_pcie_ck>; 1314 1174 clock-mult = <1>; 1315 1175 clock-div = <1>; 1316 1176 }; 1317 1177 1318 - apll_pcie_m2_ck: apll_pcie_m2_ck { 1178 + apll_pcie_m2_ck: clock-apll-pcie-m2 { 1319 1179 #clock-cells = <0>; 1320 1180 compatible = "fixed-factor-clock"; 1181 + clock-output-names = "apll_pcie_m2_ck"; 1321 1182 clocks = <&apll_pcie_ck>; 1322 1183 clock-mult = <1>; 1323 1184 clock-div = <1>; 1324 1185 }; 1325 1186 1326 - dpll_per_byp_mux: dpll_per_byp_mux@14c { 1187 + dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { 1327 1188 #clock-cells = <0>; 1328 1189 compatible = "ti,mux-clock"; 1190 + clock-output-names = "dpll_per_byp_mux"; 1329 1191 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1330 1192 ti,bit-shift = <23>; 1331 1193 reg = <0x014c>; 1332 1194 }; 1333 1195 1334 - dpll_per_ck: dpll_per_ck@140 { 1196 + dpll_per_ck: clock@140 { 1335 1197 #clock-cells = <0>; 1336 1198 compatible = "ti,omap4-dpll-clock"; 1199 + clock-output-names = "dpll_per_ck"; 1337 1200 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; 1338 1201 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 1339 1202 }; 1340 1203 1341 - dpll_per_m2_ck: dpll_per_m2_ck@150 { 1204 + dpll_per_m2_ck: clock-dpll-per-m2-8@150 { 1342 1205 #clock-cells = <0>; 1343 1206 compatible = "ti,divider-clock"; 1207 + clock-output-names = "dpll_per_m2_ck"; 1344 1208 clocks = <&dpll_per_ck>; 1345 1209 ti,max-div = <31>; 1346 1210 ti,autoidle-shift = <8>; ··· 1355 1207 ti,invert-autoidle-bit; 1356 1208 }; 1357 1209 1358 - func_96m_aon_dclk_div: func_96m_aon_dclk_div { 1210 + func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { 1359 1211 #clock-cells = <0>; 1360 1212 compatible = "fixed-factor-clock"; 1213 + clock-output-names = "func_96m_aon_dclk_div"; 1361 1214 clocks = <&dpll_per_m2_ck>; 1362 1215 clock-mult = <1>; 1363 1216 clock-div = <1>; 1364 1217 }; 1365 1218 1366 - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { 1219 + dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { 1367 1220 #clock-cells = <0>; 1368 1221 compatible = "ti,mux-clock"; 1222 + clock-output-names = "dpll_usb_byp_mux"; 1369 1223 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1370 1224 ti,bit-shift = <23>; 1371 1225 reg = <0x018c>; 1372 1226 }; 1373 1227 1374 - dpll_usb_ck: dpll_usb_ck@180 { 1228 + dpll_usb_ck: clock@180 { 1375 1229 #clock-cells = <0>; 1376 1230 compatible = "ti,omap4-dpll-j-type-clock"; 1231 + clock-output-names = "dpll_usb_ck"; 1377 1232 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; 1378 1233 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 1379 1234 }; 1380 1235 1381 - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { 1236 + dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { 1382 1237 #clock-cells = <0>; 1383 1238 compatible = "ti,divider-clock"; 1239 + clock-output-names = "dpll_usb_m2_ck"; 1384 1240 clocks = <&dpll_usb_ck>; 1385 1241 ti,max-div = <127>; 1386 1242 ti,autoidle-shift = <8>; ··· 1393 1241 ti,invert-autoidle-bit; 1394 1242 }; 1395 1243 1396 - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { 1244 + dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { 1397 1245 #clock-cells = <0>; 1398 1246 compatible = "ti,divider-clock"; 1247 + clock-output-names = "dpll_pcie_ref_m2_ck"; 1399 1248 clocks = <&dpll_pcie_ref_ck>; 1400 1249 ti,max-div = <127>; 1401 1250 ti,autoidle-shift = <8>; ··· 1405 1252 ti,invert-autoidle-bit; 1406 1253 }; 1407 1254 1408 - dpll_per_x2_ck: dpll_per_x2_ck { 1255 + dpll_per_x2_ck: clock-dpll-per-x2 { 1409 1256 #clock-cells = <0>; 1410 1257 compatible = "ti,omap4-dpll-x2-clock"; 1258 + clock-output-names = "dpll_per_x2_ck"; 1411 1259 clocks = <&dpll_per_ck>; 1412 1260 }; 1413 1261 1414 - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { 1262 + dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { 1415 1263 #clock-cells = <0>; 1416 1264 compatible = "ti,divider-clock"; 1265 + clock-output-names = "dpll_per_h11x2_ck"; 1417 1266 clocks = <&dpll_per_x2_ck>; 1418 1267 ti,max-div = <63>; 1419 1268 ti,autoidle-shift = <8>; ··· 1424 1269 ti,invert-autoidle-bit; 1425 1270 }; 1426 1271 1427 - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { 1272 + dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { 1428 1273 #clock-cells = <0>; 1429 1274 compatible = "ti,divider-clock"; 1275 + clock-output-names = "dpll_per_h12x2_ck"; 1430 1276 clocks = <&dpll_per_x2_ck>; 1431 1277 ti,max-div = <63>; 1432 1278 ti,autoidle-shift = <8>; ··· 1436 1280 ti,invert-autoidle-bit; 1437 1281 }; 1438 1282 1439 - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { 1283 + dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { 1440 1284 #clock-cells = <0>; 1441 1285 compatible = "ti,divider-clock"; 1286 + clock-output-names = "dpll_per_h13x2_ck"; 1442 1287 clocks = <&dpll_per_x2_ck>; 1443 1288 ti,max-div = <63>; 1444 1289 ti,autoidle-shift = <8>; ··· 1448 1291 ti,invert-autoidle-bit; 1449 1292 }; 1450 1293 1451 - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { 1294 + dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { 1452 1295 #clock-cells = <0>; 1453 1296 compatible = "ti,divider-clock"; 1297 + clock-output-names = "dpll_per_h14x2_ck"; 1454 1298 clocks = <&dpll_per_x2_ck>; 1455 1299 ti,max-div = <63>; 1456 1300 ti,autoidle-shift = <8>; ··· 1460 1302 ti,invert-autoidle-bit; 1461 1303 }; 1462 1304 1463 - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { 1305 + dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { 1464 1306 #clock-cells = <0>; 1465 1307 compatible = "ti,divider-clock"; 1308 + clock-output-names = "dpll_per_m2x2_ck"; 1466 1309 clocks = <&dpll_per_x2_ck>; 1467 1310 ti,max-div = <31>; 1468 1311 ti,autoidle-shift = <8>; ··· 1472 1313 ti,invert-autoidle-bit; 1473 1314 }; 1474 1315 1475 - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { 1316 + dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { 1476 1317 #clock-cells = <0>; 1477 1318 compatible = "fixed-factor-clock"; 1319 + clock-output-names = "dpll_usb_clkdcoldo"; 1478 1320 clocks = <&dpll_usb_ck>; 1479 1321 clock-mult = <1>; 1480 1322 clock-div = <1>; 1481 1323 }; 1482 1324 1483 - func_128m_clk: func_128m_clk { 1325 + func_128m_clk: clock-func-128m { 1484 1326 #clock-cells = <0>; 1485 1327 compatible = "fixed-factor-clock"; 1328 + clock-output-names = "func_128m_clk"; 1486 1329 clocks = <&dpll_per_h11x2_ck>; 1487 1330 clock-mult = <1>; 1488 1331 clock-div = <2>; 1489 1332 }; 1490 1333 1491 - func_12m_fclk: func_12m_fclk { 1334 + func_12m_fclk: clock-func-12m-fclk { 1492 1335 #clock-cells = <0>; 1493 1336 compatible = "fixed-factor-clock"; 1337 + clock-output-names = "func_12m_fclk"; 1494 1338 clocks = <&dpll_per_m2x2_ck>; 1495 1339 clock-mult = <1>; 1496 1340 clock-div = <16>; 1497 1341 }; 1498 1342 1499 - func_24m_clk: func_24m_clk { 1343 + func_24m_clk: clock-func-24m { 1500 1344 #clock-cells = <0>; 1501 1345 compatible = "fixed-factor-clock"; 1346 + clock-output-names = "func_24m_clk"; 1502 1347 clocks = <&dpll_per_m2_ck>; 1503 1348 clock-mult = <1>; 1504 1349 clock-div = <4>; 1505 1350 }; 1506 1351 1507 - func_48m_fclk: func_48m_fclk { 1352 + func_48m_fclk: clock-func-48m-fclk { 1508 1353 #clock-cells = <0>; 1509 1354 compatible = "fixed-factor-clock"; 1355 + clock-output-names = "func_48m_fclk"; 1510 1356 clocks = <&dpll_per_m2x2_ck>; 1511 1357 clock-mult = <1>; 1512 1358 clock-div = <4>; 1513 1359 }; 1514 1360 1515 - func_96m_fclk: func_96m_fclk { 1361 + func_96m_fclk: clock-func-96m-fclk { 1516 1362 #clock-cells = <0>; 1517 1363 compatible = "fixed-factor-clock"; 1364 + clock-output-names = "func_96m_fclk"; 1518 1365 clocks = <&dpll_per_m2x2_ck>; 1519 1366 clock-mult = <1>; 1520 1367 clock-div = <2>; 1521 1368 }; 1522 1369 1523 - l3init_60m_fclk: l3init_60m_fclk@104 { 1370 + l3init_60m_fclk: clock-l3init-60m@104 { 1524 1371 #clock-cells = <0>; 1525 1372 compatible = "ti,divider-clock"; 1373 + clock-output-names = "l3init_60m_fclk"; 1526 1374 clocks = <&dpll_usb_m2_ck>; 1527 1375 reg = <0x0104>; 1528 1376 ti,dividers = <1>, <8>; 1529 1377 }; 1530 1378 1531 - clkout2_clk: clkout2_clk@6b0 { 1379 + clkout2_clk: clock-clkout2-8@6b0 { 1532 1380 #clock-cells = <0>; 1533 1381 compatible = "ti,gate-clock"; 1382 + clock-output-names = "clkout2_clk"; 1534 1383 clocks = <&clkoutmux2_clk_mux>; 1535 1384 ti,bit-shift = <8>; 1536 1385 reg = <0x06b0>; 1537 1386 }; 1538 1387 1539 - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { 1388 + l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { 1540 1389 #clock-cells = <0>; 1541 1390 compatible = "ti,gate-clock"; 1391 + clock-output-names = "l3init_960m_gfclk"; 1542 1392 clocks = <&dpll_usb_clkdcoldo>; 1543 1393 ti,bit-shift = <8>; 1544 1394 reg = <0x06c0>; 1545 1395 }; 1546 1396 1547 - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { 1397 + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { 1548 1398 #clock-cells = <0>; 1549 1399 compatible = "ti,gate-clock"; 1400 + clock-output-names = "usb_phy1_always_on_clk32k"; 1550 1401 clocks = <&sys_32k_ck>; 1551 1402 ti,bit-shift = <8>; 1552 1403 reg = <0x0640>; 1553 1404 }; 1554 1405 1555 - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { 1406 + usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { 1556 1407 #clock-cells = <0>; 1557 1408 compatible = "ti,gate-clock"; 1409 + clock-output-names = "usb_phy2_always_on_clk32k"; 1558 1410 clocks = <&sys_32k_ck>; 1559 1411 ti,bit-shift = <8>; 1560 1412 reg = <0x0688>; 1561 1413 }; 1562 1414 1563 - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { 1415 + usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { 1564 1416 #clock-cells = <0>; 1565 1417 compatible = "ti,gate-clock"; 1418 + clock-output-names = "usb_phy3_always_on_clk32k"; 1566 1419 clocks = <&sys_32k_ck>; 1567 1420 ti,bit-shift = <8>; 1568 1421 reg = <0x0698>; 1569 1422 }; 1570 1423 1571 - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { 1424 + gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { 1572 1425 #clock-cells = <0>; 1573 1426 compatible = "ti,mux-clock"; 1427 + clock-output-names = "gpu_core_gclk_mux"; 1574 1428 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; 1575 1429 ti,bit-shift = <24>; 1576 1430 reg = <0x1220>; ··· 1591 1419 assigned-clock-parents = <&dpll_gpu_m2_ck>; 1592 1420 }; 1593 1421 1594 - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { 1422 + gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { 1595 1423 #clock-cells = <0>; 1596 1424 compatible = "ti,mux-clock"; 1425 + clock-output-names = "gpu_hyd_gclk_mux"; 1597 1426 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; 1598 1427 ti,bit-shift = <26>; 1599 1428 reg = <0x1220>; ··· 1602 1429 assigned-clock-parents = <&dpll_gpu_m2_ck>; 1603 1430 }; 1604 1431 1605 - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { 1432 + l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { 1606 1433 #clock-cells = <0>; 1607 1434 compatible = "ti,divider-clock"; 1435 + clock-output-names = "l3instr_ts_gclk_div"; 1608 1436 clocks = <&wkupaon_iclk_mux>; 1609 1437 ti,bit-shift = <24>; 1610 1438 reg = <0x0e50>; 1611 1439 ti,dividers = <8>, <16>, <32>; 1612 1440 }; 1613 1441 1614 - vip1_gclk_mux: vip1_gclk_mux@1020 { 1442 + vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { 1615 1443 #clock-cells = <0>; 1616 1444 compatible = "ti,mux-clock"; 1445 + clock-output-names = "vip1_gclk_mux"; 1617 1446 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1618 1447 ti,bit-shift = <24>; 1619 1448 reg = <0x1020>; 1620 1449 }; 1621 1450 1622 - vip2_gclk_mux: vip2_gclk_mux@1028 { 1451 + vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { 1623 1452 #clock-cells = <0>; 1624 1453 compatible = "ti,mux-clock"; 1454 + clock-output-names = "vip2_gclk_mux"; 1625 1455 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1626 1456 ti,bit-shift = <24>; 1627 1457 reg = <0x1028>; 1628 1458 }; 1629 1459 1630 - vip3_gclk_mux: vip3_gclk_mux@1030 { 1460 + vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { 1631 1461 #clock-cells = <0>; 1632 1462 compatible = "ti,mux-clock"; 1463 + clock-output-names = "vip3_gclk_mux"; 1633 1464 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1634 1465 ti,bit-shift = <24>; 1635 1466 reg = <0x1030>; ··· 1641 1464 }; 1642 1465 1643 1466 &cm_core_clockdomains { 1644 - coreaon_clkdm: coreaon_clkdm { 1467 + coreaon_clkdm: clock-coreaon-clkdm { 1645 1468 compatible = "ti,clockdomain"; 1469 + clock-output-names = "coreaon_clkdm"; 1646 1470 clocks = <&dpll_usb_ck>; 1647 1471 }; 1648 1472 }; 1649 1473 1650 1474 &scm_conf_clocks { 1651 - dss_deshdcp_clk: dss_deshdcp_clk@558 { 1475 + dss_deshdcp_clk: clock-dss-deshdcp-0@558 { 1652 1476 #clock-cells = <0>; 1653 1477 compatible = "ti,gate-clock"; 1478 + clock-output-names = "dss_deshdcp_clk"; 1654 1479 clocks = <&l3_iclk_div>; 1655 1480 ti,bit-shift = <0>; 1656 1481 reg = <0x558>; 1657 1482 }; 1658 1483 1659 - ehrpwm0_tbclk: ehrpwm0_tbclk@558 { 1484 + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { 1660 1485 #clock-cells = <0>; 1661 1486 compatible = "ti,gate-clock"; 1487 + clock-output-names = "ehrpwm0_tbclk"; 1662 1488 clocks = <&l4_root_clk_div>; 1663 1489 ti,bit-shift = <20>; 1664 1490 reg = <0x0558>; 1665 1491 }; 1666 1492 1667 - ehrpwm1_tbclk: ehrpwm1_tbclk@558 { 1493 + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { 1668 1494 #clock-cells = <0>; 1669 1495 compatible = "ti,gate-clock"; 1496 + clock-output-names = "ehrpwm1_tbclk"; 1670 1497 clocks = <&l4_root_clk_div>; 1671 1498 ti,bit-shift = <21>; 1672 1499 reg = <0x0558>; 1673 1500 }; 1674 1501 1675 - ehrpwm2_tbclk: ehrpwm2_tbclk@558 { 1502 + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { 1676 1503 #clock-cells = <0>; 1677 1504 compatible = "ti,gate-clock"; 1505 + clock-output-names = "ehrpwm2_tbclk"; 1678 1506 clocks = <&l4_root_clk_div>; 1679 1507 ti,bit-shift = <22>; 1680 1508 reg = <0x0558>; 1681 1509 }; 1682 1510 1683 - sys_32k_ck: sys_32k_ck { 1511 + sys_32k_ck: clock-sys-32k { 1684 1512 #clock-cells = <0>; 1685 1513 compatible = "ti,mux-clock"; 1514 + clock-output-names = "sys_32k_ck"; 1686 1515 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; 1687 1516 ti,bit-shift = <8>; 1688 1517 reg = <0x6c4>; ··· 1696 1513 }; 1697 1514 1698 1515 &cm_core_aon { 1699 - mpu_cm: mpu-cm@300 { 1516 + mpu_cm: clock@300 { 1700 1517 compatible = "ti,omap4-cm"; 1518 + clock-output-names = "mpu_cm"; 1701 1519 reg = <0x300 0x100>; 1702 1520 #address-cells = <1>; 1703 1521 #size-cells = <1>; 1704 1522 ranges = <0 0x300 0x100>; 1705 1523 1706 - mpu_clkctrl: mpu-clkctrl@20 { 1524 + mpu_clkctrl: clock@20 { 1707 1525 compatible = "ti,clkctrl"; 1526 + clock-output-names = "mpu_clkctrl"; 1708 1527 reg = <0x20 0x4>; 1709 1528 #clock-cells = <2>; 1710 1529 }; 1711 1530 1712 1531 }; 1713 1532 1714 - dsp1_cm: dsp1-cm@400 { 1533 + dsp1_cm: clock@400 { 1715 1534 compatible = "ti,omap4-cm"; 1535 + clock-output-names = "dsp1_cm"; 1716 1536 reg = <0x400 0x100>; 1717 1537 #address-cells = <1>; 1718 1538 #size-cells = <1>; 1719 1539 ranges = <0 0x400 0x100>; 1720 1540 1721 - dsp1_clkctrl: dsp1-clkctrl@20 { 1541 + dsp1_clkctrl: clock@20 { 1722 1542 compatible = "ti,clkctrl"; 1543 + clock-output-names = "dsp1_clkctrl"; 1723 1544 reg = <0x20 0x4>; 1724 1545 #clock-cells = <2>; 1725 1546 }; 1726 1547 1727 1548 }; 1728 1549 1729 - ipu_cm: ipu-cm@500 { 1550 + ipu_cm: clock@500 { 1730 1551 compatible = "ti,omap4-cm"; 1552 + clock-output-names = "ipu_cm"; 1731 1553 reg = <0x500 0x100>; 1732 1554 #address-cells = <1>; 1733 1555 #size-cells = <1>; 1734 1556 ranges = <0 0x500 0x100>; 1735 1557 1736 - ipu1_clkctrl: ipu1-clkctrl@20 { 1558 + ipu1_clkctrl: clock@20 { 1737 1559 compatible = "ti,clkctrl"; 1560 + clock-output-names = "ipu1_clkctrl"; 1738 1561 reg = <0x20 0x4>; 1739 1562 #clock-cells = <2>; 1740 1563 assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; 1741 1564 assigned-clock-parents = <&dpll_core_h22x2_ck>; 1742 1565 }; 1743 1566 1744 - ipu_clkctrl: ipu-clkctrl@50 { 1567 + ipu_clkctrl: clock@50 { 1745 1568 compatible = "ti,clkctrl"; 1569 + clock-output-names = "ipu_clkctrl"; 1746 1570 reg = <0x50 0x34>; 1747 1571 #clock-cells = <2>; 1748 1572 }; 1749 1573 1750 1574 }; 1751 1575 1752 - dsp2_cm: dsp2-cm@600 { 1576 + dsp2_cm: clock@600 { 1753 1577 compatible = "ti,omap4-cm"; 1578 + clock-output-names = "dsp2_cm"; 1754 1579 reg = <0x600 0x100>; 1755 1580 #address-cells = <1>; 1756 1581 #size-cells = <1>; 1757 1582 ranges = <0 0x600 0x100>; 1758 1583 1759 - dsp2_clkctrl: dsp2-clkctrl@20 { 1584 + dsp2_clkctrl: clock@20 { 1760 1585 compatible = "ti,clkctrl"; 1586 + clock-output-names = "dsp2_clkctrl"; 1761 1587 reg = <0x20 0x4>; 1762 1588 #clock-cells = <2>; 1763 1589 }; 1764 1590 1765 1591 }; 1766 1592 1767 - rtc_cm: rtc-cm@700 { 1593 + rtc_cm: clock@700 { 1768 1594 compatible = "ti,omap4-cm"; 1595 + clock-output-names = "rtc_cm"; 1769 1596 reg = <0x700 0x60>; 1770 1597 #address-cells = <1>; 1771 1598 #size-cells = <1>; 1772 1599 ranges = <0 0x700 0x60>; 1773 1600 1774 - rtc_clkctrl: rtc-clkctrl@20 { 1601 + rtc_clkctrl: clock@20 { 1775 1602 compatible = "ti,clkctrl"; 1603 + clock-output-names = "rtc_clkctrl"; 1776 1604 reg = <0x20 0x28>; 1777 1605 #clock-cells = <2>; 1778 1606 }; 1779 1607 }; 1780 1608 1781 - vpe_cm: vpe-cm@760 { 1609 + vpe_cm: clock@760 { 1782 1610 compatible = "ti,omap4-cm"; 1611 + clock-output-names = "vpe_cm"; 1783 1612 reg = <0x760 0xc>; 1784 1613 #address-cells = <1>; 1785 1614 #size-cells = <1>; 1786 1615 ranges = <0 0x760 0xc>; 1787 1616 1788 - vpe_clkctrl: vpe-clkctrl@0 { 1617 + vpe_clkctrl: clock@0 { 1789 1618 compatible = "ti,clkctrl"; 1619 + clock-output-names = "vpe_clkctrl"; 1790 1620 reg = <0x0 0xc>; 1791 1621 #clock-cells = <2>; 1792 1622 }; ··· 1808 1612 }; 1809 1613 1810 1614 &cm_core { 1811 - coreaon_cm: coreaon-cm@600 { 1615 + coreaon_cm: clock@600 { 1812 1616 compatible = "ti,omap4-cm"; 1617 + clock-output-names = "coreaon_cm"; 1813 1618 reg = <0x600 0x100>; 1814 1619 #address-cells = <1>; 1815 1620 #size-cells = <1>; 1816 1621 ranges = <0 0x600 0x100>; 1817 1622 1818 - coreaon_clkctrl: coreaon-clkctrl@20 { 1623 + coreaon_clkctrl: clock@20 { 1819 1624 compatible = "ti,clkctrl"; 1625 + clock-output-names = "coreaon_clkctrl"; 1820 1626 reg = <0x20 0x1c>; 1821 1627 #clock-cells = <2>; 1822 1628 }; 1823 1629 }; 1824 1630 1825 - l3main1_cm: l3main1-cm@700 { 1631 + l3main1_cm: clock@700 { 1826 1632 compatible = "ti,omap4-cm"; 1633 + clock-output-names = "l3main1_cm"; 1827 1634 reg = <0x700 0x100>; 1828 1635 #address-cells = <1>; 1829 1636 #size-cells = <1>; 1830 1637 ranges = <0 0x700 0x100>; 1831 1638 1832 - l3main1_clkctrl: l3main1-clkctrl@20 { 1639 + l3main1_clkctrl: clock@20 { 1833 1640 compatible = "ti,clkctrl"; 1641 + clock-output-names = "l3main1_clkctrl"; 1834 1642 reg = <0x20 0x74>; 1835 1643 #clock-cells = <2>; 1836 1644 }; 1837 1645 1838 1646 }; 1839 1647 1840 - ipu2_cm: ipu2-cm@900 { 1648 + ipu2_cm: clock@900 { 1841 1649 compatible = "ti,omap4-cm"; 1650 + clock-output-names = "ipu2_cm"; 1842 1651 reg = <0x900 0x100>; 1843 1652 #address-cells = <1>; 1844 1653 #size-cells = <1>; 1845 1654 ranges = <0 0x900 0x100>; 1846 1655 1847 - ipu2_clkctrl: ipu2-clkctrl@20 { 1656 + ipu2_clkctrl: clock@20 { 1848 1657 compatible = "ti,clkctrl"; 1658 + clock-output-names = "ipu2_clkctrl"; 1849 1659 reg = <0x20 0x4>; 1850 1660 #clock-cells = <2>; 1851 1661 }; 1852 1662 1853 1663 }; 1854 1664 1855 - dma_cm: dma-cm@a00 { 1665 + dma_cm: clock@a00 { 1856 1666 compatible = "ti,omap4-cm"; 1667 + clock-output-names = "dma_cm"; 1857 1668 reg = <0xa00 0x100>; 1858 1669 #address-cells = <1>; 1859 1670 #size-cells = <1>; 1860 1671 ranges = <0 0xa00 0x100>; 1861 1672 1862 - dma_clkctrl: dma-clkctrl@20 { 1673 + dma_clkctrl: clock@20 { 1863 1674 compatible = "ti,clkctrl"; 1675 + clock-output-names = "dma_clkctrl"; 1864 1676 reg = <0x20 0x4>; 1865 1677 #clock-cells = <2>; 1866 1678 }; 1867 1679 }; 1868 1680 1869 - emif_cm: emif-cm@b00 { 1681 + emif_cm: clock@b00 { 1870 1682 compatible = "ti,omap4-cm"; 1683 + clock-output-names = "emif_cm"; 1871 1684 reg = <0xb00 0x100>; 1872 1685 #address-cells = <1>; 1873 1686 #size-cells = <1>; 1874 1687 ranges = <0 0xb00 0x100>; 1875 1688 1876 - emif_clkctrl: emif-clkctrl@20 { 1689 + emif_clkctrl: clock@20 { 1877 1690 compatible = "ti,clkctrl"; 1691 + clock-output-names = "emif_clkctrl"; 1878 1692 reg = <0x20 0x4>; 1879 1693 #clock-cells = <2>; 1880 1694 }; 1881 1695 }; 1882 1696 1883 - atl_cm: atl-cm@c00 { 1697 + atl_cm: clock@c00 { 1884 1698 compatible = "ti,omap4-cm"; 1699 + clock-output-names = "atl_cm"; 1885 1700 reg = <0xc00 0x100>; 1886 1701 #address-cells = <1>; 1887 1702 #size-cells = <1>; 1888 1703 ranges = <0 0xc00 0x100>; 1889 1704 1890 - atl_clkctrl: atl-clkctrl@0 { 1705 + atl_clkctrl: clock@0 { 1891 1706 compatible = "ti,clkctrl"; 1707 + clock-output-names = "atl_clkctrl"; 1892 1708 reg = <0x0 0x4>; 1893 1709 #clock-cells = <2>; 1894 1710 }; 1895 1711 }; 1896 1712 1897 - l4cfg_cm: l4cfg-cm@d00 { 1713 + l4cfg_cm: clock@d00 { 1898 1714 compatible = "ti,omap4-cm"; 1715 + clock-output-names = "l4cfg_cm"; 1899 1716 reg = <0xd00 0x100>; 1900 1717 #address-cells = <1>; 1901 1718 #size-cells = <1>; 1902 1719 ranges = <0 0xd00 0x100>; 1903 1720 1904 - l4cfg_clkctrl: l4cfg-clkctrl@20 { 1721 + l4cfg_clkctrl: clock@20 { 1905 1722 compatible = "ti,clkctrl"; 1723 + clock-output-names = "l4cfg_clkctrl"; 1906 1724 reg = <0x20 0x84>; 1907 1725 #clock-cells = <2>; 1908 1726 }; 1909 1727 }; 1910 1728 1911 - l3instr_cm: l3instr-cm@e00 { 1729 + l3instr_cm: clock@e00 { 1912 1730 compatible = "ti,omap4-cm"; 1731 + clock-output-names = "l3instr_cm"; 1913 1732 reg = <0xe00 0x100>; 1914 1733 #address-cells = <1>; 1915 1734 #size-cells = <1>; 1916 1735 ranges = <0 0xe00 0x100>; 1917 1736 1918 - l3instr_clkctrl: l3instr-clkctrl@20 { 1737 + l3instr_clkctrl: clock@20 { 1919 1738 compatible = "ti,clkctrl"; 1739 + clock-output-names = "l3instr_clkctrl"; 1920 1740 reg = <0x20 0xc>; 1921 1741 #clock-cells = <2>; 1922 1742 }; 1923 1743 }; 1924 1744 1925 - iva_cm: iva-cm@f00 { 1745 + iva_cm: clock@f00 { 1926 1746 compatible = "ti,omap4-cm"; 1747 + clock-output-names = "iva_cm"; 1927 1748 reg = <0xf00 0x100>; 1928 1749 #address-cells = <1>; 1929 1750 #size-cells = <1>; 1930 1751 ranges = <0 0xf00 0x100>; 1931 1752 1932 - iva_clkctrl: iva-clkctrl@20 { 1753 + iva_clkctrl: clock@20 { 1933 1754 compatible = "ti,clkctrl"; 1755 + clock-output-names = "iva_clkctrl"; 1934 1756 reg = <0x20 0xc>; 1935 1757 #clock-cells = <2>; 1936 1758 }; 1937 1759 }; 1938 1760 1939 - cam_cm: cam-cm@1000 { 1761 + cam_cm: clock@1000 { 1940 1762 compatible = "ti,omap4-cm"; 1763 + clock-output-names = "cam_cm"; 1941 1764 reg = <0x1000 0x100>; 1942 1765 #address-cells = <1>; 1943 1766 #size-cells = <1>; 1944 1767 ranges = <0 0x1000 0x100>; 1945 1768 1946 - cam_clkctrl: cam-clkctrl@20 { 1769 + cam_clkctrl: clock@20 { 1947 1770 compatible = "ti,clkctrl"; 1771 + clock-output-names = "cam_clkctrl"; 1948 1772 reg = <0x20 0x2c>; 1949 1773 #clock-cells = <2>; 1950 1774 }; 1951 1775 }; 1952 1776 1953 - dss_cm: dss-cm@1100 { 1777 + dss_cm: clock@1100 { 1954 1778 compatible = "ti,omap4-cm"; 1779 + clock-output-names = "dss_cm"; 1955 1780 reg = <0x1100 0x100>; 1956 1781 #address-cells = <1>; 1957 1782 #size-cells = <1>; 1958 1783 ranges = <0 0x1100 0x100>; 1959 1784 1960 - dss_clkctrl: dss-clkctrl@20 { 1785 + dss_clkctrl: clock@20 { 1961 1786 compatible = "ti,clkctrl"; 1787 + clock-output-names = "dss_clkctrl"; 1962 1788 reg = <0x20 0x14>; 1963 1789 #clock-cells = <2>; 1964 1790 }; 1965 1791 }; 1966 1792 1967 - gpu_cm: gpu-cm@1200 { 1793 + gpu_cm: clock@1200 { 1968 1794 compatible = "ti,omap4-cm"; 1795 + clock-output-names = "gpu_cm"; 1969 1796 reg = <0x1200 0x100>; 1970 1797 #address-cells = <1>; 1971 1798 #size-cells = <1>; 1972 1799 ranges = <0 0x1200 0x100>; 1973 1800 1974 - gpu_clkctrl: gpu-clkctrl@20 { 1801 + gpu_clkctrl: clock@20 { 1975 1802 compatible = "ti,clkctrl"; 1803 + clock-output-names = "gpu_clkctrl"; 1976 1804 reg = <0x20 0x4>; 1977 1805 #clock-cells = <2>; 1978 1806 }; 1979 1807 }; 1980 1808 1981 - l3init_cm: l3init-cm@1300 { 1809 + l3init_cm: clock@1300 { 1982 1810 compatible = "ti,omap4-cm"; 1811 + clock-output-names = "l3init_cm"; 1983 1812 reg = <0x1300 0x100>; 1984 1813 #address-cells = <1>; 1985 1814 #size-cells = <1>; 1986 1815 ranges = <0 0x1300 0x100>; 1987 1816 1988 - l3init_clkctrl: l3init-clkctrl@20 { 1817 + l3init_clkctrl: clock@20 { 1989 1818 compatible = "ti,clkctrl"; 1819 + clock-output-names = "l3init_clkctrl"; 1990 1820 reg = <0x20 0x6c>, <0xe0 0x14>; 1991 1821 #clock-cells = <2>; 1992 1822 }; 1993 1823 1994 - pcie_clkctrl: pcie-clkctrl@b0 { 1824 + pcie_clkctrl: clock@b0 { 1995 1825 compatible = "ti,clkctrl"; 1826 + clock-output-names = "pcie_clkctrl"; 1996 1827 reg = <0xb0 0xc>; 1997 1828 #clock-cells = <2>; 1998 1829 }; 1999 1830 2000 - gmac_clkctrl: gmac-clkctrl@d0 { 1831 + gmac_clkctrl: clock@d0 { 2001 1832 compatible = "ti,clkctrl"; 1833 + clock-output-names = "gmac_clkctrl"; 2002 1834 reg = <0xd0 0x4>; 2003 1835 #clock-cells = <2>; 2004 1836 }; 2005 1837 2006 1838 }; 2007 1839 2008 - l4per_cm: l4per-cm@1700 { 1840 + l4per_cm: clock@1700 { 2009 1841 compatible = "ti,omap4-cm"; 1842 + clock-output-names = "l4per_cm"; 2010 1843 reg = <0x1700 0x300>; 2011 1844 #address-cells = <1>; 2012 1845 #size-cells = <1>; 2013 1846 ranges = <0 0x1700 0x300>; 2014 1847 2015 - l4per_clkctrl: l4per-clkctrl@28 { 1848 + l4per_clkctrl: clock@28 { 2016 1849 compatible = "ti,clkctrl"; 1850 + clock-output-names = "l4per_clkctrl"; 2017 1851 reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; 2018 1852 #clock-cells = <2>; 2019 1853 ··· 2051 1825 assigned-clock-parents = <&abe_24m_fclk>; 2052 1826 }; 2053 1827 2054 - l4sec_clkctrl: l4sec-clkctrl@1a0 { 1828 + l4sec_clkctrl: clock@1a0 { 2055 1829 compatible = "ti,clkctrl"; 1830 + clock-output-names = "l4sec_clkctrl"; 2056 1831 reg = <0x1a0 0x2c>; 2057 1832 #clock-cells = <2>; 2058 1833 }; 2059 1834 2060 - l4per2_clkctrl: l4per2-clkctrl@c { 1835 + l4per2_clkctrl: clock@c { 2061 1836 compatible = "ti,clkctrl"; 1837 + clock-output-names = "l4per2_clkctrl"; 2062 1838 reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; 2063 1839 #clock-cells = <2>; 2064 1840 }; 2065 1841 2066 - l4per3_clkctrl: l4per3-clkctrl@14 { 1842 + l4per3_clkctrl: clock@14 { 2067 1843 compatible = "ti,clkctrl"; 1844 + clock-output-names = "l4per3_clkctrl"; 2068 1845 reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; 2069 1846 #clock-cells = <2>; 2070 1847 }; ··· 2076 1847 }; 2077 1848 2078 1849 &prm { 2079 - wkupaon_cm: wkupaon-cm@1800 { 1850 + wkupaon_cm: clock@1800 { 2080 1851 compatible = "ti,omap4-cm"; 1852 + clock-output-names = "wkupaon_cm"; 2081 1853 reg = <0x1800 0x100>; 2082 1854 #address-cells = <1>; 2083 1855 #size-cells = <1>; 2084 1856 ranges = <0 0x1800 0x100>; 2085 1857 2086 - wkupaon_clkctrl: wkupaon-clkctrl@20 { 1858 + wkupaon_clkctrl: clock@20 { 2087 1859 compatible = "ti,clkctrl"; 1860 + clock-output-names = "wkupaon_clkctrl"; 2088 1861 reg = <0x20 0x6c>; 2089 1862 #clock-cells = <2>; 2090 1863 };

+5 -5

arch/arm/boot/dts/logicpd-som-lv.dtsi

··· 27 27 28 28 /* HS USB Host PHY on PORT 1 */ 29 29 hsusb2_phy: hsusb2_phy { 30 + pinctrl-names = "default"; 31 + pinctrl-0 = <&hsusb2_reset_pin>; 30 32 compatible = "usb-nop-xceiv"; 31 33 reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ 32 34 #phy-cells = <0>; ··· 146 144 }; 147 145 148 146 &usbhshost { 147 + pinctrl-names = "default"; 148 + pinctrl-0 = <&hsusb2_pins>; 149 149 port2-mode = "ehci-phy"; 150 150 }; 151 151 ··· 155 151 phys = <0 &hsusb2_phy>; 156 152 }; 157 153 158 - 159 154 &omap3_pmx_core { 160 - pinctrl-names = "default"; 161 - pinctrl-0 = <&hsusb2_pins>; 162 155 163 156 mmc3_pins: pinmux_mm3_pins { 164 157 pinctrl-single,pins = < ··· 251 250 }; 252 251 253 252 &omap3_pmx_wkup { 254 - pinctrl-names = "default"; 255 - pinctrl-0 = <&hsusb2_reset_pin>; 253 + 256 254 hsusb2_reset_pin: pinmux_hsusb1_reset_pin { 257 255 pinctrl-single,pins = < 258 256 OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */

+1 -1

arch/arm/boot/dts/omap3-beagle-xm.dts

··· 370 370 #address-cells = <1>; 371 371 #size-cells = <0>; 372 372 373 - ethernet: usbether@1 { 373 + ethernet: ethernet@1 { 374 374 compatible = "usb424,ec00"; 375 375 reg = <1>; 376 376 };

+1 -1

arch/arm/boot/dts/omap4-panda-common.dtsi

··· 558 558 #address-cells = <1>; 559 559 #size-cells = <0>; 560 560 561 - ethernet: usbether@1 { 561 + ethernet: ethernet@1 { 562 562 compatible = "usb424,ec00"; 563 563 reg = <1>; 564 564 };

+1

arch/arm/boot/dts/omap443x-clocks.dtsi

··· 8 8 bandgap_fclk: bandgap_fclk@1888 { 9 9 #clock-cells = <0>; 10 10 compatible = "ti,gate-clock"; 11 + clock-output-names = "bandgap_fclk"; 11 12 clocks = <&sys_32k_ck>; 12 13 ti,bit-shift = <8>; 13 14 reg = <0x1888>;

+2

arch/arm/boot/dts/omap446x-clocks.dtsi

··· 8 8 div_ts_ck: div_ts_ck@1888 { 9 9 #clock-cells = <0>; 10 10 compatible = "ti,divider-clock"; 11 + clock-output-names = "div_ts_ck"; 11 12 clocks = <&l4_wkup_clk_mux_ck>; 12 13 ti,bit-shift = <24>; 13 14 reg = <0x1888>; ··· 18 17 bandgap_ts_fclk: bandgap_ts_fclk@1888 { 19 18 #clock-cells = <0>; 20 19 compatible = "ti,gate-clock"; 20 + clock-output-names = "bandgap_ts_fclk"; 21 21 clocks = <&div_ts_ck>; 22 22 ti,bit-shift = <8>; 23 23 reg = <0x1888>;

+170 -3

arch/arm/boot/dts/omap44xx-clocks.dtsi

··· 8 8 extalt_clkin_ck: extalt_clkin_ck { 9 9 #clock-cells = <0>; 10 10 compatible = "fixed-clock"; 11 + clock-output-names = "extalt_clkin_ck"; 11 12 clock-frequency = <59000000>; 12 13 }; 13 14 14 15 pad_clks_src_ck: pad_clks_src_ck { 15 16 #clock-cells = <0>; 16 17 compatible = "fixed-clock"; 18 + clock-output-names = "pad_clks_src_ck"; 17 19 clock-frequency = <12000000>; 18 20 }; 19 21 20 22 pad_clks_ck: pad_clks_ck@108 { 21 23 #clock-cells = <0>; 22 24 compatible = "ti,gate-clock"; 25 + clock-output-names = "pad_clks_ck"; 23 26 clocks = <&pad_clks_src_ck>; 24 27 ti,bit-shift = <8>; 25 28 reg = <0x0108>; ··· 31 28 pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { 32 29 #clock-cells = <0>; 33 30 compatible = "fixed-clock"; 31 + clock-output-names = "pad_slimbus_core_clks_ck"; 34 32 clock-frequency = <12000000>; 35 33 }; 36 34 37 35 secure_32k_clk_src_ck: secure_32k_clk_src_ck { 38 36 #clock-cells = <0>; 39 37 compatible = "fixed-clock"; 38 + clock-output-names = "secure_32k_clk_src_ck"; 40 39 clock-frequency = <32768>; 41 40 }; 42 41 43 42 slimbus_src_clk: slimbus_src_clk { 44 43 #clock-cells = <0>; 45 44 compatible = "fixed-clock"; 45 + clock-output-names = "slimbus_src_clk"; 46 46 clock-frequency = <12000000>; 47 47 }; 48 48 49 49 slimbus_clk: slimbus_clk@108 { 50 50 #clock-cells = <0>; 51 51 compatible = "ti,gate-clock"; 52 + clock-output-names = "slimbus_clk"; 52 53 clocks = <&slimbus_src_clk>; 53 54 ti,bit-shift = <10>; 54 55 reg = <0x0108>; ··· 61 54 sys_32k_ck: sys_32k_ck { 62 55 #clock-cells = <0>; 63 56 compatible = "fixed-clock"; 57 + clock-output-names = "sys_32k_ck"; 64 58 clock-frequency = <32768>; 65 59 }; 66 60 67 61 virt_12000000_ck: virt_12000000_ck { 68 62 #clock-cells = <0>; 69 63 compatible = "fixed-clock"; 64 + clock-output-names = "virt_12000000_ck"; 70 65 clock-frequency = <12000000>; 71 66 }; 72 67 73 68 virt_13000000_ck: virt_13000000_ck { 74 69 #clock-cells = <0>; 75 70 compatible = "fixed-clock"; 71 + clock-output-names = "virt_13000000_ck"; 76 72 clock-frequency = <13000000>; 77 73 }; 78 74 79 75 virt_16800000_ck: virt_16800000_ck { 80 76 #clock-cells = <0>; 81 77 compatible = "fixed-clock"; 78 + clock-output-names = "virt_16800000_ck"; 82 79 clock-frequency = <16800000>; 83 80 }; 84 81 85 82 virt_19200000_ck: virt_19200000_ck { 86 83 #clock-cells = <0>; 87 84 compatible = "fixed-clock"; 85 + clock-output-names = "virt_19200000_ck"; 88 86 clock-frequency = <19200000>; 89 87 }; 90 88 91 89 virt_26000000_ck: virt_26000000_ck { 92 90 #clock-cells = <0>; 93 91 compatible = "fixed-clock"; 92 + clock-output-names = "virt_26000000_ck"; 94 93 clock-frequency = <26000000>; 95 94 }; 96 95 97 96 virt_27000000_ck: virt_27000000_ck { 98 97 #clock-cells = <0>; 99 98 compatible = "fixed-clock"; 99 + clock-output-names = "virt_27000000_ck"; 100 100 clock-frequency = <27000000>; 101 101 }; 102 102 103 103 virt_38400000_ck: virt_38400000_ck { 104 104 #clock-cells = <0>; 105 105 compatible = "fixed-clock"; 106 + clock-output-names = "virt_38400000_ck"; 106 107 clock-frequency = <38400000>; 107 108 }; 108 109 109 110 tie_low_clock_ck: tie_low_clock_ck { 110 111 #clock-cells = <0>; 111 112 compatible = "fixed-clock"; 113 + clock-output-names = "tie_low_clock_ck"; 112 114 clock-frequency = <0>; 113 115 }; 114 116 115 117 utmi_phy_clkout_ck: utmi_phy_clkout_ck { 116 118 #clock-cells = <0>; 117 119 compatible = "fixed-clock"; 120 + clock-output-names = "utmi_phy_clkout_ck"; 118 121 clock-frequency = <60000000>; 119 122 }; 120 123 121 124 xclk60mhsp1_ck: xclk60mhsp1_ck { 122 125 #clock-cells = <0>; 123 126 compatible = "fixed-clock"; 127 + clock-output-names = "xclk60mhsp1_ck"; 124 128 clock-frequency = <60000000>; 125 129 }; 126 130 127 131 xclk60mhsp2_ck: xclk60mhsp2_ck { 128 132 #clock-cells = <0>; 129 133 compatible = "fixed-clock"; 134 + clock-output-names = "xclk60mhsp2_ck"; 130 135 clock-frequency = <60000000>; 131 136 }; 132 137 133 138 xclk60motg_ck: xclk60motg_ck { 134 139 #clock-cells = <0>; 135 140 compatible = "fixed-clock"; 141 + clock-output-names = "xclk60motg_ck"; 136 142 clock-frequency = <60000000>; 137 143 }; 138 144 139 145 dpll_abe_ck: dpll_abe_ck@1e0 { 140 146 #clock-cells = <0>; 141 147 compatible = "ti,omap4-dpll-m4xen-clock"; 148 + clock-output-names = "dpll_abe_ck"; 142 149 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; 143 150 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 144 151 }; ··· 160 139 dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { 161 140 #clock-cells = <0>; 162 141 compatible = "ti,omap4-dpll-x2-clock"; 142 + clock-output-names = "dpll_abe_x2_ck"; 163 143 clocks = <&dpll_abe_ck>; 164 144 reg = <0x01f0>; 165 145 }; ··· 168 146 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { 169 147 #clock-cells = <0>; 170 148 compatible = "ti,divider-clock"; 149 + clock-output-names = "dpll_abe_m2x2_ck"; 171 150 clocks = <&dpll_abe_x2_ck>; 172 151 ti,max-div = <31>; 173 152 ti,autoidle-shift = <8>; ··· 180 157 abe_24m_fclk: abe_24m_fclk { 181 158 #clock-cells = <0>; 182 159 compatible = "fixed-factor-clock"; 160 + clock-output-names = "abe_24m_fclk"; 183 161 clocks = <&dpll_abe_m2x2_ck>; 184 162 clock-mult = <1>; 185 163 clock-div = <8>; ··· 189 165 abe_clk: abe_clk@108 { 190 166 #clock-cells = <0>; 191 167 compatible = "ti,divider-clock"; 168 + clock-output-names = "abe_clk"; 192 169 clocks = <&dpll_abe_m2x2_ck>; 193 170 ti,max-div = <4>; 194 171 reg = <0x0108>; ··· 200 175 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { 201 176 #clock-cells = <0>; 202 177 compatible = "ti,divider-clock"; 178 + clock-output-names = "dpll_abe_m3x2_ck"; 203 179 clocks = <&dpll_abe_x2_ck>; 204 180 ti,max-div = <31>; 205 181 ti,autoidle-shift = <8>; ··· 212 186 core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { 213 187 #clock-cells = <0>; 214 188 compatible = "ti,mux-clock"; 189 + clock-output-names = "core_hsd_byp_clk_mux_ck"; 215 190 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; 216 191 ti,bit-shift = <23>; 217 192 reg = <0x012c>; ··· 221 194 dpll_core_ck: dpll_core_ck@120 { 222 195 #clock-cells = <0>; 223 196 compatible = "ti,omap4-dpll-core-clock"; 197 + clock-output-names = "dpll_core_ck"; 224 198 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; 225 199 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 226 200 }; ··· 229 201 dpll_core_x2_ck: dpll_core_x2_ck { 230 202 #clock-cells = <0>; 231 203 compatible = "ti,omap4-dpll-x2-clock"; 204 + clock-output-names = "dpll_core_x2_ck"; 232 205 clocks = <&dpll_core_ck>; 233 206 }; 234 207 235 208 dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { 236 209 #clock-cells = <0>; 237 210 compatible = "ti,divider-clock"; 211 + clock-output-names = "dpll_core_m6x2_ck"; 238 212 clocks = <&dpll_core_x2_ck>; 239 213 ti,max-div = <31>; 240 214 ti,autoidle-shift = <8>; ··· 248 218 dpll_core_m2_ck: dpll_core_m2_ck@130 { 249 219 #clock-cells = <0>; 250 220 compatible = "ti,divider-clock"; 221 + clock-output-names = "dpll_core_m2_ck"; 251 222 clocks = <&dpll_core_ck>; 252 223 ti,max-div = <31>; 253 224 ti,autoidle-shift = <8>; ··· 260 229 ddrphy_ck: ddrphy_ck { 261 230 #clock-cells = <0>; 262 231 compatible = "fixed-factor-clock"; 232 + clock-output-names = "ddrphy_ck"; 263 233 clocks = <&dpll_core_m2_ck>; 264 234 clock-mult = <1>; 265 235 clock-div = <2>; ··· 269 237 dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { 270 238 #clock-cells = <0>; 271 239 compatible = "ti,divider-clock"; 240 + clock-output-names = "dpll_core_m5x2_ck"; 272 241 clocks = <&dpll_core_x2_ck>; 273 242 ti,max-div = <31>; 274 243 ti,autoidle-shift = <8>; ··· 281 248 div_core_ck: div_core_ck@100 { 282 249 #clock-cells = <0>; 283 250 compatible = "ti,divider-clock"; 251 + clock-output-names = "div_core_ck"; 284 252 clocks = <&dpll_core_m5x2_ck>; 285 253 reg = <0x0100>; 286 254 ti,max-div = <2>; ··· 290 256 div_iva_hs_clk: div_iva_hs_clk@1dc { 291 257 #clock-cells = <0>; 292 258 compatible = "ti,divider-clock"; 259 + clock-output-names = "div_iva_hs_clk"; 293 260 clocks = <&dpll_core_m5x2_ck>; 294 261 ti,max-div = <4>; 295 262 reg = <0x01dc>; ··· 300 265 div_mpu_hs_clk: div_mpu_hs_clk@19c { 301 266 #clock-cells = <0>; 302 267 compatible = "ti,divider-clock"; 268 + clock-output-names = "div_mpu_hs_clk"; 303 269 clocks = <&dpll_core_m5x2_ck>; 304 270 ti,max-div = <4>; 305 271 reg = <0x019c>; ··· 310 274 dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { 311 275 #clock-cells = <0>; 312 276 compatible = "ti,divider-clock"; 277 + clock-output-names = "dpll_core_m4x2_ck"; 313 278 clocks = <&dpll_core_x2_ck>; 314 279 ti,max-div = <31>; 315 280 ti,autoidle-shift = <8>; ··· 322 285 dll_clk_div_ck: dll_clk_div_ck { 323 286 #clock-cells = <0>; 324 287 compatible = "fixed-factor-clock"; 288 + clock-output-names = "dll_clk_div_ck"; 325 289 clocks = <&dpll_core_m4x2_ck>; 326 290 clock-mult = <1>; 327 291 clock-div = <2>; ··· 331 293 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { 332 294 #clock-cells = <0>; 333 295 compatible = "ti,divider-clock"; 296 + clock-output-names = "dpll_abe_m2_ck"; 334 297 clocks = <&dpll_abe_ck>; 335 298 ti,max-div = <31>; 336 299 reg = <0x01f0>; ··· 341 302 dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { 342 303 #clock-cells = <0>; 343 304 compatible = "ti,composite-no-wait-gate-clock"; 305 + clock-output-names = "dpll_core_m3x2_gate_ck"; 344 306 clocks = <&dpll_core_x2_ck>; 345 307 ti,bit-shift = <8>; 346 308 reg = <0x0134>; ··· 350 310 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { 351 311 #clock-cells = <0>; 352 312 compatible = "ti,composite-divider-clock"; 313 + clock-output-names = "dpll_core_m3x2_div_ck"; 353 314 clocks = <&dpll_core_x2_ck>; 354 315 ti,max-div = <31>; 355 316 reg = <0x0134>; ··· 360 319 dpll_core_m3x2_ck: dpll_core_m3x2_ck { 361 320 #clock-cells = <0>; 362 321 compatible = "ti,composite-clock"; 322 + clock-output-names = "dpll_core_m3x2_ck"; 363 323 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; 364 324 }; 365 325 366 326 dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { 367 327 #clock-cells = <0>; 368 328 compatible = "ti,divider-clock"; 329 + clock-output-names = "dpll_core_m7x2_ck"; 369 330 clocks = <&dpll_core_x2_ck>; 370 331 ti,max-div = <31>; 371 332 ti,autoidle-shift = <8>; ··· 379 336 iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { 380 337 #clock-cells = <0>; 381 338 compatible = "ti,mux-clock"; 339 + clock-output-names = "iva_hsd_byp_clk_mux_ck"; 382 340 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; 383 341 ti,bit-shift = <23>; 384 342 reg = <0x01ac>; ··· 388 344 dpll_iva_ck: dpll_iva_ck@1a0 { 389 345 #clock-cells = <0>; 390 346 compatible = "ti,omap4-dpll-clock"; 347 + clock-output-names = "dpll_iva_ck"; 391 348 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; 392 349 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 393 350 assigned-clocks = <&dpll_iva_ck>; ··· 398 353 dpll_iva_x2_ck: dpll_iva_x2_ck { 399 354 #clock-cells = <0>; 400 355 compatible = "ti,omap4-dpll-x2-clock"; 356 + clock-output-names = "dpll_iva_x2_ck"; 401 357 clocks = <&dpll_iva_ck>; 402 358 }; 403 359 404 360 dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { 405 361 #clock-cells = <0>; 406 362 compatible = "ti,divider-clock"; 363 + clock-output-names = "dpll_iva_m4x2_ck"; 407 364 clocks = <&dpll_iva_x2_ck>; 408 365 ti,max-div = <31>; 409 366 ti,autoidle-shift = <8>; ··· 419 372 dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { 420 373 #clock-cells = <0>; 421 374 compatible = "ti,divider-clock"; 375 + clock-output-names = "dpll_iva_m5x2_ck"; 422 376 clocks = <&dpll_iva_x2_ck>; 423 377 ti,max-div = <31>; 424 378 ti,autoidle-shift = <8>; ··· 433 385 dpll_mpu_ck: dpll_mpu_ck@160 { 434 386 #clock-cells = <0>; 435 387 compatible = "ti,omap4-dpll-clock"; 388 + clock-output-names = "dpll_mpu_ck"; 436 389 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; 437 390 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 438 391 }; ··· 441 392 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { 442 393 #clock-cells = <0>; 443 394 compatible = "ti,divider-clock"; 395 + clock-output-names = "dpll_mpu_m2_ck"; 444 396 clocks = <&dpll_mpu_ck>; 445 397 ti,max-div = <31>; 446 398 ti,autoidle-shift = <8>; ··· 453 403 per_hs_clk_div_ck: per_hs_clk_div_ck { 454 404 #clock-cells = <0>; 455 405 compatible = "fixed-factor-clock"; 406 + clock-output-names = "per_hs_clk_div_ck"; 456 407 clocks = <&dpll_abe_m3x2_ck>; 457 408 clock-mult = <1>; 458 409 clock-div = <2>; ··· 462 411 usb_hs_clk_div_ck: usb_hs_clk_div_ck { 463 412 #clock-cells = <0>; 464 413 compatible = "fixed-factor-clock"; 414 + clock-output-names = "usb_hs_clk_div_ck"; 465 415 clocks = <&dpll_abe_m3x2_ck>; 466 416 clock-mult = <1>; 467 417 clock-div = <3>; ··· 471 419 l3_div_ck: l3_div_ck@100 { 472 420 #clock-cells = <0>; 473 421 compatible = "ti,divider-clock"; 422 + clock-output-names = "l3_div_ck"; 474 423 clocks = <&div_core_ck>; 475 424 ti,bit-shift = <4>; 476 425 ti,max-div = <2>; ··· 481 428 l4_div_ck: l4_div_ck@100 { 482 429 #clock-cells = <0>; 483 430 compatible = "ti,divider-clock"; 431 + clock-output-names = "l4_div_ck"; 484 432 clocks = <&l3_div_ck>; 485 433 ti,bit-shift = <8>; 486 434 ti,max-div = <2>; ··· 491 437 lp_clk_div_ck: lp_clk_div_ck { 492 438 #clock-cells = <0>; 493 439 compatible = "fixed-factor-clock"; 440 + clock-output-names = "lp_clk_div_ck"; 494 441 clocks = <&dpll_abe_m2x2_ck>; 495 442 clock-mult = <1>; 496 443 clock-div = <16>; ··· 500 445 mpu_periphclk: mpu_periphclk { 501 446 #clock-cells = <0>; 502 447 compatible = "fixed-factor-clock"; 448 + clock-output-names = "mpu_periphclk"; 503 449 clocks = <&dpll_mpu_ck>; 504 450 clock-mult = <1>; 505 451 clock-div = <2>; ··· 509 453 ocp_abe_iclk: ocp_abe_iclk@528 { 510 454 #clock-cells = <0>; 511 455 compatible = "ti,divider-clock"; 456 + clock-output-names = "ocp_abe_iclk"; 512 457 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; 513 458 ti,bit-shift = <24>; 514 459 reg = <0x0528>; ··· 519 462 per_abe_24m_fclk: per_abe_24m_fclk { 520 463 #clock-cells = <0>; 521 464 compatible = "fixed-factor-clock"; 465 + clock-output-names = "per_abe_24m_fclk"; 522 466 clocks = <&dpll_abe_m2_ck>; 523 467 clock-mult = <1>; 524 468 clock-div = <4>; ··· 528 470 dummy_ck: dummy_ck { 529 471 #clock-cells = <0>; 530 472 compatible = "fixed-clock"; 473 + clock-output-names = "dummy_ck"; 531 474 clock-frequency = <0>; 532 475 }; 533 476 }; ··· 537 478 sys_clkin_ck: sys_clkin_ck@110 { 538 479 #clock-cells = <0>; 539 480 compatible = "ti,mux-clock"; 481 + clock-output-names = "sys_clkin_ck"; 540 482 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 541 483 reg = <0x0110>; 542 484 ti,index-starts-at-one; ··· 546 486 abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { 547 487 #clock-cells = <0>; 548 488 compatible = "ti,mux-clock"; 489 + clock-output-names = "abe_dpll_bypass_clk_mux_ck"; 549 490 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 550 491 ti,bit-shift = <24>; 551 492 reg = <0x0108>; ··· 555 494 abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { 556 495 #clock-cells = <0>; 557 496 compatible = "ti,mux-clock"; 497 + clock-output-names = "abe_dpll_refclk_mux_ck"; 558 498 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 559 499 reg = <0x010c>; 560 500 }; ··· 563 501 dbgclk_mux_ck: dbgclk_mux_ck { 564 502 #clock-cells = <0>; 565 503 compatible = "fixed-factor-clock"; 504 + clock-output-names = "dbgclk_mux_ck"; 566 505 clocks = <&sys_clkin_ck>; 567 506 clock-mult = <1>; 568 507 clock-div = <1>; ··· 572 509 l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { 573 510 #clock-cells = <0>; 574 511 compatible = "ti,mux-clock"; 512 + clock-output-names = "l4_wkup_clk_mux_ck"; 575 513 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; 576 514 reg = <0x0108>; 577 515 }; ··· 580 516 syc_clk_div_ck: syc_clk_div_ck@100 { 581 517 #clock-cells = <0>; 582 518 compatible = "ti,divider-clock"; 519 + clock-output-names = "syc_clk_div_ck"; 583 520 clocks = <&sys_clkin_ck>; 584 521 reg = <0x0100>; 585 522 ti,max-div = <2>; ··· 589 524 usim_ck: usim_ck@1858 { 590 525 #clock-cells = <0>; 591 526 compatible = "ti,divider-clock"; 527 + clock-output-names = "usim_ck"; 592 528 clocks = <&dpll_per_m4x2_ck>; 593 529 ti,bit-shift = <24>; 594 530 reg = <0x1858>; ··· 599 533 usim_fclk: usim_fclk@1858 { 600 534 #clock-cells = <0>; 601 535 compatible = "ti,gate-clock"; 536 + clock-output-names = "usim_fclk"; 602 537 clocks = <&usim_ck>; 603 538 ti,bit-shift = <8>; 604 539 reg = <0x1858>; ··· 608 541 trace_clk_div_ck: trace_clk_div_ck { 609 542 #clock-cells = <0>; 610 543 compatible = "ti,clkdm-gate-clock"; 544 + clock-output-names = "trace_clk_div_ck"; 611 545 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; 612 546 }; 613 547 }; ··· 616 548 &prm_clockdomains { 617 549 emu_sys_clkdm: emu_sys_clkdm { 618 550 compatible = "ti,clockdomain"; 551 + clock-output-names = "emu_sys_clkdm"; 619 552 clocks = <&trace_clk_div_ck>; 620 553 }; 621 554 }; ··· 625 556 per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { 626 557 #clock-cells = <0>; 627 558 compatible = "ti,mux-clock"; 559 + clock-output-names = "per_hsd_byp_clk_mux_ck"; 628 560 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; 629 561 ti,bit-shift = <23>; 630 562 reg = <0x014c>; ··· 634 564 dpll_per_ck: dpll_per_ck@140 { 635 565 #clock-cells = <0>; 636 566 compatible = "ti,omap4-dpll-clock"; 567 + clock-output-names = "dpll_per_ck"; 637 568 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; 638 569 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 639 570 }; ··· 642 571 dpll_per_m2_ck: dpll_per_m2_ck@150 { 643 572 #clock-cells = <0>; 644 573 compatible = "ti,divider-clock"; 574 + clock-output-names = "dpll_per_m2_ck"; 645 575 clocks = <&dpll_per_ck>; 646 576 ti,max-div = <31>; 647 577 reg = <0x0150>; ··· 652 580 dpll_per_x2_ck: dpll_per_x2_ck@150 { 653 581 #clock-cells = <0>; 654 582 compatible = "ti,omap4-dpll-x2-clock"; 583 + clock-output-names = "dpll_per_x2_ck"; 655 584 clocks = <&dpll_per_ck>; 656 585 reg = <0x0150>; 657 586 }; ··· 660 587 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { 661 588 #clock-cells = <0>; 662 589 compatible = "ti,divider-clock"; 590 + clock-output-names = "dpll_per_m2x2_ck"; 663 591 clocks = <&dpll_per_x2_ck>; 664 592 ti,max-div = <31>; 665 593 ti,autoidle-shift = <8>; ··· 672 598 dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { 673 599 #clock-cells = <0>; 674 600 compatible = "ti,composite-no-wait-gate-clock"; 601 + clock-output-names = "dpll_per_m3x2_gate_ck"; 675 602 clocks = <&dpll_per_x2_ck>; 676 603 ti,bit-shift = <8>; 677 604 reg = <0x0154>; ··· 681 606 dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { 682 607 #clock-cells = <0>; 683 608 compatible = "ti,composite-divider-clock"; 609 + clock-output-names = "dpll_per_m3x2_div_ck"; 684 610 clocks = <&dpll_per_x2_ck>; 685 611 ti,max-div = <31>; 686 612 reg = <0x0154>; ··· 691 615 dpll_per_m3x2_ck: dpll_per_m3x2_ck { 692 616 #clock-cells = <0>; 693 617 compatible = "ti,composite-clock"; 618 + clock-output-names = "dpll_per_m3x2_ck"; 694 619 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; 695 620 }; 696 621 697 622 dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { 698 623 #clock-cells = <0>; 699 624 compatible = "ti,divider-clock"; 625 + clock-output-names = "dpll_per_m4x2_ck"; 700 626 clocks = <&dpll_per_x2_ck>; 701 627 ti,max-div = <31>; 702 628 ti,autoidle-shift = <8>; ··· 710 632 dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { 711 633 #clock-cells = <0>; 712 634 compatible = "ti,divider-clock"; 635 + clock-output-names = "dpll_per_m5x2_ck"; 713 636 clocks = <&dpll_per_x2_ck>; 714 637 ti,max-div = <31>; 715 638 ti,autoidle-shift = <8>; ··· 722 643 dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { 723 644 #clock-cells = <0>; 724 645 compatible = "ti,divider-clock"; 646 + clock-output-names = "dpll_per_m6x2_ck"; 725 647 clocks = <&dpll_per_x2_ck>; 726 648 ti,max-div = <31>; 727 649 ti,autoidle-shift = <8>; ··· 734 654 dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { 735 655 #clock-cells = <0>; 736 656 compatible = "ti,divider-clock"; 657 + clock-output-names = "dpll_per_m7x2_ck"; 737 658 clocks = <&dpll_per_x2_ck>; 738 659 ti,max-div = <31>; 739 660 ti,autoidle-shift = <8>; ··· 746 665 dpll_usb_ck: dpll_usb_ck@180 { 747 666 #clock-cells = <0>; 748 667 compatible = "ti,omap4-dpll-j-type-clock"; 668 + clock-output-names = "dpll_usb_ck"; 749 669 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; 750 670 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 751 671 }; ··· 754 672 dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { 755 673 #clock-cells = <0>; 756 674 compatible = "ti,fixed-factor-clock"; 675 + clock-output-names = "dpll_usb_clkdcoldo_ck"; 757 676 clocks = <&dpll_usb_ck>; 758 677 ti,clock-div = <1>; 759 678 ti,autoidle-shift = <8>; ··· 766 683 dpll_usb_m2_ck: dpll_usb_m2_ck@190 { 767 684 #clock-cells = <0>; 768 685 compatible = "ti,divider-clock"; 686 + clock-output-names = "dpll_usb_m2_ck"; 769 687 clocks = <&dpll_usb_ck>; 770 688 ti,max-div = <127>; 771 689 ti,autoidle-shift = <8>; ··· 778 694 ducati_clk_mux_ck: ducati_clk_mux_ck@100 { 779 695 #clock-cells = <0>; 780 696 compatible = "ti,mux-clock"; 697 + clock-output-names = "ducati_clk_mux_ck"; 781 698 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; 782 699 reg = <0x0100>; 783 700 }; ··· 786 701 func_12m_fclk: func_12m_fclk { 787 702 #clock-cells = <0>; 788 703 compatible = "fixed-factor-clock"; 704 + clock-output-names = "func_12m_fclk"; 789 705 clocks = <&dpll_per_m2x2_ck>; 790 706 clock-mult = <1>; 791 707 clock-div = <16>; ··· 795 709 func_24m_clk: func_24m_clk { 796 710 #clock-cells = <0>; 797 711 compatible = "fixed-factor-clock"; 712 + clock-output-names = "func_24m_clk"; 798 713 clocks = <&dpll_per_m2_ck>; 799 714 clock-mult = <1>; 800 715 clock-div = <4>; ··· 804 717 func_24mc_fclk: func_24mc_fclk { 805 718 #clock-cells = <0>; 806 719 compatible = "fixed-factor-clock"; 720 + clock-output-names = "func_24mc_fclk"; 807 721 clocks = <&dpll_per_m2x2_ck>; 808 722 clock-mult = <1>; 809 723 clock-div = <8>; ··· 813 725 func_48m_fclk: func_48m_fclk@108 { 814 726 #clock-cells = <0>; 815 727 compatible = "ti,divider-clock"; 728 + clock-output-names = "func_48m_fclk"; 816 729 clocks = <&dpll_per_m2x2_ck>; 817 730 reg = <0x0108>; 818 731 ti,dividers = <4>, <8>; ··· 822 733 func_48mc_fclk: func_48mc_fclk { 823 734 #clock-cells = <0>; 824 735 compatible = "fixed-factor-clock"; 736 + clock-output-names = "func_48mc_fclk"; 825 737 clocks = <&dpll_per_m2x2_ck>; 826 738 clock-mult = <1>; 827 739 clock-div = <4>; ··· 831 741 func_64m_fclk: func_64m_fclk@108 { 832 742 #clock-cells = <0>; 833 743 compatible = "ti,divider-clock"; 744 + clock-output-names = "func_64m_fclk"; 834 745 clocks = <&dpll_per_m4x2_ck>; 835 746 reg = <0x0108>; 836 747 ti,dividers = <2>, <4>; ··· 840 749 func_96m_fclk: func_96m_fclk@108 { 841 750 #clock-cells = <0>; 842 751 compatible = "ti,divider-clock"; 752 + clock-output-names = "func_96m_fclk"; 843 753 clocks = <&dpll_per_m2x2_ck>; 844 754 reg = <0x0108>; 845 755 ti,dividers = <2>, <4>; ··· 849 757 init_60m_fclk: init_60m_fclk@104 { 850 758 #clock-cells = <0>; 851 759 compatible = "ti,divider-clock"; 760 + clock-output-names = "init_60m_fclk"; 852 761 clocks = <&dpll_usb_m2_ck>; 853 762 reg = <0x0104>; 854 763 ti,dividers = <1>, <8>; ··· 858 765 per_abe_nc_fclk: per_abe_nc_fclk@108 { 859 766 #clock-cells = <0>; 860 767 compatible = "ti,divider-clock"; 768 + clock-output-names = "per_abe_nc_fclk"; 861 769 clocks = <&dpll_abe_m2_ck>; 862 770 reg = <0x0108>; 863 771 ti,max-div = <2>; ··· 867 773 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { 868 774 #clock-cells = <0>; 869 775 compatible = "ti,gate-clock"; 776 + clock-output-names = "usb_phy_cm_clk32k"; 870 777 clocks = <&sys_32k_ck>; 871 778 ti,bit-shift = <8>; 872 779 reg = <0x0640>; ··· 877 782 &cm2_clockdomains { 878 783 l3_init_clkdm: l3_init_clkdm { 879 784 compatible = "ti,clockdomain"; 785 + clock-output-names = "l3_init_clkdm"; 880 786 clocks = <&dpll_usb_ck>; 881 787 }; 882 788 }; ··· 886 790 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { 887 791 #clock-cells = <0>; 888 792 compatible = "ti,composite-no-wait-gate-clock"; 793 + clock-output-names = "auxclk0_src_gate_ck"; 889 794 clocks = <&dpll_core_m3x2_ck>; 890 795 ti,bit-shift = <8>; 891 796 reg = <0x0310>; ··· 895 798 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { 896 799 #clock-cells = <0>; 897 800 compatible = "ti,composite-mux-clock"; 801 + clock-output-names = "auxclk0_src_mux_ck"; 898 802 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 899 803 ti,bit-shift = <1>; 900 804 reg = <0x0310>; ··· 904 806 auxclk0_src_ck: auxclk0_src_ck { 905 807 #clock-cells = <0>; 906 808 compatible = "ti,composite-clock"; 809 + clock-output-names = "auxclk0_src_ck"; 907 810 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; 908 811 }; 909 812 910 813 auxclk0_ck: auxclk0_ck@310 { 911 814 #clock-cells = <0>; 912 815 compatible = "ti,divider-clock"; 816 + clock-output-names = "auxclk0_ck"; 913 817 clocks = <&auxclk0_src_ck>; 914 818 ti,bit-shift = <16>; 915 819 ti,max-div = <16>; ··· 921 821 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { 922 822 #clock-cells = <0>; 923 823 compatible = "ti,composite-no-wait-gate-clock"; 824 + clock-output-names = "auxclk1_src_gate_ck"; 924 825 clocks = <&dpll_core_m3x2_ck>; 925 826 ti,bit-shift = <8>; 926 827 reg = <0x0314>; ··· 930 829 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { 931 830 #clock-cells = <0>; 932 831 compatible = "ti,composite-mux-clock"; 832 + clock-output-names = "auxclk1_src_mux_ck"; 933 833 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 934 834 ti,bit-shift = <1>; 935 835 reg = <0x0314>; ··· 939 837 auxclk1_src_ck: auxclk1_src_ck { 940 838 #clock-cells = <0>; 941 839 compatible = "ti,composite-clock"; 840 + clock-output-names = "auxclk1_src_ck"; 942 841 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; 943 842 }; 944 843 945 844 auxclk1_ck: auxclk1_ck@314 { 946 845 #clock-cells = <0>; 947 846 compatible = "ti,divider-clock"; 847 + clock-output-names = "auxclk1_ck"; 948 848 clocks = <&auxclk1_src_ck>; 949 849 ti,bit-shift = <16>; 950 850 ti,max-div = <16>; ··· 956 852 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { 957 853 #clock-cells = <0>; 958 854 compatible = "ti,composite-no-wait-gate-clock"; 855 + clock-output-names = "auxclk2_src_gate_ck"; 959 856 clocks = <&dpll_core_m3x2_ck>; 960 857 ti,bit-shift = <8>; 961 858 reg = <0x0318>; ··· 965 860 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { 966 861 #clock-cells = <0>; 967 862 compatible = "ti,composite-mux-clock"; 863 + clock-output-names = "auxclk2_src_mux_ck"; 968 864 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 969 865 ti,bit-shift = <1>; 970 866 reg = <0x0318>; ··· 974 868 auxclk2_src_ck: auxclk2_src_ck { 975 869 #clock-cells = <0>; 976 870 compatible = "ti,composite-clock"; 871 + clock-output-names = "auxclk2_src_ck"; 977 872 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; 978 873 }; 979 874 980 875 auxclk2_ck: auxclk2_ck@318 { 981 876 #clock-cells = <0>; 982 877 compatible = "ti,divider-clock"; 878 + clock-output-names = "auxclk2_ck"; 983 879 clocks = <&auxclk2_src_ck>; 984 880 ti,bit-shift = <16>; 985 881 ti,max-div = <16>; ··· 991 883 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { 992 884 #clock-cells = <0>; 993 885 compatible = "ti,composite-no-wait-gate-clock"; 886 + clock-output-names = "auxclk3_src_gate_ck"; 994 887 clocks = <&dpll_core_m3x2_ck>; 995 888 ti,bit-shift = <8>; 996 889 reg = <0x031c>; ··· 1000 891 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { 1001 892 #clock-cells = <0>; 1002 893 compatible = "ti,composite-mux-clock"; 894 + clock-output-names = "auxclk3_src_mux_ck"; 1003 895 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1004 896 ti,bit-shift = <1>; 1005 897 reg = <0x031c>; ··· 1009 899 auxclk3_src_ck: auxclk3_src_ck { 1010 900 #clock-cells = <0>; 1011 901 compatible = "ti,composite-clock"; 902 + clock-output-names = "auxclk3_src_ck"; 1012 903 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; 1013 904 }; 1014 905 1015 906 auxclk3_ck: auxclk3_ck@31c { 1016 907 #clock-cells = <0>; 1017 908 compatible = "ti,divider-clock"; 909 + clock-output-names = "auxclk3_ck"; 1018 910 clocks = <&auxclk3_src_ck>; 1019 911 ti,bit-shift = <16>; 1020 912 ti,max-div = <16>; ··· 1026 914 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { 1027 915 #clock-cells = <0>; 1028 916 compatible = "ti,composite-no-wait-gate-clock"; 917 + clock-output-names = "auxclk4_src_gate_ck"; 1029 918 clocks = <&dpll_core_m3x2_ck>; 1030 919 ti,bit-shift = <8>; 1031 920 reg = <0x0320>; ··· 1035 922 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { 1036 923 #clock-cells = <0>; 1037 924 compatible = "ti,composite-mux-clock"; 925 + clock-output-names = "auxclk4_src_mux_ck"; 1038 926 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1039 927 ti,bit-shift = <1>; 1040 928 reg = <0x0320>; ··· 1044 930 auxclk4_src_ck: auxclk4_src_ck { 1045 931 #clock-cells = <0>; 1046 932 compatible = "ti,composite-clock"; 933 + clock-output-names = "auxclk4_src_ck"; 1047 934 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; 1048 935 }; 1049 936 1050 937 auxclk4_ck: auxclk4_ck@320 { 1051 938 #clock-cells = <0>; 1052 939 compatible = "ti,divider-clock"; 940 + clock-output-names = "auxclk4_ck"; 1053 941 clocks = <&auxclk4_src_ck>; 1054 942 ti,bit-shift = <16>; 1055 943 ti,max-div = <16>; ··· 1061 945 auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { 1062 946 #clock-cells = <0>; 1063 947 compatible = "ti,composite-no-wait-gate-clock"; 948 + clock-output-names = "auxclk5_src_gate_ck"; 1064 949 clocks = <&dpll_core_m3x2_ck>; 1065 950 ti,bit-shift = <8>; 1066 951 reg = <0x0324>; ··· 1070 953 auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { 1071 954 #clock-cells = <0>; 1072 955 compatible = "ti,composite-mux-clock"; 956 + clock-output-names = "auxclk5_src_mux_ck"; 1073 957 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1074 958 ti,bit-shift = <1>; 1075 959 reg = <0x0324>; ··· 1079 961 auxclk5_src_ck: auxclk5_src_ck { 1080 962 #clock-cells = <0>; 1081 963 compatible = "ti,composite-clock"; 964 + clock-output-names = "auxclk5_src_ck"; 1082 965 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; 1083 966 }; 1084 967 1085 968 auxclk5_ck: auxclk5_ck@324 { 1086 969 #clock-cells = <0>; 1087 970 compatible = "ti,divider-clock"; 971 + clock-output-names = "auxclk5_ck"; 1088 972 clocks = <&auxclk5_src_ck>; 1089 973 ti,bit-shift = <16>; 1090 974 ti,max-div = <16>; ··· 1096 976 auxclkreq0_ck: auxclkreq0_ck@210 { 1097 977 #clock-cells = <0>; 1098 978 compatible = "ti,mux-clock"; 979 + clock-output-names = "auxclkreq0_ck"; 1099 980 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1100 981 ti,bit-shift = <2>; 1101 982 reg = <0x0210>; ··· 1105 984 auxclkreq1_ck: auxclkreq1_ck@214 { 1106 985 #clock-cells = <0>; 1107 986 compatible = "ti,mux-clock"; 987 + clock-output-names = "auxclkreq1_ck"; 1108 988 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1109 989 ti,bit-shift = <2>; 1110 990 reg = <0x0214>; ··· 1114 992 auxclkreq2_ck: auxclkreq2_ck@218 { 1115 993 #clock-cells = <0>; 1116 994 compatible = "ti,mux-clock"; 995 + clock-output-names = "auxclkreq2_ck"; 1117 996 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1118 997 ti,bit-shift = <2>; 1119 998 reg = <0x0218>; ··· 1123 1000 auxclkreq3_ck: auxclkreq3_ck@21c { 1124 1001 #clock-cells = <0>; 1125 1002 compatible = "ti,mux-clock"; 1003 + clock-output-names = "auxclkreq3_ck"; 1126 1004 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1127 1005 ti,bit-shift = <2>; 1128 1006 reg = <0x021c>; ··· 1132 1008 auxclkreq4_ck: auxclkreq4_ck@220 { 1133 1009 #clock-cells = <0>; 1134 1010 compatible = "ti,mux-clock"; 1011 + clock-output-names = "auxclkreq4_ck"; 1135 1012 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1136 1013 ti,bit-shift = <2>; 1137 1014 reg = <0x0220>; ··· 1141 1016 auxclkreq5_ck: auxclkreq5_ck@224 { 1142 1017 #clock-cells = <0>; 1143 1018 compatible = "ti,mux-clock"; 1019 + clock-output-names = "auxclkreq5_ck"; 1144 1020 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1145 1021 ti,bit-shift = <2>; 1146 1022 reg = <0x0224>; ··· 1151 1025 &cm1 { 1152 1026 mpuss_cm: mpuss_cm@300 { 1153 1027 compatible = "ti,omap4-cm"; 1028 + clock-output-names = "mpuss_cm"; 1154 1029 reg = <0x300 0x100>; 1155 1030 #address-cells = <1>; 1156 1031 #size-cells = <1>; ··· 1159 1032 1160 1033 mpuss_clkctrl: clk@20 { 1161 1034 compatible = "ti,clkctrl"; 1035 + clock-output-names = "mpuss_clkctrl"; 1162 1036 reg = <0x20 0x4>; 1163 1037 #clock-cells = <2>; 1164 1038 }; ··· 1167 1039 1168 1040 tesla_cm: tesla_cm@400 { 1169 1041 compatible = "ti,omap4-cm"; 1042 + clock-output-names = "tesla_cm"; 1170 1043 reg = <0x400 0x100>; 1171 1044 #address-cells = <1>; 1172 1045 #size-cells = <1>; ··· 1175 1046 1176 1047 tesla_clkctrl: clk@20 { 1177 1048 compatible = "ti,clkctrl"; 1049 + clock-output-names = "tesla_clkctrl"; 1178 1050 reg = <0x20 0x4>; 1179 1051 #clock-cells = <2>; 1180 1052 }; ··· 1183 1053 1184 1054 abe_cm: abe_cm@500 { 1185 1055 compatible = "ti,omap4-cm"; 1056 + clock-output-names = "abe_cm"; 1186 1057 reg = <0x500 0x100>; 1187 1058 #address-cells = <1>; 1188 1059 #size-cells = <1>; ··· 1191 1060 1192 1061 abe_clkctrl: clk@20 { 1193 1062 compatible = "ti,clkctrl"; 1063 + clock-output-names = "abe_clkctrl"; 1194 1064 reg = <0x20 0x6c>; 1195 1065 #clock-cells = <2>; 1196 1066 }; ··· 1202 1070 &cm2 { 1203 1071 l4_ao_cm: l4_ao_cm@600 { 1204 1072 compatible = "ti,omap4-cm"; 1073 + clock-output-names = "l4_ao_cm"; 1205 1074 reg = <0x600 0x100>; 1206 1075 #address-cells = <1>; 1207 1076 #size-cells = <1>; ··· 1210 1077 1211 1078 l4_ao_clkctrl: clk@20 { 1212 1079 compatible = "ti,clkctrl"; 1080 + clock-output-names = "l4_ao_clkctrl"; 1213 1081 reg = <0x20 0x1c>; 1214 1082 #clock-cells = <2>; 1215 1083 }; ··· 1218 1084 1219 1085 l3_1_cm: l3_1_cm@700 { 1220 1086 compatible = "ti,omap4-cm"; 1087 + clock-output-names = "l3_1_cm"; 1221 1088 reg = <0x700 0x100>; 1222 1089 #address-cells = <1>; 1223 1090 #size-cells = <1>; ··· 1226 1091 1227 1092 l3_1_clkctrl: clk@20 { 1228 1093 compatible = "ti,clkctrl"; 1094 + clock-output-names = "l3_1_clkctrl"; 1229 1095 reg = <0x20 0x4>; 1230 1096 #clock-cells = <2>; 1231 1097 }; ··· 1234 1098 1235 1099 l3_2_cm: l3_2_cm@800 { 1236 1100 compatible = "ti,omap4-cm"; 1101 + clock-output-names = "l3_2_cm"; 1237 1102 reg = <0x800 0x100>; 1238 1103 #address-cells = <1>; 1239 1104 #size-cells = <1>; ··· 1242 1105 1243 1106 l3_2_clkctrl: clk@20 { 1244 1107 compatible = "ti,clkctrl"; 1108 + clock-output-names = "l3_2_clkctrl"; 1245 1109 reg = <0x20 0x14>; 1246 1110 #clock-cells = <2>; 1247 1111 }; ··· 1250 1112 1251 1113 ducati_cm: ducati_cm@900 { 1252 1114 compatible = "ti,omap4-cm"; 1115 + clock-output-names = "ducati_cm"; 1253 1116 reg = <0x900 0x100>; 1254 1117 #address-cells = <1>; 1255 1118 #size-cells = <1>; ··· 1258 1119 1259 1120 ducati_clkctrl: clk@20 { 1260 1121 compatible = "ti,clkctrl"; 1122 + clock-output-names = "ducati_clkctrl"; 1261 1123 reg = <0x20 0x4>; 1262 1124 #clock-cells = <2>; 1263 1125 }; ··· 1266 1126 1267 1127 l3_dma_cm: l3_dma_cm@a00 { 1268 1128 compatible = "ti,omap4-cm"; 1129 + clock-output-names = "l3_dma_cm"; 1269 1130 reg = <0xa00 0x100>; 1270 1131 #address-cells = <1>; 1271 1132 #size-cells = <1>; ··· 1274 1133 1275 1134 l3_dma_clkctrl: clk@20 { 1276 1135 compatible = "ti,clkctrl"; 1136 + clock-output-names = "l3_dma_clkctrl"; 1277 1137 reg = <0x20 0x4>; 1278 1138 #clock-cells = <2>; 1279 1139 }; ··· 1282 1140 1283 1141 l3_emif_cm: l3_emif_cm@b00 { 1284 1142 compatible = "ti,omap4-cm"; 1143 + clock-output-names = "l3_emif_cm"; 1285 1144 reg = <0xb00 0x100>; 1286 1145 #address-cells = <1>; 1287 1146 #size-cells = <1>; ··· 1290 1147 1291 1148 l3_emif_clkctrl: clk@20 { 1292 1149 compatible = "ti,clkctrl"; 1150 + clock-output-names = "l3_emif_clkctrl"; 1293 1151 reg = <0x20 0x1c>; 1294 1152 #clock-cells = <2>; 1295 1153 }; ··· 1298 1154 1299 1155 d2d_cm: d2d_cm@c00 { 1300 1156 compatible = "ti,omap4-cm"; 1157 + clock-output-names = "d2d_cm"; 1301 1158 reg = <0xc00 0x100>; 1302 1159 #address-cells = <1>; 1303 1160 #size-cells = <1>; ··· 1306 1161 1307 1162 d2d_clkctrl: clk@20 { 1308 1163 compatible = "ti,clkctrl"; 1164 + clock-output-names = "d2d_clkctrl"; 1309 1165 reg = <0x20 0x4>; 1310 1166 #clock-cells = <2>; 1311 1167 }; ··· 1314 1168 1315 1169 l4_cfg_cm: l4_cfg_cm@d00 { 1316 1170 compatible = "ti,omap4-cm"; 1171 + clock-output-names = "l4_cfg_cm"; 1317 1172 reg = <0xd00 0x100>; 1318 1173 #address-cells = <1>; 1319 1174 #size-cells = <1>; ··· 1322 1175 1323 1176 l4_cfg_clkctrl: clk@20 { 1324 1177 compatible = "ti,clkctrl"; 1178 + clock-output-names = "l4_cfg_clkctrl"; 1325 1179 reg = <0x20 0x14>; 1326 1180 #clock-cells = <2>; 1327 1181 }; ··· 1330 1182 1331 1183 l3_instr_cm: l3_instr_cm@e00 { 1332 1184 compatible = "ti,omap4-cm"; 1185 + clock-output-names = "l3_instr_cm"; 1333 1186 reg = <0xe00 0x100>; 1334 1187 #address-cells = <1>; 1335 1188 #size-cells = <1>; ··· 1338 1189 1339 1190 l3_instr_clkctrl: clk@20 { 1340 1191 compatible = "ti,clkctrl"; 1192 + clock-output-names = "l3_instr_clkctrl"; 1341 1193 reg = <0x20 0x24>; 1342 1194 #clock-cells = <2>; 1343 1195 }; ··· 1346 1196 1347 1197 ivahd_cm: ivahd_cm@f00 { 1348 1198 compatible = "ti,omap4-cm"; 1199 + clock-output-names = "ivahd_cm"; 1349 1200 reg = <0xf00 0x100>; 1350 1201 #address-cells = <1>; 1351 1202 #size-cells = <1>; ··· 1354 1203 1355 1204 ivahd_clkctrl: clk@20 { 1356 1205 compatible = "ti,clkctrl"; 1206 + clock-output-names = "ivahd_clkctrl"; 1357 1207 reg = <0x20 0xc>; 1358 1208 #clock-cells = <2>; 1359 1209 }; ··· 1362 1210 1363 1211 iss_cm: iss_cm@1000 { 1364 1212 compatible = "ti,omap4-cm"; 1213 + clock-output-names = "iss_cm"; 1365 1214 reg = <0x1000 0x100>; 1366 1215 #address-cells = <1>; 1367 1216 #size-cells = <1>; ··· 1370 1217 1371 1218 iss_clkctrl: clk@20 { 1372 1219 compatible = "ti,clkctrl"; 1220 + clock-output-names = "iss_clkctrl"; 1373 1221 reg = <0x20 0xc>; 1374 1222 #clock-cells = <2>; 1375 1223 }; ··· 1378 1224 1379 1225 l3_dss_cm: l3_dss_cm@1100 { 1380 1226 compatible = "ti,omap4-cm"; 1227 + clock-output-names = "l3_dss_cm"; 1381 1228 reg = <0x1100 0x100>; 1382 1229 #address-cells = <1>; 1383 1230 #size-cells = <1>; ··· 1386 1231 1387 1232 l3_dss_clkctrl: clk@20 { 1388 1233 compatible = "ti,clkctrl"; 1234 + clock-output-names = "l3_dss_clkctrl"; 1389 1235 reg = <0x20 0x4>; 1390 1236 #clock-cells = <2>; 1391 1237 }; ··· 1394 1238 1395 1239 l3_gfx_cm: l3_gfx_cm@1200 { 1396 1240 compatible = "ti,omap4-cm"; 1241 + clock-output-names = "l3_gfx_cm"; 1397 1242 reg = <0x1200 0x100>; 1398 1243 #address-cells = <1>; 1399 1244 #size-cells = <1>; ··· 1402 1245 1403 1246 l3_gfx_clkctrl: clk@20 { 1404 1247 compatible = "ti,clkctrl"; 1248 + clock-output-names = "l3_gfx_clkctrl"; 1405 1249 reg = <0x20 0x4>; 1406 1250 #clock-cells = <2>; 1407 1251 }; ··· 1410 1252 1411 1253 l3_init_cm: l3_init_cm@1300 { 1412 1254 compatible = "ti,omap4-cm"; 1255 + clock-output-names = "l3_init_cm"; 1413 1256 reg = <0x1300 0x100>; 1414 1257 #address-cells = <1>; 1415 1258 #size-cells = <1>; ··· 1418 1259 1419 1260 l3_init_clkctrl: clk@20 { 1420 1261 compatible = "ti,clkctrl"; 1262 + clock-output-names = "l3_init_clkctrl"; 1421 1263 reg = <0x20 0xc4>; 1422 1264 #clock-cells = <2>; 1423 1265 }; 1424 1266 }; 1425 1267 1426 - l4_per_cm: l4_per_cm@1400 { 1268 + l4_per_cm: clock@1400 { 1427 1269 compatible = "ti,omap4-cm"; 1270 + clock-output-names = "l4_per_cm"; 1428 1271 reg = <0x1400 0x200>; 1429 1272 #address-cells = <1>; 1430 1273 #size-cells = <1>; 1431 1274 ranges = <0 0x1400 0x200>; 1432 1275 1433 1276 l4_per_clkctrl: clock@20 { 1434 - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; 1277 + compatible = "ti,clkctrl"; 1278 + clock-output-names = "l4_per_clkctrl"; 1435 1279 reg = <0x20 0x144>; 1436 1280 #clock-cells = <2>; 1437 1281 }; 1438 1282 1439 1283 l4_secure_clkctrl: clock@1a0 { 1440 - compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; 1284 + compatible = "ti,clkctrl"; 1285 + clock-output-names = "l4_secure_clkctrl"; 1441 1286 reg = <0x1a0 0x3c>; 1442 1287 #clock-cells = <2>; 1443 1288 }; ··· 1451 1288 &prm { 1452 1289 l4_wkup_cm: l4_wkup_cm@1800 { 1453 1290 compatible = "ti,omap4-cm"; 1291 + clock-output-names = "l4_wkup_cm"; 1454 1292 reg = <0x1800 0x100>; 1455 1293 #address-cells = <1>; 1456 1294 #size-cells = <1>; ··· 1459 1295 1460 1296 l4_wkup_clkctrl: clk@20 { 1461 1297 compatible = "ti,clkctrl"; 1298 + clock-output-names = "l4_wkup_clkctrl"; 1462 1299 reg = <0x20 0x5c>; 1463 1300 #clock-cells = <2>; 1464 1301 }; ··· 1467 1302 1468 1303 emu_sys_cm: emu_sys_cm@1a00 { 1469 1304 compatible = "ti,omap4-cm"; 1305 + clock-output-names = "emu_sys_cm"; 1470 1306 reg = <0x1a00 0x100>; 1471 1307 #address-cells = <1>; 1472 1308 #size-cells = <1>; ··· 1475 1309 1476 1310 emu_sys_clkctrl: clk@20 { 1477 1311 compatible = "ti,clkctrl"; 1312 + clock-output-names = "emu_sys_clkctrl"; 1478 1313 reg = <0x20 0x4>; 1479 1314 #clock-cells = <2>; 1480 1315 };

+1 -1

arch/arm/boot/dts/omap5-igep0050.dts

··· 128 128 #address-cells = <1>; 129 129 #size-cells = <0>; 130 130 131 - ethernet: usbether@3 { 131 + ethernet: ethernet@3 { 132 132 compatible = "usb424,7500"; 133 133 reg = <3>; 134 134 };

+1 -1

arch/arm/boot/dts/omap5-uevm.dts

··· 209 209 #size-cells = <0>; 210 210 }; 211 211 212 - ethernet: usbether@3 { 212 + ethernet: ethernet@3 { 213 213 compatible = "usb424,9730"; 214 214 reg = <3>; 215 215 };

+157 -3

arch/arm/boot/dts/omap54xx-clocks.dtsi

··· 8 8 pad_clks_src_ck: pad_clks_src_ck { 9 9 #clock-cells = <0>; 10 10 compatible = "fixed-clock"; 11 + clock-output-names = "pad_clks_src_ck"; 11 12 clock-frequency = <12000000>; 12 13 }; 13 14 14 15 pad_clks_ck: pad_clks_ck@108 { 15 16 #clock-cells = <0>; 16 17 compatible = "ti,gate-clock"; 18 + clock-output-names = "pad_clks_ck"; 17 19 clocks = <&pad_clks_src_ck>; 18 20 ti,bit-shift = <8>; 19 21 reg = <0x0108>; ··· 24 22 secure_32k_clk_src_ck: secure_32k_clk_src_ck { 25 23 #clock-cells = <0>; 26 24 compatible = "fixed-clock"; 25 + clock-output-names = "secure_32k_clk_src_ck"; 27 26 clock-frequency = <32768>; 28 27 }; 29 28 30 29 slimbus_src_clk: slimbus_src_clk { 31 30 #clock-cells = <0>; 32 31 compatible = "fixed-clock"; 32 + clock-output-names = "slimbus_src_clk"; 33 33 clock-frequency = <12000000>; 34 34 }; 35 35 36 36 slimbus_clk: slimbus_clk@108 { 37 37 #clock-cells = <0>; 38 38 compatible = "ti,gate-clock"; 39 + clock-output-names = "slimbus_clk"; 39 40 clocks = <&slimbus_src_clk>; 40 41 ti,bit-shift = <10>; 41 42 reg = <0x0108>; ··· 47 42 sys_32k_ck: sys_32k_ck { 48 43 #clock-cells = <0>; 49 44 compatible = "fixed-clock"; 45 + clock-output-names = "sys_32k_ck"; 50 46 clock-frequency = <32768>; 51 47 }; 52 48 53 49 virt_12000000_ck: virt_12000000_ck { 54 50 #clock-cells = <0>; 55 51 compatible = "fixed-clock"; 52 + clock-output-names = "virt_12000000_ck"; 56 53 clock-frequency = <12000000>; 57 54 }; 58 55 59 56 virt_13000000_ck: virt_13000000_ck { 60 57 #clock-cells = <0>; 61 58 compatible = "fixed-clock"; 59 + clock-output-names = "virt_13000000_ck"; 62 60 clock-frequency = <13000000>; 63 61 }; 64 62 65 63 virt_16800000_ck: virt_16800000_ck { 66 64 #clock-cells = <0>; 67 65 compatible = "fixed-clock"; 66 + clock-output-names = "virt_16800000_ck"; 68 67 clock-frequency = <16800000>; 69 68 }; 70 69 71 70 virt_19200000_ck: virt_19200000_ck { 72 71 #clock-cells = <0>; 73 72 compatible = "fixed-clock"; 73 + clock-output-names = "virt_19200000_ck"; 74 74 clock-frequency = <19200000>; 75 75 }; 76 76 77 77 virt_26000000_ck: virt_26000000_ck { 78 78 #clock-cells = <0>; 79 79 compatible = "fixed-clock"; 80 + clock-output-names = "virt_26000000_ck"; 80 81 clock-frequency = <26000000>; 81 82 }; 82 83 83 84 virt_27000000_ck: virt_27000000_ck { 84 85 #clock-cells = <0>; 85 86 compatible = "fixed-clock"; 87 + clock-output-names = "virt_27000000_ck"; 86 88 clock-frequency = <27000000>; 87 89 }; 88 90 89 91 virt_38400000_ck: virt_38400000_ck { 90 92 #clock-cells = <0>; 91 93 compatible = "fixed-clock"; 94 + clock-output-names = "virt_38400000_ck"; 92 95 clock-frequency = <38400000>; 93 96 }; 94 97 95 98 xclk60mhsp1_ck: xclk60mhsp1_ck { 96 99 #clock-cells = <0>; 97 100 compatible = "fixed-clock"; 101 + clock-output-names = "xclk60mhsp1_ck"; 98 102 clock-frequency = <60000000>; 99 103 }; 100 104 101 105 xclk60mhsp2_ck: xclk60mhsp2_ck { 102 106 #clock-cells = <0>; 103 107 compatible = "fixed-clock"; 108 + clock-output-names = "xclk60mhsp2_ck"; 104 109 clock-frequency = <60000000>; 105 110 }; 106 111 107 112 dpll_abe_ck: dpll_abe_ck@1e0 { 108 113 #clock-cells = <0>; 109 114 compatible = "ti,omap4-dpll-m4xen-clock"; 115 + clock-output-names = "dpll_abe_ck"; 110 116 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; 111 117 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 112 118 }; ··· 125 109 dpll_abe_x2_ck: dpll_abe_x2_ck { 126 110 #clock-cells = <0>; 127 111 compatible = "ti,omap4-dpll-x2-clock"; 112 + clock-output-names = "dpll_abe_x2_ck"; 128 113 clocks = <&dpll_abe_ck>; 129 114 }; 130 115 131 116 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { 132 117 #clock-cells = <0>; 133 118 compatible = "ti,divider-clock"; 119 + clock-output-names = "dpll_abe_m2x2_ck"; 134 120 clocks = <&dpll_abe_x2_ck>; 135 121 ti,max-div = <31>; 136 122 reg = <0x01f0>; ··· 142 124 abe_24m_fclk: abe_24m_fclk { 143 125 #clock-cells = <0>; 144 126 compatible = "fixed-factor-clock"; 127 + clock-output-names = "abe_24m_fclk"; 145 128 clocks = <&dpll_abe_m2x2_ck>; 146 129 clock-mult = <1>; 147 130 clock-div = <8>; ··· 151 132 abe_clk: abe_clk@108 { 152 133 #clock-cells = <0>; 153 134 compatible = "ti,divider-clock"; 135 + clock-output-names = "abe_clk"; 154 136 clocks = <&dpll_abe_m2x2_ck>; 155 137 ti,max-div = <4>; 156 138 reg = <0x0108>; ··· 161 141 abe_iclk: abe_iclk@528 { 162 142 #clock-cells = <0>; 163 143 compatible = "ti,divider-clock"; 144 + clock-output-names = "abe_iclk"; 164 145 clocks = <&aess_fclk>; 165 146 ti,bit-shift = <24>; 166 147 reg = <0x0528>; ··· 171 150 abe_lp_clk_div: abe_lp_clk_div { 172 151 #clock-cells = <0>; 173 152 compatible = "fixed-factor-clock"; 153 + clock-output-names = "abe_lp_clk_div"; 174 154 clocks = <&dpll_abe_m2x2_ck>; 175 155 clock-mult = <1>; 176 156 clock-div = <16>; ··· 180 158 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { 181 159 #clock-cells = <0>; 182 160 compatible = "ti,divider-clock"; 161 + clock-output-names = "dpll_abe_m3x2_ck"; 183 162 clocks = <&dpll_abe_x2_ck>; 184 163 ti,max-div = <31>; 185 164 reg = <0x01f4>; ··· 190 167 dpll_core_byp_mux: dpll_core_byp_mux@12c { 191 168 #clock-cells = <0>; 192 169 compatible = "ti,mux-clock"; 170 + clock-output-names = "dpll_core_byp_mux"; 193 171 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 194 172 ti,bit-shift = <23>; 195 173 reg = <0x012c>; ··· 199 175 dpll_core_ck: dpll_core_ck@120 { 200 176 #clock-cells = <0>; 201 177 compatible = "ti,omap4-dpll-core-clock"; 178 + clock-output-names = "dpll_core_ck"; 202 179 clocks = <&sys_clkin>, <&dpll_core_byp_mux>; 203 180 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 204 181 }; ··· 207 182 dpll_core_x2_ck: dpll_core_x2_ck { 208 183 #clock-cells = <0>; 209 184 compatible = "ti,omap4-dpll-x2-clock"; 185 + clock-output-names = "dpll_core_x2_ck"; 210 186 clocks = <&dpll_core_ck>; 211 187 }; 212 188 213 189 dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { 214 190 #clock-cells = <0>; 215 191 compatible = "ti,divider-clock"; 192 + clock-output-names = "dpll_core_h21x2_ck"; 216 193 clocks = <&dpll_core_x2_ck>; 217 194 ti,max-div = <63>; 218 195 reg = <0x0150>; ··· 224 197 c2c_fclk: c2c_fclk { 225 198 #clock-cells = <0>; 226 199 compatible = "fixed-factor-clock"; 200 + clock-output-names = "c2c_fclk"; 227 201 clocks = <&dpll_core_h21x2_ck>; 228 202 clock-mult = <1>; 229 203 clock-div = <1>; ··· 233 205 c2c_iclk: c2c_iclk { 234 206 #clock-cells = <0>; 235 207 compatible = "fixed-factor-clock"; 208 + clock-output-names = "c2c_iclk"; 236 209 clocks = <&c2c_fclk>; 237 210 clock-mult = <1>; 238 211 clock-div = <2>; ··· 242 213 dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { 243 214 #clock-cells = <0>; 244 215 compatible = "ti,divider-clock"; 216 + clock-output-names = "dpll_core_h11x2_ck"; 245 217 clocks = <&dpll_core_x2_ck>; 246 218 ti,max-div = <63>; 247 219 reg = <0x0138>; ··· 252 222 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { 253 223 #clock-cells = <0>; 254 224 compatible = "ti,divider-clock"; 225 + clock-output-names = "dpll_core_h12x2_ck"; 255 226 clocks = <&dpll_core_x2_ck>; 256 227 ti,max-div = <63>; 257 228 reg = <0x013c>; ··· 262 231 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { 263 232 #clock-cells = <0>; 264 233 compatible = "ti,divider-clock"; 234 + clock-output-names = "dpll_core_h13x2_ck"; 265 235 clocks = <&dpll_core_x2_ck>; 266 236 ti,max-div = <63>; 267 237 reg = <0x0140>; ··· 272 240 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { 273 241 #clock-cells = <0>; 274 242 compatible = "ti,divider-clock"; 243 + clock-output-names = "dpll_core_h14x2_ck"; 275 244 clocks = <&dpll_core_x2_ck>; 276 245 ti,max-div = <63>; 277 246 reg = <0x0144>; ··· 282 249 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { 283 250 #clock-cells = <0>; 284 251 compatible = "ti,divider-clock"; 252 + clock-output-names = "dpll_core_h22x2_ck"; 285 253 clocks = <&dpll_core_x2_ck>; 286 254 ti,max-div = <63>; 287 255 reg = <0x0154>; ··· 292 258 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { 293 259 #clock-cells = <0>; 294 260 compatible = "ti,divider-clock"; 261 + clock-output-names = "dpll_core_h23x2_ck"; 295 262 clocks = <&dpll_core_x2_ck>; 296 263 ti,max-div = <63>; 297 264 reg = <0x0158>; ··· 302 267 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { 303 268 #clock-cells = <0>; 304 269 compatible = "ti,divider-clock"; 270 + clock-output-names = "dpll_core_h24x2_ck"; 305 271 clocks = <&dpll_core_x2_ck>; 306 272 ti,max-div = <63>; 307 273 reg = <0x015c>; ··· 312 276 dpll_core_m2_ck: dpll_core_m2_ck@130 { 313 277 #clock-cells = <0>; 314 278 compatible = "ti,divider-clock"; 279 + clock-output-names = "dpll_core_m2_ck"; 315 280 clocks = <&dpll_core_ck>; 316 281 ti,max-div = <31>; 317 282 reg = <0x0130>; ··· 322 285 dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { 323 286 #clock-cells = <0>; 324 287 compatible = "ti,divider-clock"; 288 + clock-output-names = "dpll_core_m3x2_ck"; 325 289 clocks = <&dpll_core_x2_ck>; 326 290 ti,max-div = <31>; 327 291 reg = <0x0134>; ··· 332 294 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { 333 295 #clock-cells = <0>; 334 296 compatible = "fixed-factor-clock"; 297 + clock-output-names = "iva_dpll_hs_clk_div"; 335 298 clocks = <&dpll_core_h12x2_ck>; 336 299 clock-mult = <1>; 337 300 clock-div = <1>; ··· 341 302 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { 342 303 #clock-cells = <0>; 343 304 compatible = "ti,mux-clock"; 305 + clock-output-names = "dpll_iva_byp_mux"; 344 306 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 345 307 ti,bit-shift = <23>; 346 308 reg = <0x01ac>; ··· 350 310 dpll_iva_ck: dpll_iva_ck@1a0 { 351 311 #clock-cells = <0>; 352 312 compatible = "ti,omap4-dpll-clock"; 313 + clock-output-names = "dpll_iva_ck"; 353 314 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; 354 315 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 355 316 assigned-clocks = <&dpll_iva_ck>; ··· 360 319 dpll_iva_x2_ck: dpll_iva_x2_ck { 361 320 #clock-cells = <0>; 362 321 compatible = "ti,omap4-dpll-x2-clock"; 322 + clock-output-names = "dpll_iva_x2_ck"; 363 323 clocks = <&dpll_iva_ck>; 364 324 }; 365 325 366 326 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { 367 327 #clock-cells = <0>; 368 328 compatible = "ti,divider-clock"; 329 + clock-output-names = "dpll_iva_h11x2_ck"; 369 330 clocks = <&dpll_iva_x2_ck>; 370 331 ti,max-div = <63>; 371 332 reg = <0x01b8>; ··· 379 336 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { 380 337 #clock-cells = <0>; 381 338 compatible = "ti,divider-clock"; 339 + clock-output-names = "dpll_iva_h12x2_ck"; 382 340 clocks = <&dpll_iva_x2_ck>; 383 341 ti,max-div = <63>; 384 342 reg = <0x01bc>; ··· 391 347 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { 392 348 #clock-cells = <0>; 393 349 compatible = "fixed-factor-clock"; 350 + clock-output-names = "mpu_dpll_hs_clk_div"; 394 351 clocks = <&dpll_core_h12x2_ck>; 395 352 clock-mult = <1>; 396 353 clock-div = <1>; ··· 400 355 dpll_mpu_ck: dpll_mpu_ck@160 { 401 356 #clock-cells = <0>; 402 357 compatible = "ti,omap5-mpu-dpll-clock"; 358 + clock-output-names = "dpll_mpu_ck"; 403 359 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; 404 360 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 405 361 }; ··· 408 362 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { 409 363 #clock-cells = <0>; 410 364 compatible = "ti,divider-clock"; 365 + clock-output-names = "dpll_mpu_m2_ck"; 411 366 clocks = <&dpll_mpu_ck>; 412 367 ti,max-div = <31>; 413 368 reg = <0x0170>; ··· 418 371 per_dpll_hs_clk_div: per_dpll_hs_clk_div { 419 372 #clock-cells = <0>; 420 373 compatible = "fixed-factor-clock"; 374 + clock-output-names = "per_dpll_hs_clk_div"; 421 375 clocks = <&dpll_abe_m3x2_ck>; 422 376 clock-mult = <1>; 423 377 clock-div = <2>; ··· 427 379 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { 428 380 #clock-cells = <0>; 429 381 compatible = "fixed-factor-clock"; 382 + clock-output-names = "usb_dpll_hs_clk_div"; 430 383 clocks = <&dpll_abe_m3x2_ck>; 431 384 clock-mult = <1>; 432 385 clock-div = <3>; ··· 436 387 l3_iclk_div: l3_iclk_div@100 { 437 388 #clock-cells = <0>; 438 389 compatible = "ti,divider-clock"; 390 + clock-output-names = "l3_iclk_div"; 439 391 ti,max-div = <2>; 440 392 ti,bit-shift = <4>; 441 393 reg = <0x100>; ··· 447 397 gpu_l3_iclk: gpu_l3_iclk { 448 398 #clock-cells = <0>; 449 399 compatible = "fixed-factor-clock"; 400 + clock-output-names = "gpu_l3_iclk"; 450 401 clocks = <&l3_iclk_div>; 451 402 clock-mult = <1>; 452 403 clock-div = <1>; ··· 456 405 l4_root_clk_div: l4_root_clk_div@100 { 457 406 #clock-cells = <0>; 458 407 compatible = "ti,divider-clock"; 408 + clock-output-names = "l4_root_clk_div"; 459 409 ti,max-div = <2>; 460 410 ti,bit-shift = <8>; 461 411 reg = <0x100>; ··· 467 415 slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { 468 416 #clock-cells = <0>; 469 417 compatible = "ti,gate-clock"; 418 + clock-output-names = "slimbus1_slimbus_clk"; 470 419 clocks = <&slimbus_clk>; 471 420 ti,bit-shift = <11>; 472 421 reg = <0x0560>; ··· 476 423 aess_fclk: aess_fclk@528 { 477 424 #clock-cells = <0>; 478 425 compatible = "ti,divider-clock"; 426 + clock-output-names = "aess_fclk"; 479 427 clocks = <&abe_clk>; 480 428 ti,bit-shift = <24>; 481 429 ti,max-div = <2>; ··· 486 432 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { 487 433 #clock-cells = <0>; 488 434 compatible = "ti,mux-clock"; 435 + clock-output-names = "mcasp_sync_mux_ck"; 489 436 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 490 437 ti,bit-shift = <26>; 491 438 reg = <0x0540>; ··· 495 440 mcasp_gfclk: mcasp_gfclk@540 { 496 441 #clock-cells = <0>; 497 442 compatible = "ti,mux-clock"; 443 + clock-output-names = "mcasp_gfclk"; 498 444 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 499 445 ti,bit-shift = <24>; 500 446 reg = <0x0540>; ··· 504 448 dummy_ck: dummy_ck { 505 449 #clock-cells = <0>; 506 450 compatible = "fixed-clock"; 451 + clock-output-names = "dummy_ck"; 507 452 clock-frequency = <0>; 508 453 }; 509 454 }; ··· 512 455 sys_clkin: sys_clkin@110 { 513 456 #clock-cells = <0>; 514 457 compatible = "ti,mux-clock"; 458 + clock-output-names = "sys_clkin"; 515 459 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 516 460 reg = <0x0110>; 517 461 ti,index-starts-at-one; ··· 521 463 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { 522 464 #clock-cells = <0>; 523 465 compatible = "ti,mux-clock"; 466 + clock-output-names = "abe_dpll_bypass_clk_mux"; 524 467 clocks = <&sys_clkin>, <&sys_32k_ck>; 525 468 reg = <0x0108>; 526 469 }; ··· 529 470 abe_dpll_clk_mux: abe_dpll_clk_mux@10c { 530 471 #clock-cells = <0>; 531 472 compatible = "ti,mux-clock"; 473 + clock-output-names = "abe_dpll_clk_mux"; 532 474 clocks = <&sys_clkin>, <&sys_32k_ck>; 533 475 reg = <0x010c>; 534 476 }; ··· 537 477 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { 538 478 #clock-cells = <0>; 539 479 compatible = "fixed-factor-clock"; 480 + clock-output-names = "custefuse_sys_gfclk_div"; 540 481 clocks = <&sys_clkin>; 541 482 clock-mult = <1>; 542 483 clock-div = <2>; ··· 546 485 dss_syc_gfclk_div: dss_syc_gfclk_div { 547 486 #clock-cells = <0>; 548 487 compatible = "fixed-factor-clock"; 488 + clock-output-names = "dss_syc_gfclk_div"; 549 489 clocks = <&sys_clkin>; 550 490 clock-mult = <1>; 551 491 clock-div = <1>; ··· 555 493 wkupaon_iclk_mux: wkupaon_iclk_mux@108 { 556 494 #clock-cells = <0>; 557 495 compatible = "ti,mux-clock"; 496 + clock-output-names = "wkupaon_iclk_mux"; 558 497 clocks = <&sys_clkin>, <&abe_lp_clk_div>; 559 498 reg = <0x0108>; 560 499 }; ··· 563 500 l3instr_ts_gclk_div: l3instr_ts_gclk_div { 564 501 #clock-cells = <0>; 565 502 compatible = "fixed-factor-clock"; 503 + clock-output-names = "l3instr_ts_gclk_div"; 566 504 clocks = <&wkupaon_iclk_mux>; 567 505 clock-mult = <1>; 568 506 clock-div = <1>; ··· 575 511 dpll_per_byp_mux: dpll_per_byp_mux@14c { 576 512 #clock-cells = <0>; 577 513 compatible = "ti,mux-clock"; 514 + clock-output-names = "dpll_per_byp_mux"; 578 515 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 579 516 ti,bit-shift = <23>; 580 517 reg = <0x014c>; ··· 584 519 dpll_per_ck: dpll_per_ck@140 { 585 520 #clock-cells = <0>; 586 521 compatible = "ti,omap4-dpll-clock"; 522 + clock-output-names = "dpll_per_ck"; 587 523 clocks = <&sys_clkin>, <&dpll_per_byp_mux>; 588 524 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 589 525 }; ··· 592 526 dpll_per_x2_ck: dpll_per_x2_ck { 593 527 #clock-cells = <0>; 594 528 compatible = "ti,omap4-dpll-x2-clock"; 529 + clock-output-names = "dpll_per_x2_ck"; 595 530 clocks = <&dpll_per_ck>; 596 531 }; 597 532 598 533 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { 599 534 #clock-cells = <0>; 600 535 compatible = "ti,divider-clock"; 536 + clock-output-names = "dpll_per_h11x2_ck"; 601 537 clocks = <&dpll_per_x2_ck>; 602 538 ti,max-div = <63>; 603 539 reg = <0x0158>; ··· 609 541 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { 610 542 #clock-cells = <0>; 611 543 compatible = "ti,divider-clock"; 544 + clock-output-names = "dpll_per_h12x2_ck"; 612 545 clocks = <&dpll_per_x2_ck>; 613 546 ti,max-div = <63>; 614 547 reg = <0x015c>; ··· 619 550 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { 620 551 #clock-cells = <0>; 621 552 compatible = "ti,divider-clock"; 553 + clock-output-names = "dpll_per_h14x2_ck"; 622 554 clocks = <&dpll_per_x2_ck>; 623 555 ti,max-div = <63>; 624 556 reg = <0x0164>; ··· 629 559 dpll_per_m2_ck: dpll_per_m2_ck@150 { 630 560 #clock-cells = <0>; 631 561 compatible = "ti,divider-clock"; 562 + clock-output-names = "dpll_per_m2_ck"; 632 563 clocks = <&dpll_per_ck>; 633 564 ti,max-div = <31>; 634 565 reg = <0x0150>; ··· 639 568 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { 640 569 #clock-cells = <0>; 641 570 compatible = "ti,divider-clock"; 571 + clock-output-names = "dpll_per_m2x2_ck"; 642 572 clocks = <&dpll_per_x2_ck>; 643 573 ti,max-div = <31>; 644 574 reg = <0x0150>; ··· 649 577 dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { 650 578 #clock-cells = <0>; 651 579 compatible = "ti,divider-clock"; 580 + clock-output-names = "dpll_per_m3x2_ck"; 652 581 clocks = <&dpll_per_x2_ck>; 653 582 ti,max-div = <31>; 654 583 reg = <0x0154>; ··· 659 586 dpll_unipro1_ck: dpll_unipro1_ck@200 { 660 587 #clock-cells = <0>; 661 588 compatible = "ti,omap4-dpll-clock"; 589 + clock-output-names = "dpll_unipro1_ck"; 662 590 clocks = <&sys_clkin>, <&sys_clkin>; 663 591 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; 664 592 }; ··· 667 593 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { 668 594 #clock-cells = <0>; 669 595 compatible = "fixed-factor-clock"; 596 + clock-output-names = "dpll_unipro1_clkdcoldo"; 670 597 clocks = <&dpll_unipro1_ck>; 671 598 clock-mult = <1>; 672 599 clock-div = <1>; ··· 676 601 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { 677 602 #clock-cells = <0>; 678 603 compatible = "ti,divider-clock"; 604 + clock-output-names = "dpll_unipro1_m2_ck"; 679 605 clocks = <&dpll_unipro1_ck>; 680 606 ti,max-div = <127>; 681 607 reg = <0x0210>; ··· 686 610 dpll_unipro2_ck: dpll_unipro2_ck@1c0 { 687 611 #clock-cells = <0>; 688 612 compatible = "ti,omap4-dpll-clock"; 613 + clock-output-names = "dpll_unipro2_ck"; 689 614 clocks = <&sys_clkin>, <&sys_clkin>; 690 615 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; 691 616 }; ··· 694 617 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { 695 618 #clock-cells = <0>; 696 619 compatible = "fixed-factor-clock"; 620 + clock-output-names = "dpll_unipro2_clkdcoldo"; 697 621 clocks = <&dpll_unipro2_ck>; 698 622 clock-mult = <1>; 699 623 clock-div = <1>; ··· 703 625 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { 704 626 #clock-cells = <0>; 705 627 compatible = "ti,divider-clock"; 628 + clock-output-names = "dpll_unipro2_m2_ck"; 706 629 clocks = <&dpll_unipro2_ck>; 707 630 ti,max-div = <127>; 708 631 reg = <0x01d0>; ··· 713 634 dpll_usb_byp_mux: dpll_usb_byp_mux@18c { 714 635 #clock-cells = <0>; 715 636 compatible = "ti,mux-clock"; 637 + clock-output-names = "dpll_usb_byp_mux"; 716 638 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 717 639 ti,bit-shift = <23>; 718 640 reg = <0x018c>; ··· 722 642 dpll_usb_ck: dpll_usb_ck@180 { 723 643 #clock-cells = <0>; 724 644 compatible = "ti,omap4-dpll-j-type-clock"; 645 + clock-output-names = "dpll_usb_ck"; 725 646 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; 726 647 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 727 648 }; ··· 730 649 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { 731 650 #clock-cells = <0>; 732 651 compatible = "fixed-factor-clock"; 652 + clock-output-names = "dpll_usb_clkdcoldo"; 733 653 clocks = <&dpll_usb_ck>; 734 654 clock-mult = <1>; 735 655 clock-div = <1>; ··· 739 657 dpll_usb_m2_ck: dpll_usb_m2_ck@190 { 740 658 #clock-cells = <0>; 741 659 compatible = "ti,divider-clock"; 660 + clock-output-names = "dpll_usb_m2_ck"; 742 661 clocks = <&dpll_usb_ck>; 743 662 ti,max-div = <127>; 744 663 reg = <0x0190>; ··· 749 666 func_128m_clk: func_128m_clk { 750 667 #clock-cells = <0>; 751 668 compatible = "fixed-factor-clock"; 669 + clock-output-names = "func_128m_clk"; 752 670 clocks = <&dpll_per_h11x2_ck>; 753 671 clock-mult = <1>; 754 672 clock-div = <2>; ··· 758 674 func_12m_fclk: func_12m_fclk { 759 675 #clock-cells = <0>; 760 676 compatible = "fixed-factor-clock"; 677 + clock-output-names = "func_12m_fclk"; 761 678 clocks = <&dpll_per_m2x2_ck>; 762 679 clock-mult = <1>; 763 680 clock-div = <16>; ··· 767 682 func_24m_clk: func_24m_clk { 768 683 #clock-cells = <0>; 769 684 compatible = "fixed-factor-clock"; 685 + clock-output-names = "func_24m_clk"; 770 686 clocks = <&dpll_per_m2_ck>; 771 687 clock-mult = <1>; 772 688 clock-div = <4>; ··· 776 690 func_48m_fclk: func_48m_fclk { 777 691 #clock-cells = <0>; 778 692 compatible = "fixed-factor-clock"; 693 + clock-output-names = "func_48m_fclk"; 779 694 clocks = <&dpll_per_m2x2_ck>; 780 695 clock-mult = <1>; 781 696 clock-div = <4>; ··· 785 698 func_96m_fclk: func_96m_fclk { 786 699 #clock-cells = <0>; 787 700 compatible = "fixed-factor-clock"; 701 + clock-output-names = "func_96m_fclk"; 788 702 clocks = <&dpll_per_m2x2_ck>; 789 703 clock-mult = <1>; 790 704 clock-div = <2>; ··· 794 706 l3init_60m_fclk: l3init_60m_fclk@104 { 795 707 #clock-cells = <0>; 796 708 compatible = "ti,divider-clock"; 709 + clock-output-names = "l3init_60m_fclk"; 797 710 clocks = <&dpll_usb_m2_ck>; 798 711 reg = <0x0104>; 799 712 ti,dividers = <1>, <8>; ··· 803 714 iss_ctrlclk: iss_ctrlclk@1320 { 804 715 #clock-cells = <0>; 805 716 compatible = "ti,gate-clock"; 717 + clock-output-names = "iss_ctrlclk"; 806 718 clocks = <&func_96m_fclk>; 807 719 ti,bit-shift = <8>; 808 720 reg = <0x1320>; ··· 812 722 lli_txphy_clk: lli_txphy_clk@f20 { 813 723 #clock-cells = <0>; 814 724 compatible = "ti,gate-clock"; 725 + clock-output-names = "lli_txphy_clk"; 815 726 clocks = <&dpll_unipro1_clkdcoldo>; 816 727 ti,bit-shift = <8>; 817 728 reg = <0x0f20>; ··· 821 730 lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { 822 731 #clock-cells = <0>; 823 732 compatible = "ti,gate-clock"; 733 + clock-output-names = "lli_txphy_ls_clk"; 824 734 clocks = <&dpll_unipro1_m2_ck>; 825 735 ti,bit-shift = <9>; 826 736 reg = <0x0f20>; ··· 830 738 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { 831 739 #clock-cells = <0>; 832 740 compatible = "ti,gate-clock"; 741 + clock-output-names = "usb_phy_cm_clk32k"; 833 742 clocks = <&sys_32k_ck>; 834 743 ti,bit-shift = <8>; 835 744 reg = <0x0640>; ··· 839 746 fdif_fclk: fdif_fclk@1328 { 840 747 #clock-cells = <0>; 841 748 compatible = "ti,divider-clock"; 749 + clock-output-names = "fdif_fclk"; 842 750 clocks = <&dpll_per_h11x2_ck>; 843 751 ti,bit-shift = <24>; 844 752 ti,max-div = <2>; ··· 849 755 gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { 850 756 #clock-cells = <0>; 851 757 compatible = "ti,mux-clock"; 758 + clock-output-names = "gpu_core_gclk_mux"; 852 759 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; 853 760 ti,bit-shift = <24>; 854 761 reg = <0x1520>; ··· 858 763 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { 859 764 #clock-cells = <0>; 860 765 compatible = "ti,mux-clock"; 766 + clock-output-names = "gpu_hyd_gclk_mux"; 861 767 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; 862 768 ti,bit-shift = <25>; 863 769 reg = <0x1520>; ··· 867 771 hsi_fclk: hsi_fclk@1638 { 868 772 #clock-cells = <0>; 869 773 compatible = "ti,divider-clock"; 774 + clock-output-names = "hsi_fclk"; 870 775 clocks = <&dpll_per_m2x2_ck>; 871 776 ti,bit-shift = <24>; 872 777 ti,max-div = <2>; ··· 878 781 &cm_core_clockdomains { 879 782 l3init_clkdm: l3init_clkdm { 880 783 compatible = "ti,clockdomain"; 784 + clock-output-names = "l3init_clkdm"; 881 785 clocks = <&dpll_usb_ck>; 882 786 }; 883 787 }; ··· 887 789 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { 888 790 #clock-cells = <0>; 889 791 compatible = "ti,composite-no-wait-gate-clock"; 792 + clock-output-names = "auxclk0_src_gate_ck"; 890 793 clocks = <&dpll_core_m3x2_ck>; 891 794 ti,bit-shift = <8>; 892 795 reg = <0x0310>; ··· 896 797 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { 897 798 #clock-cells = <0>; 898 799 compatible = "ti,composite-mux-clock"; 800 + clock-output-names = "auxclk0_src_mux_ck"; 899 801 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 900 802 ti,bit-shift = <1>; 901 803 reg = <0x0310>; ··· 905 805 auxclk0_src_ck: auxclk0_src_ck { 906 806 #clock-cells = <0>; 907 807 compatible = "ti,composite-clock"; 808 + clock-output-names = "auxclk0_src_ck"; 908 809 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; 909 810 }; 910 811 911 812 auxclk0_ck: auxclk0_ck@310 { 912 813 #clock-cells = <0>; 913 814 compatible = "ti,divider-clock"; 815 + clock-output-names = "auxclk0_ck"; 914 816 clocks = <&auxclk0_src_ck>; 915 817 ti,bit-shift = <16>; 916 818 ti,max-div = <16>; ··· 922 820 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { 923 821 #clock-cells = <0>; 924 822 compatible = "ti,composite-no-wait-gate-clock"; 823 + clock-output-names = "auxclk1_src_gate_ck"; 925 824 clocks = <&dpll_core_m3x2_ck>; 926 825 ti,bit-shift = <8>; 927 826 reg = <0x0314>; ··· 931 828 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { 932 829 #clock-cells = <0>; 933 830 compatible = "ti,composite-mux-clock"; 831 + clock-output-names = "auxclk1_src_mux_ck"; 934 832 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 935 833 ti,bit-shift = <1>; 936 834 reg = <0x0314>; ··· 940 836 auxclk1_src_ck: auxclk1_src_ck { 941 837 #clock-cells = <0>; 942 838 compatible = "ti,composite-clock"; 839 + clock-output-names = "auxclk1_src_ck"; 943 840 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; 944 841 }; 945 842 946 843 auxclk1_ck: auxclk1_ck@314 { 947 844 #clock-cells = <0>; 948 845 compatible = "ti,divider-clock"; 846 + clock-output-names = "auxclk1_ck"; 949 847 clocks = <&auxclk1_src_ck>; 950 848 ti,bit-shift = <16>; 951 849 ti,max-div = <16>; ··· 957 851 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { 958 852 #clock-cells = <0>; 959 853 compatible = "ti,composite-no-wait-gate-clock"; 854 + clock-output-names = "auxclk2_src_gate_ck"; 960 855 clocks = <&dpll_core_m3x2_ck>; 961 856 ti,bit-shift = <8>; 962 857 reg = <0x0318>; ··· 966 859 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { 967 860 #clock-cells = <0>; 968 861 compatible = "ti,composite-mux-clock"; 862 + clock-output-names = "auxclk2_src_mux_ck"; 969 863 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 970 864 ti,bit-shift = <1>; 971 865 reg = <0x0318>; ··· 975 867 auxclk2_src_ck: auxclk2_src_ck { 976 868 #clock-cells = <0>; 977 869 compatible = "ti,composite-clock"; 870 + clock-output-names = "auxclk2_src_ck"; 978 871 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; 979 872 }; 980 873 981 874 auxclk2_ck: auxclk2_ck@318 { 982 875 #clock-cells = <0>; 983 876 compatible = "ti,divider-clock"; 877 + clock-output-names = "auxclk2_ck"; 984 878 clocks = <&auxclk2_src_ck>; 985 879 ti,bit-shift = <16>; 986 880 ti,max-div = <16>; ··· 992 882 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { 993 883 #clock-cells = <0>; 994 884 compatible = "ti,composite-no-wait-gate-clock"; 885 + clock-output-names = "auxclk3_src_gate_ck"; 995 886 clocks = <&dpll_core_m3x2_ck>; 996 887 ti,bit-shift = <8>; 997 888 reg = <0x031c>; ··· 1001 890 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { 1002 891 #clock-cells = <0>; 1003 892 compatible = "ti,composite-mux-clock"; 893 + clock-output-names = "auxclk3_src_mux_ck"; 1004 894 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1005 895 ti,bit-shift = <1>; 1006 896 reg = <0x031c>; ··· 1010 898 auxclk3_src_ck: auxclk3_src_ck { 1011 899 #clock-cells = <0>; 1012 900 compatible = "ti,composite-clock"; 901 + clock-output-names = "auxclk3_src_ck"; 1013 902 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; 1014 903 }; 1015 904 1016 905 auxclk3_ck: auxclk3_ck@31c { 1017 906 #clock-cells = <0>; 1018 907 compatible = "ti,divider-clock"; 908 + clock-output-names = "auxclk3_ck"; 1019 909 clocks = <&auxclk3_src_ck>; 1020 910 ti,bit-shift = <16>; 1021 911 ti,max-div = <16>; ··· 1027 913 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { 1028 914 #clock-cells = <0>; 1029 915 compatible = "ti,composite-no-wait-gate-clock"; 916 + clock-output-names = "auxclk4_src_gate_ck"; 1030 917 clocks = <&dpll_core_m3x2_ck>; 1031 918 ti,bit-shift = <8>; 1032 919 reg = <0x0320>; ··· 1036 921 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { 1037 922 #clock-cells = <0>; 1038 923 compatible = "ti,composite-mux-clock"; 924 + clock-output-names = "auxclk4_src_mux_ck"; 1039 925 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1040 926 ti,bit-shift = <1>; 1041 927 reg = <0x0320>; ··· 1045 929 auxclk4_src_ck: auxclk4_src_ck { 1046 930 #clock-cells = <0>; 1047 931 compatible = "ti,composite-clock"; 932 + clock-output-names = "auxclk4_src_ck"; 1048 933 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; 1049 934 }; 1050 935 1051 936 auxclk4_ck: auxclk4_ck@320 { 1052 937 #clock-cells = <0>; 1053 938 compatible = "ti,divider-clock"; 939 + clock-output-names = "auxclk4_ck"; 1054 940 clocks = <&auxclk4_src_ck>; 1055 941 ti,bit-shift = <16>; 1056 942 ti,max-div = <16>; ··· 1062 944 auxclkreq0_ck: auxclkreq0_ck@210 { 1063 945 #clock-cells = <0>; 1064 946 compatible = "ti,mux-clock"; 947 + clock-output-names = "auxclkreq0_ck"; 1065 948 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1066 949 ti,bit-shift = <2>; 1067 950 reg = <0x0210>; ··· 1071 952 auxclkreq1_ck: auxclkreq1_ck@214 { 1072 953 #clock-cells = <0>; 1073 954 compatible = "ti,mux-clock"; 955 + clock-output-names = "auxclkreq1_ck"; 1074 956 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1075 957 ti,bit-shift = <2>; 1076 958 reg = <0x0214>; ··· 1080 960 auxclkreq2_ck: auxclkreq2_ck@218 { 1081 961 #clock-cells = <0>; 1082 962 compatible = "ti,mux-clock"; 963 + clock-output-names = "auxclkreq2_ck"; 1083 964 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1084 965 ti,bit-shift = <2>; 1085 966 reg = <0x0218>; ··· 1089 968 auxclkreq3_ck: auxclkreq3_ck@21c { 1090 969 #clock-cells = <0>; 1091 970 compatible = "ti,mux-clock"; 971 + clock-output-names = "auxclkreq3_ck"; 1092 972 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1093 973 ti,bit-shift = <2>; 1094 974 reg = <0x021c>; ··· 1099 977 &cm_core_aon { 1100 978 mpu_cm: mpu_cm@300 { 1101 979 compatible = "ti,omap4-cm"; 980 + clock-output-names = "mpu_cm"; 1102 981 reg = <0x300 0x100>; 1103 982 #address-cells = <1>; 1104 983 #size-cells = <1>; ··· 1107 984 1108 985 mpu_clkctrl: clk@20 { 1109 986 compatible = "ti,clkctrl"; 987 + clock-output-names = "mpu_clkctrl"; 1110 988 reg = <0x20 0x4>; 1111 989 #clock-cells = <2>; 1112 990 }; ··· 1115 991 1116 992 dsp_cm: dsp_cm@400 { 1117 993 compatible = "ti,omap4-cm"; 994 + clock-output-names = "dsp_cm"; 1118 995 reg = <0x400 0x100>; 1119 996 #address-cells = <1>; 1120 997 #size-cells = <1>; ··· 1123 998 1124 999 dsp_clkctrl: clk@20 { 1125 1000 compatible = "ti,clkctrl"; 1001 + clock-output-names = "dsp_clkctrl"; 1126 1002 reg = <0x20 0x4>; 1127 1003 #clock-cells = <2>; 1128 1004 }; ··· 1131 1005 1132 1006 abe_cm: abe_cm@500 { 1133 1007 compatible = "ti,omap4-cm"; 1008 + clock-output-names = "abe_cm"; 1134 1009 reg = <0x500 0x100>; 1135 1010 #address-cells = <1>; 1136 1011 #size-cells = <1>; ··· 1139 1012 1140 1013 abe_clkctrl: clk@20 { 1141 1014 compatible = "ti,clkctrl"; 1015 + clock-output-names = "abe_clkctrl"; 1142 1016 reg = <0x20 0x64>; 1143 1017 #clock-cells = <2>; 1144 1018 }; ··· 1150 1022 &cm_core { 1151 1023 l3main1_cm: l3main1_cm@700 { 1152 1024 compatible = "ti,omap4-cm"; 1025 + clock-output-names = "l3main1_cm"; 1153 1026 reg = <0x700 0x100>; 1154 1027 #address-cells = <1>; 1155 1028 #size-cells = <1>; ··· 1158 1029 1159 1030 l3main1_clkctrl: clk@20 { 1160 1031 compatible = "ti,clkctrl"; 1032 + clock-output-names = "l3main1_clkctrl"; 1161 1033 reg = <0x20 0x4>; 1162 1034 #clock-cells = <2>; 1163 1035 }; ··· 1166 1036 1167 1037 l3main2_cm: l3main2_cm@800 { 1168 1038 compatible = "ti,omap4-cm"; 1039 + clock-output-names = "l3main2_cm"; 1169 1040 reg = <0x800 0x100>; 1170 1041 #address-cells = <1>; 1171 1042 #size-cells = <1>; ··· 1174 1043 1175 1044 l3main2_clkctrl: clk@20 { 1176 1045 compatible = "ti,clkctrl"; 1046 + clock-output-names = "l3main2_clkctrl"; 1177 1047 reg = <0x20 0x4>; 1178 1048 #clock-cells = <2>; 1179 1049 }; ··· 1182 1050 1183 1051 ipu_cm: ipu_cm@900 { 1184 1052 compatible = "ti,omap4-cm"; 1053 + clock-output-names = "ipu_cm"; 1185 1054 reg = <0x900 0x100>; 1186 1055 #address-cells = <1>; 1187 1056 #size-cells = <1>; ··· 1190 1057 1191 1058 ipu_clkctrl: clk@20 { 1192 1059 compatible = "ti,clkctrl"; 1060 + clock-output-names = "ipu_clkctrl"; 1193 1061 reg = <0x20 0x4>; 1194 1062 #clock-cells = <2>; 1195 1063 }; ··· 1198 1064 1199 1065 dma_cm: dma_cm@a00 { 1200 1066 compatible = "ti,omap4-cm"; 1067 + clock-output-names = "dma_cm"; 1201 1068 reg = <0xa00 0x100>; 1202 1069 #address-cells = <1>; 1203 1070 #size-cells = <1>; ··· 1206 1071 1207 1072 dma_clkctrl: clk@20 { 1208 1073 compatible = "ti,clkctrl"; 1074 + clock-output-names = "dma_clkctrl"; 1209 1075 reg = <0x20 0x4>; 1210 1076 #clock-cells = <2>; 1211 1077 }; ··· 1214 1078 1215 1079 emif_cm: emif_cm@b00 { 1216 1080 compatible = "ti,omap4-cm"; 1081 + clock-output-names = "emif_cm"; 1217 1082 reg = <0xb00 0x100>; 1218 1083 #address-cells = <1>; 1219 1084 #size-cells = <1>; ··· 1222 1085 1223 1086 emif_clkctrl: clk@20 { 1224 1087 compatible = "ti,clkctrl"; 1088 + clock-output-names = "emif_clkctrl"; 1225 1089 reg = <0x20 0x1c>; 1226 1090 #clock-cells = <2>; 1227 1091 }; ··· 1230 1092 1231 1093 l4cfg_cm: l4cfg_cm@d00 { 1232 1094 compatible = "ti,omap4-cm"; 1095 + clock-output-names = "l4cfg_cm"; 1233 1096 reg = <0xd00 0x100>; 1234 1097 #address-cells = <1>; 1235 1098 #size-cells = <1>; ··· 1238 1099 1239 1100 l4cfg_clkctrl: clk@20 { 1240 1101 compatible = "ti,clkctrl"; 1102 + clock-output-names = "l4cfg_clkctrl"; 1241 1103 reg = <0x20 0x14>; 1242 1104 #clock-cells = <2>; 1243 1105 }; ··· 1246 1106 1247 1107 l3instr_cm: l3instr_cm@e00 { 1248 1108 compatible = "ti,omap4-cm"; 1109 + clock-output-names = "l3instr_cm"; 1249 1110 reg = <0xe00 0x100>; 1250 1111 #address-cells = <1>; 1251 1112 #size-cells = <1>; ··· 1254 1113 1255 1114 l3instr_clkctrl: clk@20 { 1256 1115 compatible = "ti,clkctrl"; 1116 + clock-output-names = "l3instr_clkctrl"; 1257 1117 reg = <0x20 0xc>; 1258 1118 #clock-cells = <2>; 1259 1119 }; 1260 1120 }; 1261 1121 1262 - l4per_cm: l4per_cm@1000 { 1122 + l4per_cm: clock@1000 { 1263 1123 compatible = "ti,omap4-cm"; 1124 + clock-output-names = "l4per_cm"; 1264 1125 reg = <0x1000 0x200>; 1265 1126 #address-cells = <1>; 1266 1127 #size-cells = <1>; 1267 1128 ranges = <0 0x1000 0x200>; 1268 1129 1269 1130 l4per_clkctrl: clock@20 { 1270 - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; 1131 + compatible = "ti,clkctrl"; 1132 + clock-output-names = "l4per_clkctrl"; 1271 1133 reg = <0x20 0x15c>; 1272 1134 #clock-cells = <2>; 1273 1135 }; 1274 1136 1275 1137 l4sec_clkctrl: clock@1a0 { 1276 - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; 1138 + compatible = "ti,clkctrl"; 1139 + clock-output-names = "l4sec_clkctrl"; 1277 1140 reg = <0x1a0 0x3c>; 1278 1141 #clock-cells = <2>; 1279 1142 }; ··· 1285 1140 1286 1141 dss_cm: dss_cm@1400 { 1287 1142 compatible = "ti,omap4-cm"; 1143 + clock-output-names = "dss_cm"; 1288 1144 reg = <0x1400 0x100>; 1289 1145 #address-cells = <1>; 1290 1146 #size-cells = <1>; ··· 1293 1147 1294 1148 dss_clkctrl: clk@20 { 1295 1149 compatible = "ti,clkctrl"; 1150 + clock-output-names = "dss_clkctrl"; 1296 1151 reg = <0x20 0x4>; 1297 1152 #clock-cells = <2>; 1298 1153 }; ··· 1301 1154 1302 1155 gpu_cm: gpu_cm@1500 { 1303 1156 compatible = "ti,omap4-cm"; 1157 + clock-output-names = "gpu_cm"; 1304 1158 reg = <0x1500 0x100>; 1305 1159 #address-cells = <1>; 1306 1160 #size-cells = <1>; ··· 1309 1161 1310 1162 gpu_clkctrl: clk@20 { 1311 1163 compatible = "ti,clkctrl"; 1164 + clock-output-names = "gpu_clkctrl"; 1312 1165 reg = <0x20 0x4>; 1313 1166 #clock-cells = <2>; 1314 1167 }; ··· 1317 1168 1318 1169 l3init_cm: l3init_cm@1600 { 1319 1170 compatible = "ti,omap4-cm"; 1171 + clock-output-names = "l3init_cm"; 1320 1172 reg = <0x1600 0x100>; 1321 1173 #address-cells = <1>; 1322 1174 #size-cells = <1>; ··· 1325 1175 1326 1176 l3init_clkctrl: clk@20 { 1327 1177 compatible = "ti,clkctrl"; 1178 + clock-output-names = "l3init_clkctrl"; 1328 1179 reg = <0x20 0xd4>; 1329 1180 #clock-cells = <2>; 1330 1181 }; ··· 1335 1184 &prm { 1336 1185 wkupaon_cm: wkupaon_cm@1900 { 1337 1186 compatible = "ti,omap4-cm"; 1187 + clock-output-names = "wkupaon_cm"; 1338 1188 reg = <0x1900 0x100>; 1339 1189 #address-cells = <1>; 1340 1190 #size-cells = <1>; ··· 1343 1191 1344 1192 wkupaon_clkctrl: clk@20 { 1345 1193 compatible = "ti,clkctrl"; 1194 + clock-output-names = "wkupaon_clkctrl"; 1346 1195 reg = <0x20 0x5c>; 1347 1196 #clock-cells = <2>; 1348 1197 }; ··· 1354 1201 fref_xtal_ck: fref_xtal_ck { 1355 1202 #clock-cells = <0>; 1356 1203 compatible = "ti,gate-clock"; 1204 + clock-output-names = "fref_xtal_ck"; 1357 1205 clocks = <&sys_clkin>; 1358 1206 ti,bit-shift = <28>; 1359 1207 reg = <0x14>;

+1 -1

drivers/iommu/omap-iommu.c

··· 1661 1661 num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus", 1662 1662 sizeof(phandle)); 1663 1663 if (num_iommus < 0) 1664 - return 0; 1664 + return ERR_PTR(-ENODEV); 1665 1665 1666 1666 arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL); 1667 1667 if (!arch_data)

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