Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Merge branch 'net-stmmac-pcs-clean-up-pcs-interrupt-handling'
Russell King says:
====================
net: stmmac: pcs: clean up pcs interrupt handling
Clean up the stmmac PCS interrupt handling:
- Avoid promotion to unsigned long from unsigned int by defining PCS
register bits/fields using u32 macros.
- Pass struct stmmac_priv into the host_irq_status MAC core method.
- Move the existing PCS interrupt handler (dwmac_pcs_isr) into
stmmac_pcs.c, change it's arguments, use dev_info() rather than
pr_info()
- arrange to call phylink_pcs_change() on link state changes.
====================
Link: https://patch.msgid.link/aWOiOfDQkMXDwtPp@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+53
-57
+4
-3
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+4
-3
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
···
265
265
writel(pmt, ioaddr + GMAC_PMT);
266
266
}
267
267
268
-
static int dwmac1000_irq_status(struct mac_device_info *hw,
268
+
static int dwmac1000_irq_status(struct stmmac_priv *priv,
269
269
struct stmmac_extra_stats *x)
270
270
{
271
-
void __iomem *ioaddr = hw->pcsr;
271
+
void __iomem *ioaddr = priv->hw->pcsr;
272
272
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
273
273
u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
274
274
int ret = 0;
···
304
304
x->irq_rx_path_exit_lpi_mode_n++;
305
305
}
306
306
307
-
dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
307
+
if (intr_status & (PCS_ANE_IRQ | PCS_LINK_IRQ))
308
+
stmmac_integrated_pcs_irq(priv, intr_status, x);
308
309
309
310
return ret;
310
311
}
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+4
-3
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+4
-3
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
···
615
615
return ret;
616
616
}
617
617
618
-
static int dwmac4_irq_status(struct mac_device_info *hw,
618
+
static int dwmac4_irq_status(struct stmmac_priv *priv,
619
619
struct stmmac_extra_stats *x)
620
620
{
621
-
void __iomem *ioaddr = hw->pcsr;
621
+
void __iomem *ioaddr = priv->hw->pcsr;
622
622
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
623
623
u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
624
624
int ret = 0;
···
658
658
x->irq_rx_path_exit_lpi_mode_n++;
659
659
}
660
660
661
-
dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
661
+
if (intr_status & (PCS_ANE_IRQ | PCS_LINK_IRQ))
662
+
stmmac_integrated_pcs_irq(priv, intr_status, x);
662
663
663
664
return ret;
664
665
}
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+2
-2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
···
298
298
reg_space[i] = readl(ioaddr + i * 4);
299
299
}
300
300
301
-
static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
301
+
static int dwxgmac2_host_irq_status(struct stmmac_priv *priv,
302
302
struct stmmac_extra_stats *x)
303
303
{
304
-
void __iomem *ioaddr = hw->pcsr;
304
+
void __iomem *ioaddr = priv->hw->pcsr;
305
305
u32 stat, en;
306
306
int ret = 0;
307
307
+2
-2
drivers/net/ethernet/stmicro/stmmac/hwif.h
+2
-2
drivers/net/ethernet/stmicro/stmmac/hwif.h
···
354
354
/* Dump MAC registers */
355
355
void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
356
356
/* Handle extra events on specific interrupts hw dependent */
357
-
int (*host_irq_status)(struct mac_device_info *hw,
357
+
int (*host_irq_status)(struct stmmac_priv *priv,
358
358
struct stmmac_extra_stats *x);
359
359
/* Handle MTL interrupts */
360
360
int (*host_mtl_irq_status)(struct stmmac_priv *priv,
···
453
453
#define stmmac_dump_mac_regs(__priv, __args...) \
454
454
stmmac_do_void_callback(__priv, mac, dump_regs, __args)
455
455
#define stmmac_host_irq_status(__priv, __args...) \
456
-
stmmac_do_callback(__priv, mac, host_irq_status, __args)
456
+
stmmac_do_callback(__priv, mac, host_irq_status, __priv, __args)
457
457
#define stmmac_host_mtl_irq_status(__priv, __args...) \
458
458
stmmac_do_callback(__priv, mac, host_mtl_irq_status, __priv, __args)
459
459
#define stmmac_set_filter(__priv, __args...) \
+1
-1
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
6137
6137
6138
6138
/* To handle GMAC own interrupts */
6139
6139
if (priv->plat->core_type == DWMAC_CORE_GMAC || xmac) {
6140
-
int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
6140
+
int status = stmmac_host_irq_status(priv, &priv->xstats);
6141
6141
6142
6142
if (unlikely(status)) {
6143
6143
/* For LPI we need to save the tx status */
+22
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+22
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
···
45
45
.pcs_config = dwmac_integrated_pcs_config,
46
46
};
47
47
48
+
void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
49
+
struct stmmac_extra_stats *x)
50
+
{
51
+
struct stmmac_pcs *spcs = priv->integrated_pcs;
52
+
u32 val = readl(spcs->base + GMAC_AN_STATUS(0));
53
+
54
+
if (status & PCS_ANE_IRQ) {
55
+
x->irq_pcs_ane_n++;
56
+
if (val & GMAC_AN_STATUS_ANC)
57
+
dev_info(priv->device,
58
+
"PCS ANE process completed\n");
59
+
}
60
+
61
+
if (status & PCS_LINK_IRQ) {
62
+
x->irq_pcs_link_n++;
63
+
dev_info(priv->device, "PCS Link %s\n",
64
+
val & GMAC_AN_STATUS_LS ? "Up" : "Down");
65
+
66
+
phylink_pcs_change(&spcs->pcs, val & GMAC_AN_STATUS_LS);
67
+
}
68
+
}
69
+
48
70
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
49
71
u32 int_mask)
50
72
{
+17
-45
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+17
-45
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
···
25
25
#define GMAC_TBI(x) (x + 0x14) /* TBI extend status */
26
26
27
27
/* AN Configuration defines */
28
-
#define GMAC_AN_CTRL_RAN BIT(9) /* Restart Auto-Negotiation */
29
-
#define GMAC_AN_CTRL_ANE BIT(12) /* Auto-Negotiation Enable */
30
-
#define GMAC_AN_CTRL_ELE BIT(14) /* External Loopback Enable */
31
-
#define GMAC_AN_CTRL_ECD BIT(16) /* Enable Comma Detect */
32
-
#define GMAC_AN_CTRL_LR BIT(17) /* Lock to Reference */
33
-
#define GMAC_AN_CTRL_SGMRAL BIT(18) /* SGMII RAL Control */
28
+
#define GMAC_AN_CTRL_RAN BIT_U32(9) /* Restart Auto-Negotiation */
29
+
#define GMAC_AN_CTRL_ANE BIT_U32(12) /* Auto-Negotiation Enable */
30
+
#define GMAC_AN_CTRL_ELE BIT_U32(14) /* External Loopback Enable */
31
+
#define GMAC_AN_CTRL_ECD BIT_U32(16) /* Enable Comma Detect */
32
+
#define GMAC_AN_CTRL_LR BIT_U32(17) /* Lock to Reference */
33
+
#define GMAC_AN_CTRL_SGMRAL BIT_U32(18) /* SGMII RAL Control */
34
34
35
35
/* AN Status defines */
36
-
#define GMAC_AN_STATUS_LS BIT(2) /* Link Status 0:down 1:up */
37
-
#define GMAC_AN_STATUS_ANA BIT(3) /* Auto-Negotiation Ability */
38
-
#define GMAC_AN_STATUS_ANC BIT(5) /* Auto-Negotiation Complete */
39
-
#define GMAC_AN_STATUS_ES BIT(8) /* Extended Status */
36
+
#define GMAC_AN_STATUS_LS BIT_U32(2) /* Link Status 0:down 1:up */
37
+
#define GMAC_AN_STATUS_ANA BIT_U32(3) /* Auto-Negotiation Ability */
38
+
#define GMAC_AN_STATUS_ANC BIT_U32(5) /* Auto-Negotiation Complete */
39
+
#define GMAC_AN_STATUS_ES BIT_U32(8) /* Extended Status */
40
40
41
41
/* ADV and LPA defines */
42
-
#define GMAC_ANE_FD BIT(5)
43
-
#define GMAC_ANE_HD BIT(6)
44
-
#define GMAC_ANE_PSE GENMASK(8, 7)
42
+
#define GMAC_ANE_FD BIT_U32(5)
43
+
#define GMAC_ANE_HD BIT_U32(6)
44
+
#define GMAC_ANE_PSE GENMASK_U32(8, 7)
45
45
#define GMAC_ANE_PSE_SHIFT 7
46
-
#define GMAC_ANE_RFE GENMASK(13, 12)
46
+
#define GMAC_ANE_RFE GENMASK_U32(13, 12)
47
47
#define GMAC_ANE_RFE_SHIFT 12
48
-
#define GMAC_ANE_ACK BIT(14)
48
+
#define GMAC_ANE_ACK BIT_U32(14)
49
49
50
50
struct stmmac_priv;
51
51
···
62
62
return container_of(pcs, struct stmmac_pcs, pcs);
63
63
}
64
64
65
+
void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
66
+
struct stmmac_extra_stats *x);
65
67
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
66
68
u32 int_mask);
67
-
68
-
/**
69
-
* dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR
70
-
* @ioaddr: IO registers pointer
71
-
* @reg: Base address of the AN Control Register.
72
-
* @intr_status: GMAC core interrupt status
73
-
* @x: pointer to log these events as stats
74
-
* Description: it is the ISR for PCS events: Auto-Negotiation Completed and
75
-
* Link status.
76
-
*/
77
-
static inline void dwmac_pcs_isr(void __iomem *ioaddr, u32 reg,
78
-
unsigned int intr_status,
79
-
struct stmmac_extra_stats *x)
80
-
{
81
-
u32 val = readl(ioaddr + GMAC_AN_STATUS(reg));
82
-
83
-
if (intr_status & PCS_ANE_IRQ) {
84
-
x->irq_pcs_ane_n++;
85
-
if (val & GMAC_AN_STATUS_ANC)
86
-
pr_info("stmmac_pcs: ANE process completed\n");
87
-
}
88
-
89
-
if (intr_status & PCS_LINK_IRQ) {
90
-
x->irq_pcs_link_n++;
91
-
if (val & GMAC_AN_STATUS_LS)
92
-
pr_info("stmmac_pcs: Link Up\n");
93
-
else
94
-
pr_info("stmmac_pcs: Link Down\n");
95
-
}
96
-
}
97
69
98
70
/**
99
71
* dwmac_ctrl_ane - To program the AN Control Register.